Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date         : Mon Jul 15 21:31:43 2024
| Host         : Viviana running 64-bit major release  (build 9200)
| Command      : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
| Design       : CPU
| Device       : xc7a35tfgg484-1
| Speed File   : -1
| Design State : Fully Routed
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Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max violations: <unlimited>
             Violations found: 13
+----------+----------+-----------------------------------------------------+------------+
| Rule     | Severity | Description                                         | Violations |
+----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning  | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1          |
| DPIP-1   | Warning  | Input pipelining                                    | 6          |
| DPOP-1   | Warning  | PREG Output pipelining                              | 3          |
| DPOP-2   | Warning  | MREG Output pipelining                              | 3          |
+----------+----------+-----------------------------------------------------+------------+

2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties  
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
Related violations: <none>

DPIP-1#1 Warning
Input pipelining  
DSP execution/alu/result0 input execution/alu/result0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#2 Warning
Input pipelining  
DSP execution/alu/result0 input execution/alu/result0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#3 Warning
Input pipelining  
DSP execution/alu/result0__0 input execution/alu/result0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#4 Warning
Input pipelining  
DSP execution/alu/result0__0 input execution/alu/result0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#5 Warning
Input pipelining  
DSP execution/alu/result0__1 input execution/alu/result0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#6 Warning
Input pipelining  
DSP execution/alu/result0__1 input execution/alu/result0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPOP-1#1 Warning
PREG Output pipelining  
DSP execution/alu/result0 output execution/alu/result0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>

DPOP-1#2 Warning
PREG Output pipelining  
DSP execution/alu/result0__0 output execution/alu/result0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>

DPOP-1#3 Warning
PREG Output pipelining  
DSP execution/alu/result0__1 output execution/alu/result0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>

DPOP-2#1 Warning
MREG Output pipelining  
DSP execution/alu/result0 multiplier stage execution/alu/result0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#2 Warning
MREG Output pipelining  
DSP execution/alu/result0__0 multiplier stage execution/alu/result0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#3 Warning
MREG Output pipelining  
DSP execution/alu/result0__1 multiplier stage execution/alu/result0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>


