Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date         : Mon Jul 15 21:31:55 2024
| Host         : Viviana running 64-bit major release  (build 9200)
| Command      : report_timing_summary -max_paths 10 -report_unconstrained -file CPU_timing_summary_routed.rpt -pb CPU_timing_summary_routed.pb -rpx CPU_timing_summary_routed.rpx -warn_on_violation
| Design       : CPU
| Device       : 7a35t-fgg484
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule      Severity  Description      Violations  
--------  --------  ---------------  ----------  
SYNTH-10  Warning   Wide multiplier  3           

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (1)
6. checking no_output_delay (12)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (1)
------------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (12)
--------------------------------
 There are 12 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      3.719        0.000                      0                35779        0.055        0.000                      0                35779        3.000        0.000                       0                 18138  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                         Waveform(ns)       Period(ns)      Frequency(MHz)
-----                         ------------       ----------      --------------
hardware_clk                  {0.000 5.000}      10.000          100.000         
  clk_out1_phase_locked_loop  {0.000 10.000}     20.000          50.000          
  clkfbout_phase_locked_loop  {0.000 10.000}     20.000          50.000          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
hardware_clk                                                                                                                                                                    3.000        0.000                       0                     1  
  clk_out1_phase_locked_loop        3.719        0.000                      0                35779        0.055        0.000                      0                35779        9.500        0.000                       0                 18134  
  clkfbout_phase_locked_loop                                                                                                                                                   17.845        0.000                       0                     3  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock    
----------    ----------    --------    


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group                  From Clock                  To Clock                  
----------                  ----------                  --------                  
(none)                      clk_out1_phase_locked_loop                              
(none)                      clkfbout_phase_locked_loop                              
(none)                                                  clk_out1_phase_locked_loop  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  hardware_clk
  To Clock:  hardware_clk

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        3.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         hardware_clk
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { hardware_clk }

Check Type        Corner  Lib Pin           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     PLLE2_ADV/CLKIN1  n/a            1.249         10.000      8.751      PLLE2_ADV_X1Y0  pll/inst/plle2_adv_inst/CLKIN1
Max Period        n/a     PLLE2_ADV/CLKIN1  n/a            52.633        10.000      42.633     PLLE2_ADV_X1Y0  pll/inst/plle2_adv_inst/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1  n/a            2.000         5.000       3.000      PLLE2_ADV_X1Y0  pll/inst/plle2_adv_inst/CLKIN1
Low Pulse Width   Fast    PLLE2_ADV/CLKIN1  n/a            2.000         5.000       3.000      PLLE2_ADV_X1Y0  pll/inst/plle2_adv_inst/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1  n/a            2.000         5.000       3.000      PLLE2_ADV_X1Y0  pll/inst/plle2_adv_inst/CLKIN1
High Pulse Width  Fast    PLLE2_ADV/CLKIN1  n/a            2.000         5.000       3.000      PLLE2_ADV_X1Y0  pll/inst/plle2_adv_inst/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_phase_locked_loop
  To Clock:  clk_out1_phase_locked_loop

Setup :            0  Failing Endpoints,  Worst Slack        3.719ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.055ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        9.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.719ns  (required time - arrival time)
  Source:                 write_back/WB_register_write_destination_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            memory_access/MEM_ALU_result_reg[30]_rep/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        15.999ns  (logic 8.309ns (51.935%)  route 7.690ns (48.065%))
  Logic Levels:           13  (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT6=3)
  Clock Path Skew:        -0.108ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.956ns = ( 18.044 - 20.000 ) 
    Source Clock Delay      (SCD):    -2.353ns
    Clock Pessimism Removal (CPR):    -0.505ns
  Clock Uncertainty:      0.108ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.623    -2.353    write_back/clk_out1
    SLICE_X5Y53          FDRE                                         r  write_back/WB_register_write_destination_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y53          FDRE (Prop_fdre_C_Q)         0.456    -1.897 r  write_back/WB_register_write_destination_reg[2]/Q
                         net (fo=26, routed)          1.478    -0.419    write_back/Q[2]
    SLICE_X3Y54          LUT4 (Prop_lut4_I0_O)        0.152    -0.267 r  write_back/result0_i_55/O
                         net (fo=1, routed)           0.640     0.373    write_back/result0_i_55_n_0
    SLICE_X3Y53          LUT6 (Prop_lut6_I2_O)        0.332     0.705 r  write_back/result0_i_34/O
                         net (fo=34, routed)          1.251     1.956    memory_access/result0__0_0
    SLICE_X15Y45         LUT6 (Prop_lut6_I4_O)        0.124     2.080 f  memory_access/result0__0_i_22/O
                         net (fo=2, routed)           0.654     2.734    execution/result0__0_3
    SLICE_X12Y45         LUT3 (Prop_lut3_I2_O)        0.124     2.858 r  execution/result0__0_i_16/O
                         net (fo=141, routed)         1.215     4.073    execution/alu/ALU_in1[1]
    DSP48_X0Y13          DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
                                                      4.036     8.109 r  execution/alu/result0__0/PCOUT[47]
                         net (fo=1, routed)           0.002     8.111    execution/alu/result0__0_n_106
    DSP48_X0Y14          DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
                                                      1.518     9.629 r  execution/alu/result0__1/P[0]
                         net (fo=2, routed)           0.794    10.423    execution/alu/result0__1_n_105
    SLICE_X11Y35         LUT2 (Prop_lut2_I0_O)        0.124    10.547 r  execution/alu/i__carry_i_3__0/O
                         net (fo=1, routed)           0.000    10.547    execution/alu/i__carry_i_3__0_n_0
    SLICE_X11Y35         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550    11.097 r  execution/alu/result0_inferred__11/i__carry/CO[3]
                         net (fo=1, routed)           0.000    11.097    execution/alu/result0_inferred__11/i__carry_n_0
    SLICE_X11Y36         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114    11.211 r  execution/alu/result0_inferred__11/i__carry__0/CO[3]
                         net (fo=1, routed)           0.000    11.211    execution/alu/result0_inferred__11/i__carry__0_n_0
    SLICE_X11Y37         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114    11.325 r  execution/alu/result0_inferred__11/i__carry__1/CO[3]
                         net (fo=1, routed)           0.000    11.325    execution/alu/result0_inferred__11/i__carry__1_n_0
    SLICE_X11Y38         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239    11.564 r  execution/alu/result0_inferred__11/i__carry__2/O[2]
                         net (fo=1, routed)           0.667    12.231    execution/alu/result0_inferred__11/i__carry__2_n_5
    SLICE_X5Y38          LUT4 (Prop_lut4_I3_O)        0.302    12.533 r  execution/alu/MEM_ALU_result[30]_i_3/O
                         net (fo=2, routed)           0.506    13.039    execution/alu/MEM_ALU_result[30]_i_3_n_0
    SLICE_X4Y38          LUT6 (Prop_lut6_I2_O)        0.124    13.163 r  execution/alu/MEM_ALU_result[30]_rep_i_1/O
                         net (fo=1, routed)           0.483    13.646    memory_access/MEM_ALU_result_reg[30]_rep_29
    SLICE_X5Y40          FDRE                                         r  memory_access/MEM_ALU_result_reg[30]_rep/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                     20.000    20.000 r  
    R4                                                0.000    20.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000    20.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430    21.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181    22.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    14.862 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    16.438    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    16.529 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.515    18.044    memory_access/clk_out1
    SLICE_X5Y40          FDRE                                         r  memory_access/MEM_ALU_result_reg[30]_rep/C
                         clock pessimism             -0.505    17.539    
                         clock uncertainty           -0.108    17.431    
    SLICE_X5Y40          FDRE (Setup_fdre_C_D)       -0.067    17.364    memory_access/MEM_ALU_result_reg[30]_rep
  -------------------------------------------------------------------
                         required time                         17.364    
                         arrival time                         -13.646    
  -------------------------------------------------------------------
                         slack                                  3.719    

Slack (MET) :             3.762ns  (required time - arrival time)
  Source:                 write_back/WB_register_write_destination_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            memory_access/MEM_ALU_result_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        16.051ns  (logic 8.415ns (52.427%)  route 7.636ns (47.573%))
  Logic Levels:           13  (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT6=4)
  Clock Path Skew:        -0.109ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.957ns = ( 18.043 - 20.000 ) 
    Source Clock Delay      (SCD):    -2.353ns
    Clock Pessimism Removal (CPR):    -0.505ns
  Clock Uncertainty:      0.108ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.623    -2.353    write_back/clk_out1
    SLICE_X5Y53          FDRE                                         r  write_back/WB_register_write_destination_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y53          FDRE (Prop_fdre_C_Q)         0.456    -1.897 r  write_back/WB_register_write_destination_reg[2]/Q
                         net (fo=26, routed)          1.478    -0.419    write_back/Q[2]
    SLICE_X3Y54          LUT4 (Prop_lut4_I0_O)        0.152    -0.267 r  write_back/result0_i_55/O
                         net (fo=1, routed)           0.640     0.373    write_back/result0_i_55_n_0
    SLICE_X3Y53          LUT6 (Prop_lut6_I2_O)        0.332     0.705 r  write_back/result0_i_34/O
                         net (fo=34, routed)          1.251     1.956    memory_access/result0__0_0
    SLICE_X15Y45         LUT6 (Prop_lut6_I4_O)        0.124     2.080 f  memory_access/result0__0_i_22/O
                         net (fo=2, routed)           0.654     2.734    execution/result0__0_3
    SLICE_X12Y45         LUT3 (Prop_lut3_I2_O)        0.124     2.858 r  execution/result0__0_i_16/O
                         net (fo=141, routed)         1.215     4.073    execution/alu/ALU_in1[1]
    DSP48_X0Y13          DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
                                                      4.036     8.109 r  execution/alu/result0__0/PCOUT[47]
                         net (fo=1, routed)           0.002     8.111    execution/alu/result0__0_n_106
    DSP48_X0Y14          DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
                                                      1.518     9.629 r  execution/alu/result0__1/P[0]
                         net (fo=2, routed)           0.794    10.423    execution/alu/result0__1_n_105
    SLICE_X11Y35         LUT2 (Prop_lut2_I0_O)        0.124    10.547 r  execution/alu/i__carry_i_3__0/O
                         net (fo=1, routed)           0.000    10.547    execution/alu/i__carry_i_3__0_n_0
    SLICE_X11Y35         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550    11.097 r  execution/alu/result0_inferred__11/i__carry/CO[3]
                         net (fo=1, routed)           0.000    11.097    execution/alu/result0_inferred__11/i__carry_n_0
    SLICE_X11Y36         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114    11.211 r  execution/alu/result0_inferred__11/i__carry__0/CO[3]
                         net (fo=1, routed)           0.000    11.211    execution/alu/result0_inferred__11/i__carry__0_n_0
    SLICE_X11Y37         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334    11.545 r  execution/alu/result0_inferred__11/i__carry__1/O[1]
                         net (fo=1, routed)           0.683    12.228    execution/alu/result0_inferred__11/i__carry__1_n_6
    SLICE_X5Y37          LUT4 (Prop_lut4_I3_O)        0.303    12.531 r  execution/alu/MEM_ALU_result[25]_i_11/O
                         net (fo=1, routed)           0.469    13.000    execution/alu/MEM_ALU_result[25]_i_11_n_0
    SLICE_X2Y39          LUT6 (Prop_lut6_I5_O)        0.124    13.124 r  execution/alu/MEM_ALU_result[25]_i_4/O
                         net (fo=1, routed)           0.449    13.574    execution/alu/MEM_ALU_result[25]_i_4_n_0
    SLICE_X4Y38          LUT6 (Prop_lut6_I3_O)        0.124    13.698 r  execution/alu/MEM_ALU_result[25]_i_1/O
                         net (fo=1, routed)           0.000    13.698    memory_access/prev_ALU_result[25]
    SLICE_X4Y38          FDRE                                         r  memory_access/MEM_ALU_result_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                     20.000    20.000 r  
    R4                                                0.000    20.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000    20.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430    21.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181    22.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    14.862 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    16.438    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    16.529 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.514    18.043    memory_access/clk_out1
    SLICE_X4Y38          FDRE                                         r  memory_access/MEM_ALU_result_reg[25]/C
                         clock pessimism             -0.505    17.538    
                         clock uncertainty           -0.108    17.430    
    SLICE_X4Y38          FDRE (Setup_fdre_C_D)        0.029    17.459    memory_access/MEM_ALU_result_reg[25]
  -------------------------------------------------------------------
                         required time                         17.459    
                         arrival time                         -13.698    
  -------------------------------------------------------------------
                         slack                                  3.762    

Slack (MET) :             3.782ns  (required time - arrival time)
  Source:                 write_back/WB_register_write_destination_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            memory_access/MEM_ALU_result_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        16.035ns  (logic 8.283ns (51.657%)  route 7.752ns (48.343%))
  Logic Levels:           12  (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT6=4)
  Clock Path Skew:        -0.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.955ns = ( 18.045 - 20.000 ) 
    Source Clock Delay      (SCD):    -2.353ns
    Clock Pessimism Removal (CPR):    -0.505ns
  Clock Uncertainty:      0.108ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.623    -2.353    write_back/clk_out1
    SLICE_X5Y53          FDRE                                         r  write_back/WB_register_write_destination_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y53          FDRE (Prop_fdre_C_Q)         0.456    -1.897 r  write_back/WB_register_write_destination_reg[2]/Q
                         net (fo=26, routed)          1.478    -0.419    write_back/Q[2]
    SLICE_X3Y54          LUT4 (Prop_lut4_I0_O)        0.152    -0.267 r  write_back/result0_i_55/O
                         net (fo=1, routed)           0.640     0.373    write_back/result0_i_55_n_0
    SLICE_X3Y53          LUT6 (Prop_lut6_I2_O)        0.332     0.705 r  write_back/result0_i_34/O
                         net (fo=34, routed)          1.251     1.956    memory_access/result0__0_0
    SLICE_X15Y45         LUT6 (Prop_lut6_I4_O)        0.124     2.080 f  memory_access/result0__0_i_22/O
                         net (fo=2, routed)           0.654     2.734    execution/result0__0_3
    SLICE_X12Y45         LUT3 (Prop_lut3_I2_O)        0.124     2.858 r  execution/result0__0_i_16/O
                         net (fo=141, routed)         1.215     4.073    execution/alu/ALU_in1[1]
    DSP48_X0Y13          DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
                                                      4.036     8.109 r  execution/alu/result0__0/PCOUT[47]
                         net (fo=1, routed)           0.002     8.111    execution/alu/result0__0_n_106
    DSP48_X0Y14          DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
                                                      1.518     9.629 r  execution/alu/result0__1/P[0]
                         net (fo=2, routed)           0.794    10.423    execution/alu/result0__1_n_105
    SLICE_X11Y35         LUT2 (Prop_lut2_I0_O)        0.124    10.547 r  execution/alu/i__carry_i_3__0/O
                         net (fo=1, routed)           0.000    10.547    execution/alu/i__carry_i_3__0_n_0
    SLICE_X11Y35         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550    11.097 r  execution/alu/result0_inferred__11/i__carry/CO[3]
                         net (fo=1, routed)           0.000    11.097    execution/alu/result0_inferred__11/i__carry_n_0
    SLICE_X11Y36         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.313    11.410 r  execution/alu/result0_inferred__11/i__carry__0/O[3]
                         net (fo=1, routed)           0.559    11.969    execution/alu/result0_inferred__11/i__carry__0_n_4
    SLICE_X6Y36          LUT4 (Prop_lut4_I3_O)        0.306    12.275 r  execution/alu/MEM_ALU_result[23]_i_11/O
                         net (fo=1, routed)           0.702    12.977    execution/alu/MEM_ALU_result[23]_i_11_n_0
    SLICE_X3Y40          LUT6 (Prop_lut6_I5_O)        0.124    13.101 r  execution/alu/MEM_ALU_result[23]_i_4/O
                         net (fo=1, routed)           0.456    13.557    execution/alu/MEM_ALU_result[23]_i_4_n_0
    SLICE_X5Y42          LUT6 (Prop_lut6_I3_O)        0.124    13.681 r  execution/alu/MEM_ALU_result[23]_i_1/O
                         net (fo=1, routed)           0.000    13.681    memory_access/prev_ALU_result[23]
    SLICE_X5Y42          FDRE                                         r  memory_access/MEM_ALU_result_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                     20.000    20.000 r  
    R4                                                0.000    20.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000    20.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430    21.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181    22.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    14.862 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    16.438    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    16.529 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.516    18.045    memory_access/clk_out1
    SLICE_X5Y42          FDRE                                         r  memory_access/MEM_ALU_result_reg[23]/C
                         clock pessimism             -0.505    17.540    
                         clock uncertainty           -0.108    17.432    
    SLICE_X5Y42          FDRE (Setup_fdre_C_D)        0.031    17.463    memory_access/MEM_ALU_result_reg[23]
  -------------------------------------------------------------------
                         required time                         17.463    
                         arrival time                         -13.681    
  -------------------------------------------------------------------
                         slack                                  3.782    

Slack (MET) :             3.822ns  (required time - arrival time)
  Source:                 write_back/WB_register_write_destination_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            memory_access/MEM_ALU_result_reg[29]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        15.993ns  (logic 8.529ns (53.331%)  route 7.464ns (46.669%))
  Logic Levels:           14  (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.109ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.957ns = ( 18.043 - 20.000 ) 
    Source Clock Delay      (SCD):    -2.353ns
    Clock Pessimism Removal (CPR):    -0.505ns
  Clock Uncertainty:      0.108ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.623    -2.353    write_back/clk_out1
    SLICE_X5Y53          FDRE                                         r  write_back/WB_register_write_destination_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y53          FDRE (Prop_fdre_C_Q)         0.456    -1.897 r  write_back/WB_register_write_destination_reg[2]/Q
                         net (fo=26, routed)          1.478    -0.419    write_back/Q[2]
    SLICE_X3Y54          LUT4 (Prop_lut4_I0_O)        0.152    -0.267 r  write_back/result0_i_55/O
                         net (fo=1, routed)           0.640     0.373    write_back/result0_i_55_n_0
    SLICE_X3Y53          LUT6 (Prop_lut6_I2_O)        0.332     0.705 r  write_back/result0_i_34/O
                         net (fo=34, routed)          1.251     1.956    memory_access/result0__0_0
    SLICE_X15Y45         LUT6 (Prop_lut6_I4_O)        0.124     2.080 f  memory_access/result0__0_i_22/O
                         net (fo=2, routed)           0.654     2.734    execution/result0__0_3
    SLICE_X12Y45         LUT3 (Prop_lut3_I2_O)        0.124     2.858 r  execution/result0__0_i_16/O
                         net (fo=141, routed)         1.215     4.073    execution/alu/ALU_in1[1]
    DSP48_X0Y13          DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
                                                      4.036     8.109 r  execution/alu/result0__0/PCOUT[47]
                         net (fo=1, routed)           0.002     8.111    execution/alu/result0__0_n_106
    DSP48_X0Y14          DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
                                                      1.518     9.629 r  execution/alu/result0__1/P[0]
                         net (fo=2, routed)           0.794    10.423    execution/alu/result0__1_n_105
    SLICE_X11Y35         LUT2 (Prop_lut2_I0_O)        0.124    10.547 r  execution/alu/i__carry_i_3__0/O
                         net (fo=1, routed)           0.000    10.547    execution/alu/i__carry_i_3__0_n_0
    SLICE_X11Y35         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550    11.097 r  execution/alu/result0_inferred__11/i__carry/CO[3]
                         net (fo=1, routed)           0.000    11.097    execution/alu/result0_inferred__11/i__carry_n_0
    SLICE_X11Y36         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114    11.211 r  execution/alu/result0_inferred__11/i__carry__0/CO[3]
                         net (fo=1, routed)           0.000    11.211    execution/alu/result0_inferred__11/i__carry__0_n_0
    SLICE_X11Y37         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114    11.325 r  execution/alu/result0_inferred__11/i__carry__1/CO[3]
                         net (fo=1, routed)           0.000    11.325    execution/alu/result0_inferred__11/i__carry__1_n_0
    SLICE_X11Y38         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334    11.659 r  execution/alu/result0_inferred__11/i__carry__2/O[1]
                         net (fo=1, routed)           0.671    12.330    execution/alu/result0_inferred__11/i__carry__2_n_6
    SLICE_X5Y38          LUT4 (Prop_lut4_I3_O)        0.303    12.633 r  execution/alu/MEM_ALU_result[29]_i_10/O
                         net (fo=1, routed)           0.438    13.070    execution/alu/MEM_ALU_result[29]_i_10_n_0
    SLICE_X3Y39          LUT5 (Prop_lut5_I4_O)        0.124    13.194 r  execution/alu/MEM_ALU_result[29]_i_4/O
                         net (fo=1, routed)           0.321    13.515    execution/alu/MEM_ALU_result[29]_i_4_n_0
    SLICE_X4Y38          LUT6 (Prop_lut6_I3_O)        0.124    13.639 r  execution/alu/MEM_ALU_result[29]_i_1/O
                         net (fo=1, routed)           0.000    13.639    memory_access/prev_ALU_result[29]
    SLICE_X4Y38          FDRE                                         r  memory_access/MEM_ALU_result_reg[29]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                     20.000    20.000 r  
    R4                                                0.000    20.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000    20.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430    21.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181    22.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    14.862 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    16.438    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    16.529 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.514    18.043    memory_access/clk_out1
    SLICE_X4Y38          FDRE                                         r  memory_access/MEM_ALU_result_reg[29]/C
                         clock pessimism             -0.505    17.538    
                         clock uncertainty           -0.108    17.430    
    SLICE_X4Y38          FDRE (Setup_fdre_C_D)        0.031    17.461    memory_access/MEM_ALU_result_reg[29]
  -------------------------------------------------------------------
                         required time                         17.461    
                         arrival time                         -13.639    
  -------------------------------------------------------------------
                         slack                                  3.822    

Slack (MET) :             3.883ns  (required time - arrival time)
  Source:                 write_back/WB_register_write_destination_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            memory_access/MEM_ALU_result_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        15.980ns  (logic 8.301ns (51.947%)  route 7.679ns (48.053%))
  Logic Levels:           12  (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT6=4)
  Clock Path Skew:        -0.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.955ns = ( 18.045 - 20.000 ) 
    Source Clock Delay      (SCD):    -2.353ns
    Clock Pessimism Removal (CPR):    -0.505ns
  Clock Uncertainty:      0.108ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.623    -2.353    write_back/clk_out1
    SLICE_X5Y53          FDRE                                         r  write_back/WB_register_write_destination_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y53          FDRE (Prop_fdre_C_Q)         0.456    -1.897 r  write_back/WB_register_write_destination_reg[2]/Q
                         net (fo=26, routed)          1.478    -0.419    write_back/Q[2]
    SLICE_X3Y54          LUT4 (Prop_lut4_I0_O)        0.152    -0.267 r  write_back/result0_i_55/O
                         net (fo=1, routed)           0.640     0.373    write_back/result0_i_55_n_0
    SLICE_X3Y53          LUT6 (Prop_lut6_I2_O)        0.332     0.705 r  write_back/result0_i_34/O
                         net (fo=34, routed)          1.251     1.956    memory_access/result0__0_0
    SLICE_X15Y45         LUT6 (Prop_lut6_I4_O)        0.124     2.080 f  memory_access/result0__0_i_22/O
                         net (fo=2, routed)           0.654     2.734    execution/result0__0_3
    SLICE_X12Y45         LUT3 (Prop_lut3_I2_O)        0.124     2.858 r  execution/result0__0_i_16/O
                         net (fo=141, routed)         1.215     4.073    execution/alu/ALU_in1[1]
    DSP48_X0Y13          DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
                                                      4.036     8.109 r  execution/alu/result0__0/PCOUT[47]
                         net (fo=1, routed)           0.002     8.111    execution/alu/result0__0_n_106
    DSP48_X0Y14          DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
                                                      1.518     9.629 r  execution/alu/result0__1/P[0]
                         net (fo=2, routed)           0.794    10.423    execution/alu/result0__1_n_105
    SLICE_X11Y35         LUT2 (Prop_lut2_I0_O)        0.124    10.547 r  execution/alu/i__carry_i_3__0/O
                         net (fo=1, routed)           0.000    10.547    execution/alu/i__carry_i_3__0_n_0
    SLICE_X11Y35         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550    11.097 r  execution/alu/result0_inferred__11/i__carry/CO[3]
                         net (fo=1, routed)           0.000    11.097    execution/alu/result0_inferred__11/i__carry_n_0
    SLICE_X11Y36         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334    11.431 r  execution/alu/result0_inferred__11/i__carry__0/O[1]
                         net (fo=1, routed)           0.691    12.122    execution/alu/result0_inferred__11/i__carry__0_n_6
    SLICE_X3Y37          LUT4 (Prop_lut4_I1_O)        0.303    12.425 r  execution/alu/MEM_ALU_result[21]_i_12/O
                         net (fo=1, routed)           0.498    12.923    execution/alu/MEM_ALU_result[21]_i_12_n_0
    SLICE_X0Y38          LUT6 (Prop_lut6_I5_O)        0.124    13.047 r  execution/alu/MEM_ALU_result[21]_i_4/O
                         net (fo=1, routed)           0.456    13.503    execution/alu/MEM_ALU_result[21]_i_4_n_0
    SLICE_X2Y38          LUT6 (Prop_lut6_I3_O)        0.124    13.627 r  execution/alu/MEM_ALU_result[21]_i_1/O
                         net (fo=1, routed)           0.000    13.627    memory_access/prev_ALU_result[21]
    SLICE_X2Y38          FDRE                                         r  memory_access/MEM_ALU_result_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                     20.000    20.000 r  
    R4                                                0.000    20.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000    20.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430    21.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181    22.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    14.862 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    16.438    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    16.529 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.516    18.045    memory_access/clk_out1
    SLICE_X2Y38          FDRE                                         r  memory_access/MEM_ALU_result_reg[21]/C
                         clock pessimism             -0.505    17.540    
                         clock uncertainty           -0.108    17.432    
    SLICE_X2Y38          FDRE (Setup_fdre_C_D)        0.077    17.509    memory_access/MEM_ALU_result_reg[21]
  -------------------------------------------------------------------
                         required time                         17.509    
                         arrival time                         -13.627    
  -------------------------------------------------------------------
                         slack                                  3.883    

Slack (MET) :             3.889ns  (required time - arrival time)
  Source:                 write_back/WB_register_write_destination_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            memory_access/MEM_ALU_result_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        15.928ns  (logic 8.511ns (53.435%)  route 7.417ns (46.565%))
  Logic Levels:           14  (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4)
  Clock Path Skew:        -0.108ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.956ns = ( 18.044 - 20.000 ) 
    Source Clock Delay      (SCD):    -2.353ns
    Clock Pessimism Removal (CPR):    -0.505ns
  Clock Uncertainty:      0.108ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.623    -2.353    write_back/clk_out1
    SLICE_X5Y53          FDRE                                         r  write_back/WB_register_write_destination_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y53          FDRE (Prop_fdre_C_Q)         0.456    -1.897 r  write_back/WB_register_write_destination_reg[2]/Q
                         net (fo=26, routed)          1.478    -0.419    write_back/Q[2]
    SLICE_X3Y54          LUT4 (Prop_lut4_I0_O)        0.152    -0.267 r  write_back/result0_i_55/O
                         net (fo=1, routed)           0.640     0.373    write_back/result0_i_55_n_0
    SLICE_X3Y53          LUT6 (Prop_lut6_I2_O)        0.332     0.705 r  write_back/result0_i_34/O
                         net (fo=34, routed)          1.251     1.956    memory_access/result0__0_0
    SLICE_X15Y45         LUT6 (Prop_lut6_I4_O)        0.124     2.080 f  memory_access/result0__0_i_22/O
                         net (fo=2, routed)           0.654     2.734    execution/result0__0_3
    SLICE_X12Y45         LUT3 (Prop_lut3_I2_O)        0.124     2.858 r  execution/result0__0_i_16/O
                         net (fo=141, routed)         1.215     4.073    execution/alu/ALU_in1[1]
    DSP48_X0Y13          DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
                                                      4.036     8.109 r  execution/alu/result0__0/PCOUT[47]
                         net (fo=1, routed)           0.002     8.111    execution/alu/result0__0_n_106
    DSP48_X0Y14          DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
                                                      1.518     9.629 r  execution/alu/result0__1/P[0]
                         net (fo=2, routed)           0.794    10.423    execution/alu/result0__1_n_105
    SLICE_X11Y35         LUT2 (Prop_lut2_I0_O)        0.124    10.547 r  execution/alu/i__carry_i_3__0/O
                         net (fo=1, routed)           0.000    10.547    execution/alu/i__carry_i_3__0_n_0
    SLICE_X11Y35         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550    11.097 r  execution/alu/result0_inferred__11/i__carry/CO[3]
                         net (fo=1, routed)           0.000    11.097    execution/alu/result0_inferred__11/i__carry_n_0
    SLICE_X11Y36         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114    11.211 r  execution/alu/result0_inferred__11/i__carry__0/CO[3]
                         net (fo=1, routed)           0.000    11.211    execution/alu/result0_inferred__11/i__carry__0_n_0
    SLICE_X11Y37         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114    11.325 r  execution/alu/result0_inferred__11/i__carry__1/CO[3]
                         net (fo=1, routed)           0.000    11.325    execution/alu/result0_inferred__11/i__carry__1_n_0
    SLICE_X11Y38         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.313    11.638 r  execution/alu/result0_inferred__11/i__carry__2/O[3]
                         net (fo=1, routed)           0.570    12.209    execution/alu/result0_inferred__11/i__carry__2_n_4
    SLICE_X6Y39          LUT5 (Prop_lut5_I0_O)        0.306    12.515 r  execution/alu/MEM_ALU_result[31]_i_16/O
                         net (fo=1, routed)           0.409    12.924    execution/alu/MEM_ALU_result[31]_i_16_n_0
    SLICE_X4Y39          LUT6 (Prop_lut6_I2_O)        0.124    13.048 r  execution/alu/MEM_ALU_result[31]_i_5/O
                         net (fo=1, routed)           0.403    13.451    execution/alu/MEM_ALU_result[31]_i_5_n_0
    SLICE_X5Y40          LUT6 (Prop_lut6_I3_O)        0.124    13.575 r  execution/alu/MEM_ALU_result[31]_i_1/O
                         net (fo=1, routed)           0.000    13.575    memory_access/prev_ALU_result[31]
    SLICE_X5Y40          FDRE                                         r  memory_access/MEM_ALU_result_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                     20.000    20.000 r  
    R4                                                0.000    20.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000    20.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430    21.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181    22.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    14.862 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    16.438    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    16.529 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.515    18.044    memory_access/clk_out1
    SLICE_X5Y40          FDRE                                         r  memory_access/MEM_ALU_result_reg[31]/C
                         clock pessimism             -0.505    17.539    
                         clock uncertainty           -0.108    17.431    
    SLICE_X5Y40          FDRE (Setup_fdre_C_D)        0.032    17.463    memory_access/MEM_ALU_result_reg[31]
  -------------------------------------------------------------------
                         required time                         17.463    
                         arrival time                         -13.575    
  -------------------------------------------------------------------
                         slack                                  3.889    

Slack (MET) :             3.980ns  (required time - arrival time)
  Source:                 write_back/WB_register_write_destination_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            memory_access/MEM_ALU_result_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        15.835ns  (logic 8.413ns (53.128%)  route 7.422ns (46.872%))
  Logic Levels:           14  (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.108ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.956ns = ( 18.044 - 20.000 ) 
    Source Clock Delay      (SCD):    -2.353ns
    Clock Pessimism Removal (CPR):    -0.505ns
  Clock Uncertainty:      0.108ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.623    -2.353    write_back/clk_out1
    SLICE_X5Y53          FDRE                                         r  write_back/WB_register_write_destination_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y53          FDRE (Prop_fdre_C_Q)         0.456    -1.897 r  write_back/WB_register_write_destination_reg[2]/Q
                         net (fo=26, routed)          1.478    -0.419    write_back/Q[2]
    SLICE_X3Y54          LUT4 (Prop_lut4_I0_O)        0.152    -0.267 r  write_back/result0_i_55/O
                         net (fo=1, routed)           0.640     0.373    write_back/result0_i_55_n_0
    SLICE_X3Y53          LUT6 (Prop_lut6_I2_O)        0.332     0.705 r  write_back/result0_i_34/O
                         net (fo=34, routed)          1.251     1.956    memory_access/result0__0_0
    SLICE_X15Y45         LUT6 (Prop_lut6_I4_O)        0.124     2.080 f  memory_access/result0__0_i_22/O
                         net (fo=2, routed)           0.654     2.734    execution/result0__0_3
    SLICE_X12Y45         LUT3 (Prop_lut3_I2_O)        0.124     2.858 r  execution/result0__0_i_16/O
                         net (fo=141, routed)         1.215     4.073    execution/alu/ALU_in1[1]
    DSP48_X0Y13          DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
                                                      4.036     8.109 r  execution/alu/result0__0/PCOUT[47]
                         net (fo=1, routed)           0.002     8.111    execution/alu/result0__0_n_106
    DSP48_X0Y14          DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
                                                      1.518     9.629 r  execution/alu/result0__1/P[0]
                         net (fo=2, routed)           0.794    10.423    execution/alu/result0__1_n_105
    SLICE_X11Y35         LUT2 (Prop_lut2_I0_O)        0.124    10.547 r  execution/alu/i__carry_i_3__0/O
                         net (fo=1, routed)           0.000    10.547    execution/alu/i__carry_i_3__0_n_0
    SLICE_X11Y35         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550    11.097 r  execution/alu/result0_inferred__11/i__carry/CO[3]
                         net (fo=1, routed)           0.000    11.097    execution/alu/result0_inferred__11/i__carry_n_0
    SLICE_X11Y36         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114    11.211 r  execution/alu/result0_inferred__11/i__carry__0/CO[3]
                         net (fo=1, routed)           0.000    11.211    execution/alu/result0_inferred__11/i__carry__0_n_0
    SLICE_X11Y37         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114    11.325 r  execution/alu/result0_inferred__11/i__carry__1/CO[3]
                         net (fo=1, routed)           0.000    11.325    execution/alu/result0_inferred__11/i__carry__1_n_0
    SLICE_X11Y38         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.222    11.547 r  execution/alu/result0_inferred__11/i__carry__2/O[0]
                         net (fo=1, routed)           0.661    12.208    execution/alu/result0_inferred__11/i__carry__2_n_7
    SLICE_X7Y39          LUT4 (Prop_lut4_I3_O)        0.299    12.507 r  execution/alu/MEM_ALU_result[28]_i_12/O
                         net (fo=1, routed)           0.436    12.943    execution/alu/MEM_ALU_result[28]_i_12_n_0
    SLICE_X4Y40          LUT5 (Prop_lut5_I4_O)        0.124    13.067 r  execution/alu/MEM_ALU_result[28]_i_4/O
                         net (fo=1, routed)           0.291    13.358    execution/alu/MEM_ALU_result[28]_i_4_n_0
    SLICE_X5Y40          LUT6 (Prop_lut6_I3_O)        0.124    13.482 r  execution/alu/MEM_ALU_result[28]_i_1/O
                         net (fo=1, routed)           0.000    13.482    memory_access/prev_ALU_result[28]
    SLICE_X5Y40          FDRE                                         r  memory_access/MEM_ALU_result_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                     20.000    20.000 r  
    R4                                                0.000    20.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000    20.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430    21.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181    22.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    14.862 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    16.438    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    16.529 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.515    18.044    memory_access/clk_out1
    SLICE_X5Y40          FDRE                                         r  memory_access/MEM_ALU_result_reg[28]/C
                         clock pessimism             -0.505    17.539    
                         clock uncertainty           -0.108    17.431    
    SLICE_X5Y40          FDRE (Setup_fdre_C_D)        0.031    17.462    memory_access/MEM_ALU_result_reg[28]
  -------------------------------------------------------------------
                         required time                         17.462    
                         arrival time                         -13.482    
  -------------------------------------------------------------------
                         slack                                  3.980    

Slack (MET) :             4.081ns  (required time - arrival time)
  Source:                 write_back/WB_register_write_destination_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            memory_access/MEM_ALU_result_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        15.732ns  (logic 8.185ns (52.028%)  route 7.547ns (47.972%))
  Logic Levels:           12  (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT6=4)
  Clock Path Skew:        -0.111ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.959ns = ( 18.041 - 20.000 ) 
    Source Clock Delay      (SCD):    -2.353ns
    Clock Pessimism Removal (CPR):    -0.505ns
  Clock Uncertainty:      0.108ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.623    -2.353    write_back/clk_out1
    SLICE_X5Y53          FDRE                                         r  write_back/WB_register_write_destination_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y53          FDRE (Prop_fdre_C_Q)         0.456    -1.897 r  write_back/WB_register_write_destination_reg[2]/Q
                         net (fo=26, routed)          1.478    -0.419    write_back/Q[2]
    SLICE_X3Y54          LUT4 (Prop_lut4_I0_O)        0.152    -0.267 r  write_back/result0_i_55/O
                         net (fo=1, routed)           0.640     0.373    write_back/result0_i_55_n_0
    SLICE_X3Y53          LUT6 (Prop_lut6_I2_O)        0.332     0.705 r  write_back/result0_i_34/O
                         net (fo=34, routed)          1.251     1.956    memory_access/result0__0_0
    SLICE_X15Y45         LUT6 (Prop_lut6_I4_O)        0.124     2.080 f  memory_access/result0__0_i_22/O
                         net (fo=2, routed)           0.654     2.734    execution/result0__0_3
    SLICE_X12Y45         LUT3 (Prop_lut3_I2_O)        0.124     2.858 r  execution/result0__0_i_16/O
                         net (fo=141, routed)         1.215     4.073    execution/alu/ALU_in1[1]
    DSP48_X0Y13          DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
                                                      4.036     8.109 r  execution/alu/result0__0/PCOUT[47]
                         net (fo=1, routed)           0.002     8.111    execution/alu/result0__0_n_106
    DSP48_X0Y14          DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
                                                      1.518     9.629 r  execution/alu/result0__1/P[0]
                         net (fo=2, routed)           0.794    10.423    execution/alu/result0__1_n_105
    SLICE_X11Y35         LUT2 (Prop_lut2_I0_O)        0.124    10.547 r  execution/alu/i__carry_i_3__0/O
                         net (fo=1, routed)           0.000    10.547    execution/alu/i__carry_i_3__0_n_0
    SLICE_X11Y35         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550    11.097 r  execution/alu/result0_inferred__11/i__carry/CO[3]
                         net (fo=1, routed)           0.000    11.097    execution/alu/result0_inferred__11/i__carry_n_0
    SLICE_X11Y36         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.222    11.319 r  execution/alu/result0_inferred__11/i__carry__0/O[0]
                         net (fo=1, routed)           0.653    11.972    execution/alu/result0_inferred__11/i__carry__0_n_7
    SLICE_X5Y36          LUT4 (Prop_lut4_I3_O)        0.299    12.271 r  execution/alu/MEM_ALU_result[20]_i_12/O
                         net (fo=1, routed)           0.567    12.838    execution/alu/MEM_ALU_result[20]_i_12_n_0
    SLICE_X3Y34          LUT6 (Prop_lut6_I5_O)        0.124    12.962 r  execution/alu/MEM_ALU_result[20]_i_4/O
                         net (fo=1, routed)           0.292    13.254    execution/alu/MEM_ALU_result[20]_i_4_n_0
    SLICE_X3Y33          LUT6 (Prop_lut6_I3_O)        0.124    13.378 r  execution/alu/MEM_ALU_result[20]_i_1/O
                         net (fo=1, routed)           0.000    13.378    memory_access/prev_ALU_result[20]
    SLICE_X3Y33          FDRE                                         r  memory_access/MEM_ALU_result_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                     20.000    20.000 r  
    R4                                                0.000    20.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000    20.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430    21.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181    22.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    14.862 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    16.438    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    16.529 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.512    18.041    memory_access/clk_out1
    SLICE_X3Y33          FDRE                                         r  memory_access/MEM_ALU_result_reg[20]/C
                         clock pessimism             -0.505    17.536    
                         clock uncertainty           -0.108    17.428    
    SLICE_X3Y33          FDRE (Setup_fdre_C_D)        0.031    17.459    memory_access/MEM_ALU_result_reg[20]
  -------------------------------------------------------------------
                         required time                         17.459    
                         arrival time                         -13.378    
  -------------------------------------------------------------------
                         slack                                  4.081    

Slack (MET) :             4.090ns  (required time - arrival time)
  Source:                 write_back/WB_register_write_destination_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            memory_access/MEM_ALU_result_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        15.723ns  (logic 8.205ns (52.185%)  route 7.518ns (47.815%))
  Logic Levels:           12  (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT6=4)
  Clock Path Skew:        -0.109ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.957ns = ( 18.043 - 20.000 ) 
    Source Clock Delay      (SCD):    -2.353ns
    Clock Pessimism Removal (CPR):    -0.505ns
  Clock Uncertainty:      0.108ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.623    -2.353    write_back/clk_out1
    SLICE_X5Y53          FDRE                                         r  write_back/WB_register_write_destination_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y53          FDRE (Prop_fdre_C_Q)         0.456    -1.897 r  write_back/WB_register_write_destination_reg[2]/Q
                         net (fo=26, routed)          1.478    -0.419    write_back/Q[2]
    SLICE_X3Y54          LUT4 (Prop_lut4_I0_O)        0.152    -0.267 r  write_back/result0_i_55/O
                         net (fo=1, routed)           0.640     0.373    write_back/result0_i_55_n_0
    SLICE_X3Y53          LUT6 (Prop_lut6_I2_O)        0.332     0.705 r  write_back/result0_i_34/O
                         net (fo=34, routed)          1.251     1.956    memory_access/result0__0_0
    SLICE_X15Y45         LUT6 (Prop_lut6_I4_O)        0.124     2.080 f  memory_access/result0__0_i_22/O
                         net (fo=2, routed)           0.654     2.734    execution/result0__0_3
    SLICE_X12Y45         LUT3 (Prop_lut3_I2_O)        0.124     2.858 r  execution/result0__0_i_16/O
                         net (fo=141, routed)         1.215     4.073    execution/alu/ALU_in1[1]
    DSP48_X0Y13          DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
                                                      4.036     8.109 r  execution/alu/result0__0/PCOUT[47]
                         net (fo=1, routed)           0.002     8.111    execution/alu/result0__0_n_106
    DSP48_X0Y14          DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
                                                      1.518     9.629 r  execution/alu/result0__1/P[0]
                         net (fo=2, routed)           0.794    10.423    execution/alu/result0__1_n_105
    SLICE_X11Y35         LUT2 (Prop_lut2_I0_O)        0.124    10.547 r  execution/alu/i__carry_i_3__0/O
                         net (fo=1, routed)           0.000    10.547    execution/alu/i__carry_i_3__0_n_0
    SLICE_X11Y35         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550    11.097 r  execution/alu/result0_inferred__11/i__carry/CO[3]
                         net (fo=1, routed)           0.000    11.097    execution/alu/result0_inferred__11/i__carry_n_0
    SLICE_X11Y36         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239    11.336 r  execution/alu/result0_inferred__11/i__carry__0/O[2]
                         net (fo=1, routed)           0.709    12.045    execution/alu/result0_inferred__11/i__carry__0_n_5
    SLICE_X2Y36          LUT4 (Prop_lut4_I3_O)        0.302    12.347 r  execution/alu/MEM_ALU_result[22]_i_12/O
                         net (fo=1, routed)           0.291    12.638    execution/alu/MEM_ALU_result[22]_i_12_n_0
    SLICE_X0Y36          LUT6 (Prop_lut6_I5_O)        0.124    12.762 r  execution/alu/MEM_ALU_result[22]_i_4/O
                         net (fo=1, routed)           0.484    13.246    execution/alu/MEM_ALU_result[22]_i_4_n_0
    SLICE_X1Y36          LUT6 (Prop_lut6_I3_O)        0.124    13.370 r  execution/alu/MEM_ALU_result[22]_i_1/O
                         net (fo=1, routed)           0.000    13.370    memory_access/prev_ALU_result[22]
    SLICE_X1Y36          FDRE                                         r  memory_access/MEM_ALU_result_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                     20.000    20.000 r  
    R4                                                0.000    20.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000    20.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430    21.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181    22.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    14.862 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    16.438    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    16.529 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.514    18.043    memory_access/clk_out1
    SLICE_X1Y36          FDRE                                         r  memory_access/MEM_ALU_result_reg[22]/C
                         clock pessimism             -0.505    17.538    
                         clock uncertainty           -0.108    17.430    
    SLICE_X1Y36          FDRE (Setup_fdre_C_D)        0.029    17.459    memory_access/MEM_ALU_result_reg[22]
  -------------------------------------------------------------------
                         required time                         17.459    
                         arrival time                         -13.370    
  -------------------------------------------------------------------
                         slack                                  4.090    

Slack (MET) :             4.121ns  (required time - arrival time)
  Source:                 write_back/WB_register_write_destination_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            memory_access/MEM_ALU_result_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        15.745ns  (logic 8.273ns (52.545%)  route 7.472ns (47.455%))
  Logic Levels:           12  (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT6=4)
  Clock Path Skew:        -0.104ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.952ns = ( 18.048 - 20.000 ) 
    Source Clock Delay      (SCD):    -2.353ns
    Clock Pessimism Removal (CPR):    -0.505ns
  Clock Uncertainty:      0.108ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.623    -2.353    write_back/clk_out1
    SLICE_X5Y53          FDRE                                         r  write_back/WB_register_write_destination_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y53          FDRE (Prop_fdre_C_Q)         0.456    -1.897 r  write_back/WB_register_write_destination_reg[2]/Q
                         net (fo=26, routed)          1.478    -0.419    write_back/Q[2]
    SLICE_X3Y54          LUT4 (Prop_lut4_I0_O)        0.152    -0.267 r  write_back/result0_i_55/O
                         net (fo=1, routed)           0.640     0.373    write_back/result0_i_55_n_0
    SLICE_X3Y53          LUT6 (Prop_lut6_I2_O)        0.332     0.705 r  write_back/result0_i_34/O
                         net (fo=34, routed)          1.251     1.956    memory_access/result0__0_0
    SLICE_X15Y45         LUT6 (Prop_lut6_I4_O)        0.124     2.080 f  memory_access/result0__0_i_22/O
                         net (fo=2, routed)           0.654     2.734    execution/result0__0_3
    SLICE_X12Y45         LUT3 (Prop_lut3_I2_O)        0.124     2.858 r  execution/result0__0_i_16/O
                         net (fo=141, routed)         1.215     4.073    execution/alu/ALU_in1[1]
    DSP48_X0Y13          DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
                                                      4.036     8.109 r  execution/alu/result0__0/PCOUT[47]
                         net (fo=1, routed)           0.002     8.111    execution/alu/result0__0_n_106
    DSP48_X0Y14          DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
                                                      1.518     9.629 r  execution/alu/result0__1/P[0]
                         net (fo=2, routed)           0.794    10.423    execution/alu/result0__1_n_105
    SLICE_X11Y35         LUT2 (Prop_lut2_I0_O)        0.124    10.547 r  execution/alu/i__carry_i_3__0/O
                         net (fo=1, routed)           0.000    10.547    execution/alu/i__carry_i_3__0_n_0
    SLICE_X11Y35         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.550    11.097 r  execution/alu/result0_inferred__11/i__carry/CO[3]
                         net (fo=1, routed)           0.000    11.097    execution/alu/result0_inferred__11/i__carry_n_0
    SLICE_X11Y36         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114    11.211 r  execution/alu/result0_inferred__11/i__carry__0/CO[3]
                         net (fo=1, routed)           0.000    11.211    execution/alu/result0_inferred__11/i__carry__0_n_0
    SLICE_X11Y37         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.313    11.524 r  execution/alu/result0_inferred__11/i__carry__1/O[3]
                         net (fo=1, routed)           0.880    12.404    execution/alu/result0_inferred__11/i__carry__1_n_4
    SLICE_X2Y40          LUT6 (Prop_lut6_I3_O)        0.306    12.710 r  execution/alu/MEM_ALU_result[27]_i_4/O
                         net (fo=1, routed)           0.557    13.267    execution/alu/MEM_ALU_result[27]_i_4_n_0
    SLICE_X2Y43          LUT6 (Prop_lut6_I3_O)        0.124    13.391 r  execution/alu/MEM_ALU_result[27]_i_1/O
                         net (fo=1, routed)           0.000    13.391    memory_access/prev_ALU_result[27]
    SLICE_X2Y43          FDRE                                         r  memory_access/MEM_ALU_result_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                     20.000    20.000 r  
    R4                                                0.000    20.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000    20.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430    21.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181    22.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    14.862 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    16.438    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    16.529 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.519    18.048    memory_access/clk_out1
    SLICE_X2Y43          FDRE                                         r  memory_access/MEM_ALU_result_reg[27]/C
                         clock pessimism             -0.505    17.543    
                         clock uncertainty           -0.108    17.435    
    SLICE_X2Y43          FDRE (Setup_fdre_C_D)        0.077    17.512    memory_access/MEM_ALU_result_reg[27]
  -------------------------------------------------------------------
                         required time                         17.512    
                         arrival time                         -13.391    
  -------------------------------------------------------------------
                         slack                                  4.121    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 memory_access/MEM_memory_write_data_reg[19]_rep__5/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            data_memory/memory_data_reg[268435459][19]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        0.396ns  (logic 0.141ns (35.573%)  route 0.255ns (64.427%))
  Logic Levels:           0  
  Clock Path Skew:        0.271ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.293ns
    Source Clock Delay      (SCD):    -0.525ns
    Clock Pessimism Removal (CPR):    -0.039ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.562    -0.525    memory_access/clk_out1
    SLICE_X37Y51         FDRE                                         r  memory_access/MEM_memory_write_data_reg[19]_rep__5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y51         FDRE (Prop_fdre_C_Q)         0.141    -0.384 r  memory_access/MEM_memory_write_data_reg[19]_rep__5/Q
                         net (fo=64, routed)          0.255    -0.129    data_memory/memory_data_reg[268435457][31]_0[19]
    SLICE_X37Y47         FDRE                                         r  data_memory/memory_data_reg[268435459][19]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.833    -0.293    data_memory/clk_out1
    SLICE_X37Y47         FDRE                                         r  data_memory/memory_data_reg[268435459][19]/C
                         clock pessimism              0.039    -0.254    
    SLICE_X37Y47         FDRE (Hold_fdre_C_D)         0.070    -0.184    data_memory/memory_data_reg[268435459][19]
  -------------------------------------------------------------------
                         required time                          0.184    
                         arrival time                          -0.129    
  -------------------------------------------------------------------
                         slack                                  0.055    

Slack (MET) :             0.058ns  (arrival time - required time)
  Source:                 memory_access/MEM_memory_write_data_reg[10]_rep__5/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            data_memory/memory_data_reg[268435511][10]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        0.399ns  (logic 0.141ns (35.326%)  route 0.258ns (64.674%))
  Logic Levels:           0  
  Clock Path Skew:        0.271ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.293ns
    Source Clock Delay      (SCD):    -0.525ns
    Clock Pessimism Removal (CPR):    -0.039ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.562    -0.525    memory_access/clk_out1
    SLICE_X32Y52         FDRE                                         r  memory_access/MEM_memory_write_data_reg[10]_rep__5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y52         FDRE (Prop_fdre_C_Q)         0.141    -0.384 r  memory_access/MEM_memory_write_data_reg[10]_rep__5/Q
                         net (fo=65, routed)          0.258    -0.126    data_memory/memory_data_reg[268435457][31]_0[10]
    SLICE_X39Y48         FDRE                                         r  data_memory/memory_data_reg[268435511][10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.833    -0.293    data_memory/clk_out1
    SLICE_X39Y48         FDRE                                         r  data_memory/memory_data_reg[268435511][10]/C
                         clock pessimism              0.039    -0.254    
    SLICE_X39Y48         FDRE (Hold_fdre_C_D)         0.070    -0.184    data_memory/memory_data_reg[268435511][10]
  -------------------------------------------------------------------
                         required time                          0.184    
                         arrival time                          -0.126    
  -------------------------------------------------------------------
                         slack                                  0.058    

Slack (MET) :             0.061ns  (arrival time - required time)
  Source:                 memory_access/MEM_memory_write_data_reg[30]_rep__4/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            data_memory/memory_data_reg[268435544][30]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        0.401ns  (logic 0.141ns (35.126%)  route 0.260ns (64.874%))
  Logic Levels:           0  
  Clock Path Skew:        0.271ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.293ns
    Source Clock Delay      (SCD):    -0.525ns
    Clock Pessimism Removal (CPR):    -0.039ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.562    -0.525    memory_access/clk_out1
    SLICE_X32Y52         FDRE                                         r  memory_access/MEM_memory_write_data_reg[30]_rep__4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y52         FDRE (Prop_fdre_C_Q)         0.141    -0.384 r  memory_access/MEM_memory_write_data_reg[30]_rep__4/Q
                         net (fo=64, routed)          0.260    -0.124    data_memory/memory_data_reg[268435521][31]_0[30]
    SLICE_X32Y49         FDRE                                         r  data_memory/memory_data_reg[268435544][30]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.833    -0.293    data_memory/clk_out1
    SLICE_X32Y49         FDRE                                         r  data_memory/memory_data_reg[268435544][30]/C
                         clock pessimism              0.039    -0.254    
    SLICE_X32Y49         FDRE (Hold_fdre_C_D)         0.070    -0.184    data_memory/memory_data_reg[268435544][30]
  -------------------------------------------------------------------
                         required time                          0.184    
                         arrival time                          -0.124    
  -------------------------------------------------------------------
                         slack                                  0.061    

Slack (MET) :             0.068ns  (arrival time - required time)
  Source:                 memory_access/MEM_memory_write_data_reg[10]_rep__5/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            data_memory/memory_data_reg[268435507][10]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        0.397ns  (logic 0.141ns (35.476%)  route 0.256ns (64.524%))
  Logic Levels:           0  
  Clock Path Skew:        0.271ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.293ns
    Source Clock Delay      (SCD):    -0.525ns
    Clock Pessimism Removal (CPR):    -0.039ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.562    -0.525    memory_access/clk_out1
    SLICE_X32Y52         FDRE                                         r  memory_access/MEM_memory_write_data_reg[10]_rep__5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y52         FDRE (Prop_fdre_C_Q)         0.141    -0.384 r  memory_access/MEM_memory_write_data_reg[10]_rep__5/Q
                         net (fo=65, routed)          0.256    -0.128    data_memory/memory_data_reg[268435457][31]_0[10]
    SLICE_X38Y49         FDRE                                         r  data_memory/memory_data_reg[268435507][10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.833    -0.293    data_memory/clk_out1
    SLICE_X38Y49         FDRE                                         r  data_memory/memory_data_reg[268435507][10]/C
                         clock pessimism              0.039    -0.254    
    SLICE_X38Y49         FDRE (Hold_fdre_C_D)         0.059    -0.195    data_memory/memory_data_reg[268435507][10]
  -------------------------------------------------------------------
                         required time                          0.195    
                         arrival time                          -0.128    
  -------------------------------------------------------------------
                         slack                                  0.068    

Slack (MET) :             0.076ns  (arrival time - required time)
  Source:                 memory_access/MEM_memory_write_data_reg[17]_rep__3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            data_memory/memory_data_reg[268435591][17]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        0.402ns  (logic 0.141ns (35.079%)  route 0.261ns (64.921%))
  Logic Levels:           0  
  Clock Path Skew:        0.256ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.309ns
    Source Clock Delay      (SCD):    -0.531ns
    Clock Pessimism Removal (CPR):    -0.034ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.556    -0.531    memory_access/clk_out1
    SLICE_X33Y31         FDRE                                         r  memory_access/MEM_memory_write_data_reg[17]_rep__3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y31         FDRE (Prop_fdre_C_Q)         0.141    -0.390 r  memory_access/MEM_memory_write_data_reg[17]_rep__3/Q
                         net (fo=64, routed)          0.261    -0.129    data_memory/memory_data_reg[268435585][31]_0[17]
    SLICE_X39Y26         FDRE                                         r  data_memory/memory_data_reg[268435591][17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.817    -0.309    data_memory/clk_out1
    SLICE_X39Y26         FDRE                                         r  data_memory/memory_data_reg[268435591][17]/C
                         clock pessimism              0.034    -0.275    
    SLICE_X39Y26         FDRE (Hold_fdre_C_D)         0.070    -0.205    data_memory/memory_data_reg[268435591][17]
  -------------------------------------------------------------------
                         required time                          0.205    
                         arrival time                          -0.129    
  -------------------------------------------------------------------
                         slack                                  0.076    

Slack (MET) :             0.080ns  (arrival time - required time)
  Source:                 memory_access/MEM_memory_write_data_reg[30]_rep__5/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            data_memory/memory_data_reg[268435463][30]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        0.418ns  (logic 0.141ns (33.733%)  route 0.277ns (66.267%))
  Logic Levels:           0  
  Clock Path Skew:        0.272ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.292ns
    Source Clock Delay      (SCD):    -0.525ns
    Clock Pessimism Removal (CPR):    -0.039ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.562    -0.525    memory_access/clk_out1
    SLICE_X28Y52         FDRE                                         r  memory_access/MEM_memory_write_data_reg[30]_rep__5/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y52         FDRE (Prop_fdre_C_Q)         0.141    -0.384 r  memory_access/MEM_memory_write_data_reg[30]_rep__5/Q
                         net (fo=64, routed)          0.277    -0.107    data_memory/memory_data_reg[268435457][31]_0[30]
    SLICE_X28Y47         FDRE                                         r  data_memory/memory_data_reg[268435463][30]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.834    -0.292    data_memory/clk_out1
    SLICE_X28Y47         FDRE                                         r  data_memory/memory_data_reg[268435463][30]/C
                         clock pessimism              0.039    -0.253    
    SLICE_X28Y47         FDRE (Hold_fdre_C_D)         0.066    -0.187    data_memory/memory_data_reg[268435463][30]
  -------------------------------------------------------------------
                         required time                          0.187    
                         arrival time                          -0.107    
  -------------------------------------------------------------------
                         slack                                  0.080    

Slack (MET) :             0.082ns  (arrival time - required time)
  Source:                 memory_access/MEM_memory_write_data_reg[13]_rep__0/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            data_memory/memory_data_reg[268435833][13]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        0.420ns  (logic 0.141ns (33.608%)  route 0.279ns (66.392%))
  Logic Levels:           0  
  Clock Path Skew:        0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.296ns
    Source Clock Delay      (SCD):    -0.530ns
    Clock Pessimism Removal (CPR):    -0.034ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.557    -0.530    memory_access/clk_out1
    SLICE_X35Y87         FDRE                                         r  memory_access/MEM_memory_write_data_reg[13]_rep__0/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y87         FDRE (Prop_fdre_C_Q)         0.141    -0.389 r  memory_access/MEM_memory_write_data_reg[13]_rep__0/Q
                         net (fo=64, routed)          0.279    -0.111    data_memory/memory_data_reg[268435777][31]_0[13]
    SLICE_X37Y94         FDRE                                         r  data_memory/memory_data_reg[268435833][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.829    -0.296    data_memory/clk_out1
    SLICE_X37Y94         FDRE                                         r  data_memory/memory_data_reg[268435833][13]/C
                         clock pessimism              0.034    -0.262    
    SLICE_X37Y94         FDRE (Hold_fdre_C_D)         0.070    -0.192    data_memory/memory_data_reg[268435833][13]
  -------------------------------------------------------------------
                         required time                          0.192    
                         arrival time                          -0.111    
  -------------------------------------------------------------------
                         slack                                  0.082    

Slack (MET) :             0.082ns  (arrival time - required time)
  Source:                 memory_access/MEM_memory_write_data_reg[17]_rep__2/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            data_memory/memory_data_reg[268435674][17]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        0.412ns  (logic 0.141ns (34.215%)  route 0.271ns (65.785%))
  Logic Levels:           0  
  Clock Path Skew:        0.260ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.305ns
    Source Clock Delay      (SCD):    -0.531ns
    Clock Pessimism Removal (CPR):    -0.034ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.556    -0.531    memory_access/clk_out1
    SLICE_X33Y31         FDRE                                         r  memory_access/MEM_memory_write_data_reg[17]_rep__2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y31         FDRE (Prop_fdre_C_Q)         0.141    -0.390 r  memory_access/MEM_memory_write_data_reg[17]_rep__2/Q
                         net (fo=64, routed)          0.271    -0.119    data_memory/memory_data_reg[268435649][31]_0[17]
    SLICE_X41Y28         FDRE                                         r  data_memory/memory_data_reg[268435674][17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.821    -0.305    data_memory/clk_out1
    SLICE_X41Y28         FDRE                                         r  data_memory/memory_data_reg[268435674][17]/C
                         clock pessimism              0.034    -0.271    
    SLICE_X41Y28         FDRE (Hold_fdre_C_D)         0.070    -0.201    data_memory/memory_data_reg[268435674][17]
  -------------------------------------------------------------------
                         required time                          0.201    
                         arrival time                          -0.119    
  -------------------------------------------------------------------
                         slack                                  0.082    

Slack (MET) :             0.089ns  (arrival time - required time)
  Source:                 memory_access/MEM_memory_write_data_reg[9]_rep__1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            data_memory/memory_data_reg[268435738][9]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        0.512ns  (logic 0.141ns (27.552%)  route 0.371ns (72.448%))
  Logic Levels:           0  
  Clock Path Skew:        0.352ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.206ns
    Source Clock Delay      (SCD):    -0.524ns
    Clock Pessimism Removal (CPR):    -0.034ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.563    -0.524    memory_access/clk_out1
    SLICE_X49Y90         FDRE                                         r  memory_access/MEM_memory_write_data_reg[9]_rep__1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y90         FDRE (Prop_fdre_C_Q)         0.141    -0.383 r  memory_access/MEM_memory_write_data_reg[9]_rep__1/Q
                         net (fo=64, routed)          0.371    -0.012    data_memory/memory_data_reg[268435713][31]_0[9]
    SLICE_X55Y100        FDRE                                         r  data_memory/memory_data_reg[268435738][9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.920    -0.206    data_memory/clk_out1
    SLICE_X55Y100        FDRE                                         r  data_memory/memory_data_reg[268435738][9]/C
                         clock pessimism              0.034    -0.172    
    SLICE_X55Y100        FDRE (Hold_fdre_C_D)         0.070    -0.102    data_memory/memory_data_reg[268435738][9]
  -------------------------------------------------------------------
                         required time                          0.102    
                         arrival time                          -0.012    
  -------------------------------------------------------------------
                         slack                                  0.089    

Slack (MET) :             0.092ns  (arrival time - required time)
  Source:                 memory_access/MEM_memory_write_data_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            data_memory/memory_data_reg[268435927][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk_out1_phase_locked_loop
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
  Data Path Delay:        0.514ns  (logic 0.141ns (27.427%)  route 0.373ns (72.573%))
  Logic Levels:           0  
  Clock Path Skew:        0.352ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.206ns
    Source Clock Delay      (SCD):    -0.524ns
    Clock Pessimism Removal (CPR):    -0.034ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.563    -0.524    memory_access/clk_out1
    SLICE_X11Y90         FDRE                                         r  memory_access/MEM_memory_write_data_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X11Y90         FDRE (Prop_fdre_C_Q)         0.141    -0.383 r  memory_access/MEM_memory_write_data_reg[3]/Q
                         net (fo=64, routed)          0.373    -0.010    data_memory/memory_data_reg[268435905][31]_0[3]
    SLICE_X9Y107         FDRE                                         r  data_memory/memory_data_reg[268435927][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.920    -0.206    data_memory/clk_out1
    SLICE_X9Y107         FDRE                                         r  data_memory/memory_data_reg[268435927][3]/C
                         clock pessimism              0.034    -0.172    
    SLICE_X9Y107         FDRE (Hold_fdre_C_D)         0.070    -0.102    data_memory/memory_data_reg[268435927][3]
  -------------------------------------------------------------------
                         required time                          0.102    
                         arrival time                          -0.010    
  -------------------------------------------------------------------
                         slack                                  0.092    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_phase_locked_loop
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { pll/inst/plle2_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFG/I             n/a            2.155         20.000      17.845     BUFGCTRL_X0Y0   pll/inst/clkout1_buf/I
Min Period        n/a     PLLE2_ADV/CLKOUT0  n/a            1.249         20.000      18.751     PLLE2_ADV_X1Y0  pll/inst/plle2_adv_inst/CLKOUT0
Min Period        n/a     FDRE/C             n/a            1.000         20.000      19.000     SLICE_X14Y47    data_memory/memory_data_reg[268435456][0]/C
Min Period        n/a     FDRE/C             n/a            1.000         20.000      19.000     SLICE_X59Y56    data_memory/memory_data_reg[268435456][10]/C
Min Period        n/a     FDRE/C             n/a            1.000         20.000      19.000     SLICE_X55Y55    data_memory/memory_data_reg[268435456][11]/C
Min Period        n/a     FDRE/C             n/a            1.000         20.000      19.000     SLICE_X43Y28    data_memory/memory_data_reg[268435456][12]/C
Min Period        n/a     FDRE/C             n/a            1.000         20.000      19.000     SLICE_X30Y29    data_memory/memory_data_reg[268435456][13]/C
Min Period        n/a     FDRE/C             n/a            1.000         20.000      19.000     SLICE_X2Y33     data_memory/memory_data_reg[268435456][14]/C
Min Period        n/a     FDRE/C             n/a            1.000         20.000      19.000     SLICE_X46Y38    data_memory/memory_data_reg[268435456][15]/C
Min Period        n/a     FDRE/C             n/a            1.000         20.000      19.000     SLICE_X2Y33     data_memory/memory_data_reg[268435456][16]/C
Max Period        n/a     PLLE2_ADV/CLKOUT0  n/a            160.000       20.000      140.000    PLLE2_ADV_X1Y0  pll/inst/plle2_adv_inst/CLKOUT0
Low Pulse Width   Slow    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X14Y47    data_memory/memory_data_reg[268435456][0]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X14Y47    data_memory/memory_data_reg[268435456][0]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X59Y56    data_memory/memory_data_reg[268435456][10]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X59Y56    data_memory/memory_data_reg[268435456][10]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X55Y55    data_memory/memory_data_reg[268435456][11]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X55Y55    data_memory/memory_data_reg[268435456][11]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X43Y28    data_memory/memory_data_reg[268435456][12]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X43Y28    data_memory/memory_data_reg[268435456][12]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X30Y29    data_memory/memory_data_reg[268435456][13]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X30Y29    data_memory/memory_data_reg[268435456][13]/C
High Pulse Width  Slow    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X14Y47    data_memory/memory_data_reg[268435456][0]/C
High Pulse Width  Fast    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X14Y47    data_memory/memory_data_reg[268435456][0]/C
High Pulse Width  Slow    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X59Y56    data_memory/memory_data_reg[268435456][10]/C
High Pulse Width  Fast    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X59Y56    data_memory/memory_data_reg[268435456][10]/C
High Pulse Width  Slow    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X55Y55    data_memory/memory_data_reg[268435456][11]/C
High Pulse Width  Fast    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X55Y55    data_memory/memory_data_reg[268435456][11]/C
High Pulse Width  Slow    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X43Y28    data_memory/memory_data_reg[268435456][12]/C
High Pulse Width  Fast    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X43Y28    data_memory/memory_data_reg[268435456][12]/C
High Pulse Width  Slow    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X30Y29    data_memory/memory_data_reg[268435456][13]/C
High Pulse Width  Fast    FDRE/C             n/a            0.500         10.000      9.500      SLICE_X30Y29    data_memory/memory_data_reg[268435456][13]/C



---------------------------------------------------------------------------------------------------
From Clock:  clkfbout_phase_locked_loop
  To Clock:  clkfbout_phase_locked_loop

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       17.845ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clkfbout_phase_locked_loop
Waveform(ns):       { 0.000 10.000 }
Period(ns):         20.000
Sources:            { pll/inst/plle2_adv_inst/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     BUFG/I              n/a            2.155         20.000      17.845     BUFGCTRL_X0Y1   pll/inst/clkf_buf/I
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         20.000      18.751     PLLE2_ADV_X1Y0  pll/inst/plle2_adv_inst/CLKFBOUT
Min Period  n/a     PLLE2_ADV/CLKFBIN   n/a            1.249         20.000      18.751     PLLE2_ADV_X1Y0  pll/inst/plle2_adv_inst/CLKFBIN
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        20.000      32.633     PLLE2_ADV_X1Y0  pll/inst/plle2_adv_inst/CLKFBIN
Max Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            160.000       20.000      140.000    PLLE2_ADV_X1Y0  pll/inst/plle2_adv_inst/CLKFBOUT



--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_phase_locked_loop
  To Clock:  

Max Delay            12 Endpoints
Min Delay            12 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][1]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[1]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        7.325ns  (logic 4.053ns (55.326%)  route 3.272ns (44.674%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.569    -2.407    data_memory/clk_out1
    SLICE_X14Y43         FDRE                                         r  data_memory/memory_data_reg[268435460][1]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y43         FDRE (Prop_fdre_C_Q)         0.518    -1.889 r  data_memory/memory_data_reg[268435460][1]_lopt_replica/Q
                         net (fo=1, routed)           3.272     1.383    lopt_3
    P5                   OBUF (Prop_obuf_I_O)         3.535     4.918 r  bcd_control_OBUF[1]_inst/O
                         net (fo=0)                   0.000     4.918    bcd_control[1]
    P5                                                                r  bcd_control[1] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][2]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[2]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        6.876ns  (logic 4.045ns (58.829%)  route 2.831ns (41.171%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.553    -2.423    data_memory/clk_out1
    SLICE_X46Y28         FDRE                                         r  data_memory/memory_data_reg[268435460][2]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y28         FDRE (Prop_fdre_C_Q)         0.518    -1.905 r  data_memory/memory_data_reg[268435460][2]_lopt_replica/Q
                         net (fo=1, routed)           2.831     0.926    lopt_4
    V5                   OBUF (Prop_obuf_I_O)         3.527     4.453 r  bcd_control_OBUF[2]_inst/O
                         net (fo=0)                   0.000     4.453    bcd_control[2]
    V5                                                                r  bcd_control[2] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][6]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[6]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        6.494ns  (logic 4.010ns (61.739%)  route 2.485ns (38.261%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.639    -2.337    data_memory/clk_out1
    SLICE_X65Y49         FDRE                                         r  data_memory/memory_data_reg[268435460][6]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y49         FDRE (Prop_fdre_C_Q)         0.456    -1.881 r  data_memory/memory_data_reg[268435460][6]_lopt_replica/Q
                         net (fo=1, routed)           2.485     0.604    lopt_8
    W4                   OBUF (Prop_obuf_I_O)         3.554     4.157 r  bcd_control_OBUF[6]_inst/O
                         net (fo=0)                   0.000     4.157    bcd_control[6]
    W4                                                                r  bcd_control[6] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][0]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        6.309ns  (logic 3.997ns (63.348%)  route 2.313ns (36.652%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.572    -2.404    data_memory/clk_out1
    SLICE_X53Y49         FDRE                                         r  data_memory/memory_data_reg[268435460][0]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y49         FDRE (Prop_fdre_C_Q)         0.456    -1.948 r  data_memory/memory_data_reg[268435460][0]_lopt_replica/Q
                         net (fo=1, routed)           2.313     0.365    lopt
    N2                   OBUF (Prop_obuf_I_O)         3.541     3.906 r  bcd_control_OBUF[0]_inst/O
                         net (fo=0)                   0.000     3.906    bcd_control[0]
    N2                                                                r  bcd_control[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][9]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[9]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        6.009ns  (logic 4.152ns (69.110%)  route 1.856ns (30.890%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.625    -2.351    data_memory/clk_out1
    SLICE_X65Y57         FDRE                                         r  data_memory/memory_data_reg[268435460][9]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y57         FDRE (Prop_fdre_C_Q)         0.419    -1.932 r  data_memory/memory_data_reg[268435460][9]_lopt_replica/Q
                         net (fo=1, routed)           1.856    -0.076    lopt_11
    R1                   OBUF (Prop_obuf_I_O)         3.733     3.657 r  bcd_control_OBUF[9]_inst/O
                         net (fo=0)                   0.000     3.657    bcd_control[9]
    R1                                                                r  bcd_control[9] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][11]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[11]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.990ns  (logic 3.992ns (66.644%)  route 1.998ns (33.356%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.625    -2.351    data_memory/clk_out1
    SLICE_X65Y57         FDRE                                         r  data_memory/memory_data_reg[268435460][11]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y57         FDRE (Prop_fdre_C_Q)         0.456    -1.895 r  data_memory/memory_data_reg[268435460][11]_lopt_replica/Q
                         net (fo=1, routed)           1.998     0.103    lopt_2
    M2                   OBUF (Prop_obuf_I_O)         3.536     3.639 r  bcd_control_OBUF[11]_inst/O
                         net (fo=0)                   0.000     3.639    bcd_control[11]
    M2                                                                r  bcd_control[11] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][5]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[5]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.957ns  (logic 4.149ns (69.644%)  route 1.808ns (30.356%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.625    -2.351    data_memory/clk_out1
    SLICE_X65Y57         FDRE                                         r  data_memory/memory_data_reg[268435460][5]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y57         FDRE (Prop_fdre_C_Q)         0.419    -1.932 r  data_memory/memory_data_reg[268435460][5]_lopt_replica/Q
                         net (fo=1, routed)           1.808    -0.124    lopt_7
    P1                   OBUF (Prop_obuf_I_O)         3.730     3.606 r  bcd_control_OBUF[5]_inst/O
                         net (fo=0)                   0.000     3.606    bcd_control[5]
    P1                                                                r  bcd_control[5] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][7]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[7]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.910ns  (logic 4.006ns (67.792%)  route 1.903ns (32.208%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.636    -2.340    data_memory/clk_out1
    SLICE_X65Y40         FDRE                                         r  data_memory/memory_data_reg[268435460][7]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y40         FDRE (Prop_fdre_C_Q)         0.456    -1.884 r  data_memory/memory_data_reg[268435460][7]_lopt_replica/Q
                         net (fo=1, routed)           1.903     0.020    lopt_9
    V3                   OBUF (Prop_obuf_I_O)         3.550     3.570 r  bcd_control_OBUF[7]_inst/O
                         net (fo=0)                   0.000     3.570    bcd_control[7]
    V3                                                                r  bcd_control[7] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][3]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[3]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.912ns  (logic 4.012ns (67.860%)  route 1.900ns (32.140%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.624    -2.352    data_memory/clk_out1
    SLICE_X65Y28         FDRE                                         r  data_memory/memory_data_reg[268435460][3]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y28         FDRE (Prop_fdre_C_Q)         0.456    -1.896 r  data_memory/memory_data_reg[268435460][3]_lopt_replica/Q
                         net (fo=1, routed)           1.900     0.004    lopt_5
    U5                   OBUF (Prop_obuf_I_O)         3.556     3.560 r  bcd_control_OBUF[3]_inst/O
                         net (fo=0)                   0.000     3.560    bcd_control[3]
    U5                                                                r  bcd_control[3] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][4]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[4]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.903ns  (logic 4.011ns (67.953%)  route 1.892ns (32.047%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.501     1.501 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.253     2.754    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.728 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.655    -4.072    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -3.976 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.624    -2.352    data_memory/clk_out1
    SLICE_X65Y28         FDRE                                         r  data_memory/memory_data_reg[268435460][4]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y28         FDRE (Prop_fdre_C_Q)         0.456    -1.896 r  data_memory/memory_data_reg[268435460][4]_lopt_replica/Q
                         net (fo=1, routed)           1.892    -0.004    lopt_6
    T5                   OBUF (Prop_obuf_I_O)         3.555     3.551 r  bcd_control_OBUF[4]_inst/O
                         net (fo=0)                   0.000     3.551    bcd_control[4]
    T5                                                                r  bcd_control[4] (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][10]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[10]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.714ns  (logic 1.386ns (80.858%)  route 0.328ns (19.142%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.592    -0.495    data_memory/clk_out1
    SLICE_X65Y57         FDRE                                         r  data_memory/memory_data_reg[268435460][10]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y57         FDRE (Prop_fdre_C_Q)         0.141    -0.354 r  data_memory/memory_data_reg[268435460][10]_lopt_replica/Q
                         net (fo=1, routed)           0.328    -0.026    lopt_1
    P2                   OBUF (Prop_obuf_I_O)         1.245     1.219 r  bcd_control_OBUF[10]_inst/O
                         net (fo=0)                   0.000     1.219    bcd_control[10]
    P2                                                                r  bcd_control[10] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][8]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[8]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.809ns  (logic 1.450ns (80.180%)  route 0.358ns (19.820%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.585    -0.502    data_memory/clk_out1
    SLICE_X65Y28         FDRE                                         r  data_memory/memory_data_reg[268435460][8]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y28         FDRE (Prop_fdre_C_Q)         0.128    -0.374 r  data_memory/memory_data_reg[268435460][8]_lopt_replica/Q
                         net (fo=1, routed)           0.358    -0.016    lopt_10
    Y3                   OBUF (Prop_obuf_I_O)         1.322     1.306 r  bcd_control_OBUF[8]_inst/O
                         net (fo=0)                   0.000     1.306    bcd_control[8]
    Y3                                                                r  bcd_control[8] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][7]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[7]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.808ns  (logic 1.392ns (77.015%)  route 0.415ns (22.985%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.594    -0.493    data_memory/clk_out1
    SLICE_X65Y40         FDRE                                         r  data_memory/memory_data_reg[268435460][7]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y40         FDRE (Prop_fdre_C_Q)         0.141    -0.352 r  data_memory/memory_data_reg[268435460][7]_lopt_replica/Q
                         net (fo=1, routed)           0.415     0.063    lopt_9
    V3                   OBUF (Prop_obuf_I_O)         1.251     1.314 r  bcd_control_OBUF[7]_inst/O
                         net (fo=0)                   0.000     1.314    bcd_control[7]
    V3                                                                r  bcd_control[7] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][5]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[5]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.830ns  (logic 1.440ns (78.666%)  route 0.390ns (21.334%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.592    -0.495    data_memory/clk_out1
    SLICE_X65Y57         FDRE                                         r  data_memory/memory_data_reg[268435460][5]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y57         FDRE (Prop_fdre_C_Q)         0.128    -0.367 r  data_memory/memory_data_reg[268435460][5]_lopt_replica/Q
                         net (fo=1, routed)           0.390     0.023    lopt_7
    P1                   OBUF (Prop_obuf_I_O)         1.312     1.335 r  bcd_control_OBUF[5]_inst/O
                         net (fo=0)                   0.000     1.335    bcd_control[5]
    P1                                                                r  bcd_control[5] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][4]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[4]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.846ns  (logic 1.397ns (75.646%)  route 0.450ns (24.354%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.585    -0.502    data_memory/clk_out1
    SLICE_X65Y28         FDRE                                         r  data_memory/memory_data_reg[268435460][4]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y28         FDRE (Prop_fdre_C_Q)         0.141    -0.361 r  data_memory/memory_data_reg[268435460][4]_lopt_replica/Q
                         net (fo=1, routed)           0.450     0.088    lopt_6
    T5                   OBUF (Prop_obuf_I_O)         1.256     1.344 r  bcd_control_OBUF[4]_inst/O
                         net (fo=0)                   0.000     1.344    bcd_control[4]
    T5                                                                r  bcd_control[4] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][3]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[3]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.846ns  (logic 1.397ns (75.680%)  route 0.449ns (24.320%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.585    -0.502    data_memory/clk_out1
    SLICE_X65Y28         FDRE                                         r  data_memory/memory_data_reg[268435460][3]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y28         FDRE (Prop_fdre_C_Q)         0.141    -0.361 r  data_memory/memory_data_reg[268435460][3]_lopt_replica/Q
                         net (fo=1, routed)           0.449     0.088    lopt_5
    U5                   OBUF (Prop_obuf_I_O)         1.256     1.344 r  bcd_control_OBUF[3]_inst/O
                         net (fo=0)                   0.000     1.344    bcd_control[3]
    U5                                                                r  bcd_control[3] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][9]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[9]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.853ns  (logic 1.442ns (77.818%)  route 0.411ns (22.182%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.592    -0.495    data_memory/clk_out1
    SLICE_X65Y57         FDRE                                         r  data_memory/memory_data_reg[268435460][9]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y57         FDRE (Prop_fdre_C_Q)         0.128    -0.367 r  data_memory/memory_data_reg[268435460][9]_lopt_replica/Q
                         net (fo=1, routed)           0.411     0.044    lopt_11
    R1                   OBUF (Prop_obuf_I_O)         1.314     1.358 r  bcd_control_OBUF[9]_inst/O
                         net (fo=0)                   0.000     1.358    bcd_control[9]
    R1                                                                r  bcd_control[9] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][11]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[11]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.860ns  (logic 1.378ns (74.081%)  route 0.482ns (25.919%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.592    -0.495    data_memory/clk_out1
    SLICE_X65Y57         FDRE                                         r  data_memory/memory_data_reg[268435460][11]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y57         FDRE (Prop_fdre_C_Q)         0.141    -0.354 r  data_memory/memory_data_reg[268435460][11]_lopt_replica/Q
                         net (fo=1, routed)           0.482     0.128    lopt_2
    M2                   OBUF (Prop_obuf_I_O)         1.237     1.365 r  bcd_control_OBUF[11]_inst/O
                         net (fo=0)                   0.000     1.365    bcd_control[11]
    M2                                                                r  bcd_control[11] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][0]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.033ns  (logic 1.383ns (68.006%)  route 0.651ns (31.994%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.567    -0.520    data_memory/clk_out1
    SLICE_X53Y49         FDRE                                         r  data_memory/memory_data_reg[268435460][0]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y49         FDRE (Prop_fdre_C_Q)         0.141    -0.379 r  data_memory/memory_data_reg[268435460][0]_lopt_replica/Q
                         net (fo=1, routed)           0.651     0.271    lopt
    N2                   OBUF (Prop_obuf_I_O)         1.242     1.513 r  bcd_control_OBUF[0]_inst/O
                         net (fo=0)                   0.000     1.513    bcd_control[0]
    N2                                                                r  bcd_control[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 data_memory/memory_data_reg[268435460][6]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            bcd_control[6]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.071ns  (logic 1.395ns (67.368%)  route 0.676ns (32.632%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.269     0.269 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.440     0.709    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.614 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.501    -1.113    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.087 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.596    -0.491    data_memory/clk_out1
    SLICE_X65Y49         FDRE                                         r  data_memory/memory_data_reg[268435460][6]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y49         FDRE (Prop_fdre_C_Q)         0.141    -0.350 r  data_memory/memory_data_reg[268435460][6]_lopt_replica/Q
                         net (fo=1, routed)           0.676     0.326    lopt_8
    W4                   OBUF (Prop_obuf_I_O)         1.254     1.580 r  bcd_control_OBUF[6]_inst/O
                         net (fo=0)                   0.000     1.580    bcd_control[6]
    W4                                                                r  bcd_control[6] (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clkfbout_phase_locked_loop
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 pll/inst/plle2_adv_inst/CLKFBOUT
                            (clock source 'clkfbout_phase_locked_loop'  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            pll/inst/plle2_adv_inst/CLKFBIN
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.396ns  (logic 0.029ns (2.077%)  route 1.367ns (97.923%))
  Logic Levels:           1  (BUFG=1)
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.119ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clkfbout_phase_locked_loop fall edge)
                                                     10.000    10.000 f  
    R4                                                0.000    10.000 f  hardware_clk (IN)
                         net (fo=0)                   0.000    10.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457    10.457 f  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481    10.938    pll/inst/clk_in1_phase_locked_loop
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT)
                                                     -2.638     8.300 f  pll/inst/plle2_adv_inst/CLKFBOUT
                         net (fo=1, routed)           0.546     8.845    pll/inst/clkfbout_phase_locked_loop
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     8.874 f  pll/inst/clkf_buf/O
                         net (fo=1, routed)           0.822     9.696    pll/inst/clkfbout_buf_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV                                    f  pll/inst/plle2_adv_inst/CLKFBIN
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 pll/inst/plle2_adv_inst/CLKFBOUT
                            (clock source 'clkfbout_phase_locked_loop'  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            pll/inst/plle2_adv_inst/CLKFBIN
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.146ns  (logic 0.091ns (2.892%)  route 3.055ns (97.108%))
  Logic Levels:           1  (BUFG=1)
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.119ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clkfbout_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430     1.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181     2.611    pll/inst/clk_in1_phase_locked_loop
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT)
                                                     -7.750    -5.138 r  pll/inst/plle2_adv_inst/CLKFBOUT
                         net (fo=1, routed)           1.576    -3.562    pll/inst/clkfbout_phase_locked_loop
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091    -3.471 r  pll/inst/clkf_buf/O
                         net (fo=1, routed)           1.479    -1.992    pll/inst/clkfbout_buf_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV                                    r  pll/inst/plle2_adv_inst/CLKFBIN
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_phase_locked_loop

Max Delay         18132 Endpoints
Min Delay         18132 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 hardware_reset
                            (input port)
  Destination:            data_memory/memory_data_reg[268435868][14]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        16.057ns  (logic 1.650ns (10.274%)  route 14.408ns (89.726%))
  Logic Levels:           2  (IBUF=1 LUT2=1)
  Clock Path Skew:        -1.791ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.791ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    B22                                               0.000     0.000 r  hardware_reset (IN)
                         net (fo=0)                   0.000     0.000    hardware_reset
    B22                  IBUF (Prop_ibuf_I_O)         1.526     1.526 r  hardware_reset_IBUF_inst/O
                         net (fo=2, routed)           4.841     6.367    data_memory/memory_data_reg[268435457][0]_0
    SLICE_X65Y47         LUT2 (Prop_lut2_I0_O)        0.124     6.491 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       9.567    16.057    data_memory/reset
    SLICE_X3Y138         FDRE                                         r  data_memory/memory_data_reg[268435868][14]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430     1.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181     2.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    -5.138 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    -3.562    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    -3.471 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.680    -1.791    data_memory/clk_out1
    SLICE_X3Y138         FDRE                                         r  data_memory/memory_data_reg[268435868][14]/C

Slack:                    inf
  Source:                 hardware_reset
                            (input port)
  Destination:            data_memory/memory_data_reg[268435868][5]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        16.057ns  (logic 1.650ns (10.274%)  route 14.408ns (89.726%))
  Logic Levels:           2  (IBUF=1 LUT2=1)
  Clock Path Skew:        -1.791ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.791ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    B22                                               0.000     0.000 r  hardware_reset (IN)
                         net (fo=0)                   0.000     0.000    hardware_reset
    B22                  IBUF (Prop_ibuf_I_O)         1.526     1.526 r  hardware_reset_IBUF_inst/O
                         net (fo=2, routed)           4.841     6.367    data_memory/memory_data_reg[268435457][0]_0
    SLICE_X65Y47         LUT2 (Prop_lut2_I0_O)        0.124     6.491 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       9.567    16.057    data_memory/reset
    SLICE_X3Y138         FDRE                                         r  data_memory/memory_data_reg[268435868][5]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430     1.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181     2.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    -5.138 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    -3.562    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    -3.471 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.680    -1.791    data_memory/clk_out1
    SLICE_X3Y138         FDRE                                         r  data_memory/memory_data_reg[268435868][5]/C

Slack:                    inf
  Source:                 hardware_reset
                            (input port)
  Destination:            data_memory/memory_data_reg[268435845][3]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        16.034ns  (logic 1.650ns (10.289%)  route 14.384ns (89.711%))
  Logic Levels:           2  (IBUF=1 LUT2=1)
  Clock Path Skew:        -1.790ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.790ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    B22                                               0.000     0.000 r  hardware_reset (IN)
                         net (fo=0)                   0.000     0.000    hardware_reset
    B22                  IBUF (Prop_ibuf_I_O)         1.526     1.526 r  hardware_reset_IBUF_inst/O
                         net (fo=2, routed)           4.841     6.367    data_memory/memory_data_reg[268435457][0]_0
    SLICE_X65Y47         LUT2 (Prop_lut2_I0_O)        0.124     6.491 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       9.543    16.034    data_memory/reset
    SLICE_X3Y139         FDRE                                         r  data_memory/memory_data_reg[268435845][3]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430     1.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181     2.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    -5.138 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    -3.562    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    -3.471 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.681    -1.790    data_memory/clk_out1
    SLICE_X3Y139         FDRE                                         r  data_memory/memory_data_reg[268435845][3]/C

Slack:                    inf
  Source:                 hardware_reset
                            (input port)
  Destination:            data_memory/memory_data_reg[268435852][1]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        15.948ns  (logic 1.650ns (10.345%)  route 14.298ns (89.655%))
  Logic Levels:           2  (IBUF=1 LUT2=1)
  Clock Path Skew:        -1.791ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.791ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    B22                                               0.000     0.000 r  hardware_reset (IN)
                         net (fo=0)                   0.000     0.000    hardware_reset
    B22                  IBUF (Prop_ibuf_I_O)         1.526     1.526 r  hardware_reset_IBUF_inst/O
                         net (fo=2, routed)           4.841     6.367    data_memory/memory_data_reg[268435457][0]_0
    SLICE_X65Y47         LUT2 (Prop_lut2_I0_O)        0.124     6.491 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       9.457    15.948    data_memory/reset
    SLICE_X5Y139         FDRE                                         r  data_memory/memory_data_reg[268435852][1]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430     1.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181     2.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    -5.138 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    -3.562    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    -3.471 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.680    -1.791    data_memory/clk_out1
    SLICE_X5Y139         FDRE                                         r  data_memory/memory_data_reg[268435852][1]/C

Slack:                    inf
  Source:                 hardware_reset
                            (input port)
  Destination:            data_memory/memory_data_reg[268435852][3]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        15.948ns  (logic 1.650ns (10.345%)  route 14.298ns (89.655%))
  Logic Levels:           2  (IBUF=1 LUT2=1)
  Clock Path Skew:        -1.791ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.791ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    B22                                               0.000     0.000 r  hardware_reset (IN)
                         net (fo=0)                   0.000     0.000    hardware_reset
    B22                  IBUF (Prop_ibuf_I_O)         1.526     1.526 r  hardware_reset_IBUF_inst/O
                         net (fo=2, routed)           4.841     6.367    data_memory/memory_data_reg[268435457][0]_0
    SLICE_X65Y47         LUT2 (Prop_lut2_I0_O)        0.124     6.491 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       9.457    15.948    data_memory/reset
    SLICE_X5Y139         FDRE                                         r  data_memory/memory_data_reg[268435852][3]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430     1.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181     2.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    -5.138 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    -3.562    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    -3.471 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.680    -1.791    data_memory/clk_out1
    SLICE_X5Y139         FDRE                                         r  data_memory/memory_data_reg[268435852][3]/C

Slack:                    inf
  Source:                 hardware_reset
                            (input port)
  Destination:            data_memory/memory_data_reg[268435841][3]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        15.919ns  (logic 1.650ns (10.363%)  route 14.269ns (89.637%))
  Logic Levels:           2  (IBUF=1 LUT2=1)
  Clock Path Skew:        -1.792ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.792ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    B22                                               0.000     0.000 r  hardware_reset (IN)
                         net (fo=0)                   0.000     0.000    hardware_reset
    B22                  IBUF (Prop_ibuf_I_O)         1.526     1.526 r  hardware_reset_IBUF_inst/O
                         net (fo=2, routed)           4.841     6.367    data_memory/memory_data_reg[268435457][0]_0
    SLICE_X65Y47         LUT2 (Prop_lut2_I0_O)        0.124     6.491 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       9.428    15.919    data_memory/reset
    SLICE_X2Y137         FDRE                                         r  data_memory/memory_data_reg[268435841][3]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430     1.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181     2.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    -5.138 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    -3.562    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    -3.471 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.679    -1.792    data_memory/clk_out1
    SLICE_X2Y137         FDRE                                         r  data_memory/memory_data_reg[268435841][3]/C

Slack:                    inf
  Source:                 hardware_reset
                            (input port)
  Destination:            data_memory/memory_data_reg[268435871][11]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        15.919ns  (logic 1.650ns (10.363%)  route 14.269ns (89.637%))
  Logic Levels:           2  (IBUF=1 LUT2=1)
  Clock Path Skew:        -1.792ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.792ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    B22                                               0.000     0.000 r  hardware_reset (IN)
                         net (fo=0)                   0.000     0.000    hardware_reset
    B22                  IBUF (Prop_ibuf_I_O)         1.526     1.526 r  hardware_reset_IBUF_inst/O
                         net (fo=2, routed)           4.841     6.367    data_memory/memory_data_reg[268435457][0]_0
    SLICE_X65Y47         LUT2 (Prop_lut2_I0_O)        0.124     6.491 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       9.428    15.919    data_memory/reset
    SLICE_X3Y137         FDRE                                         r  data_memory/memory_data_reg[268435871][11]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430     1.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181     2.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    -5.138 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    -3.562    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    -3.471 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.679    -1.792    data_memory/clk_out1
    SLICE_X3Y137         FDRE                                         r  data_memory/memory_data_reg[268435871][11]/C

Slack:                    inf
  Source:                 hardware_reset
                            (input port)
  Destination:            data_memory/memory_data_reg[268435871][14]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        15.919ns  (logic 1.650ns (10.363%)  route 14.269ns (89.637%))
  Logic Levels:           2  (IBUF=1 LUT2=1)
  Clock Path Skew:        -1.792ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.792ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    B22                                               0.000     0.000 r  hardware_reset (IN)
                         net (fo=0)                   0.000     0.000    hardware_reset
    B22                  IBUF (Prop_ibuf_I_O)         1.526     1.526 r  hardware_reset_IBUF_inst/O
                         net (fo=2, routed)           4.841     6.367    data_memory/memory_data_reg[268435457][0]_0
    SLICE_X65Y47         LUT2 (Prop_lut2_I0_O)        0.124     6.491 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       9.428    15.919    data_memory/reset
    SLICE_X3Y137         FDRE                                         r  data_memory/memory_data_reg[268435871][14]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430     1.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181     2.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    -5.138 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    -3.562    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    -3.471 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.679    -1.792    data_memory/clk_out1
    SLICE_X3Y137         FDRE                                         r  data_memory/memory_data_reg[268435871][14]/C

Slack:                    inf
  Source:                 hardware_reset
                            (input port)
  Destination:            data_memory/memory_data_reg[268435871][5]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        15.919ns  (logic 1.650ns (10.363%)  route 14.269ns (89.637%))
  Logic Levels:           2  (IBUF=1 LUT2=1)
  Clock Path Skew:        -1.792ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.792ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    B22                                               0.000     0.000 r  hardware_reset (IN)
                         net (fo=0)                   0.000     0.000    hardware_reset
    B22                  IBUF (Prop_ibuf_I_O)         1.526     1.526 r  hardware_reset_IBUF_inst/O
                         net (fo=2, routed)           4.841     6.367    data_memory/memory_data_reg[268435457][0]_0
    SLICE_X65Y47         LUT2 (Prop_lut2_I0_O)        0.124     6.491 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       9.428    15.919    data_memory/reset
    SLICE_X3Y137         FDRE                                         r  data_memory/memory_data_reg[268435871][5]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430     1.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181     2.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    -5.138 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    -3.562    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    -3.471 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.679    -1.792    data_memory/clk_out1
    SLICE_X3Y137         FDRE                                         r  data_memory/memory_data_reg[268435871][5]/C

Slack:                    inf
  Source:                 hardware_reset
                            (input port)
  Destination:            data_memory/memory_data_reg[268435854][3]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        15.907ns  (logic 1.650ns (10.371%)  route 14.258ns (89.629%))
  Logic Levels:           2  (IBUF=1 LUT2=1)
  Clock Path Skew:        -1.791ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.791ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    B22                                               0.000     0.000 r  hardware_reset (IN)
                         net (fo=0)                   0.000     0.000    hardware_reset
    B22                  IBUF (Prop_ibuf_I_O)         1.526     1.526 r  hardware_reset_IBUF_inst/O
                         net (fo=2, routed)           4.841     6.367    data_memory/memory_data_reg[268435457][0]_0
    SLICE_X65Y47         LUT2 (Prop_lut2_I0_O)        0.124     6.491 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       9.417    15.907    data_memory/reset
    SLICE_X4Y140         FDRE                                         r  data_memory/memory_data_reg[268435854][3]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         1.430     1.430 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           1.181     2.611    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750    -5.138 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.576    -3.562    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    -3.471 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       1.680    -1.791    data_memory/clk_out1
    SLICE_X4Y140         FDRE                                         r  data_memory/memory_data_reg[268435854][3]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 pll/inst/plle2_adv_inst/LOCKED
                            (internal pin)
  Destination:            data_memory/memory_data_reg[268435486][4]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.085ns  (logic 0.045ns (4.146%)  route 1.040ns (95.854%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y0       PLLE2_ADV                    0.000     0.000 f  pll/inst/plle2_adv_inst/LOCKED
                         net (fo=2, routed)           0.394     0.394    data_memory/locked
    SLICE_X65Y47         LUT2 (Prop_lut2_I1_O)        0.045     0.439 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       0.647     1.085    data_memory/reset
    SLICE_X59Y47         FDRE                                         r  data_memory/memory_data_reg[268435486][4]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.865    -0.261    data_memory/clk_out1
    SLICE_X59Y47         FDRE                                         r  data_memory/memory_data_reg[268435486][4]/C

Slack:                    inf
  Source:                 pll/inst/plle2_adv_inst/LOCKED
                            (internal pin)
  Destination:            data_memory/memory_data_reg[268435528][10]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.090ns  (logic 0.045ns (4.129%)  route 1.045ns (95.871%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y0       PLLE2_ADV                    0.000     0.000 f  pll/inst/plle2_adv_inst/LOCKED
                         net (fo=2, routed)           0.394     0.394    data_memory/locked
    SLICE_X65Y47         LUT2 (Prop_lut2_I1_O)        0.045     0.439 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       0.651     1.090    data_memory/reset
    SLICE_X58Y47         FDRE                                         r  data_memory/memory_data_reg[268435528][10]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.865    -0.261    data_memory/clk_out1
    SLICE_X58Y47         FDRE                                         r  data_memory/memory_data_reg[268435528][10]/C

Slack:                    inf
  Source:                 pll/inst/plle2_adv_inst/LOCKED
                            (internal pin)
  Destination:            data_memory/memory_data_reg[268435528][4]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.090ns  (logic 0.045ns (4.129%)  route 1.045ns (95.871%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y0       PLLE2_ADV                    0.000     0.000 f  pll/inst/plle2_adv_inst/LOCKED
                         net (fo=2, routed)           0.394     0.394    data_memory/locked
    SLICE_X65Y47         LUT2 (Prop_lut2_I1_O)        0.045     0.439 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       0.651     1.090    data_memory/reset
    SLICE_X58Y47         FDRE                                         r  data_memory/memory_data_reg[268435528][4]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.865    -0.261    data_memory/clk_out1
    SLICE_X58Y47         FDRE                                         r  data_memory/memory_data_reg[268435528][4]/C

Slack:                    inf
  Source:                 pll/inst/plle2_adv_inst/LOCKED
                            (internal pin)
  Destination:            data_memory/memory_data_reg[268435528][7]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.090ns  (logic 0.045ns (4.129%)  route 1.045ns (95.871%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y0       PLLE2_ADV                    0.000     0.000 f  pll/inst/plle2_adv_inst/LOCKED
                         net (fo=2, routed)           0.394     0.394    data_memory/locked
    SLICE_X65Y47         LUT2 (Prop_lut2_I1_O)        0.045     0.439 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       0.651     1.090    data_memory/reset
    SLICE_X58Y47         FDRE                                         r  data_memory/memory_data_reg[268435528][7]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.865    -0.261    data_memory/clk_out1
    SLICE_X58Y47         FDRE                                         r  data_memory/memory_data_reg[268435528][7]/C

Slack:                    inf
  Source:                 pll/inst/plle2_adv_inst/LOCKED
                            (internal pin)
  Destination:            data_memory/memory_data_reg[268435528][9]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.090ns  (logic 0.045ns (4.129%)  route 1.045ns (95.871%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y0       PLLE2_ADV                    0.000     0.000 f  pll/inst/plle2_adv_inst/LOCKED
                         net (fo=2, routed)           0.394     0.394    data_memory/locked
    SLICE_X65Y47         LUT2 (Prop_lut2_I1_O)        0.045     0.439 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       0.651     1.090    data_memory/reset
    SLICE_X58Y47         FDRE                                         r  data_memory/memory_data_reg[268435528][9]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.865    -0.261    data_memory/clk_out1
    SLICE_X58Y47         FDRE                                         r  data_memory/memory_data_reg[268435528][9]/C

Slack:                    inf
  Source:                 pll/inst/plle2_adv_inst/LOCKED
                            (internal pin)
  Destination:            data_memory/memory_data_reg[268435475][4]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.119ns  (logic 0.045ns (4.022%)  route 1.074ns (95.978%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y0       PLLE2_ADV                    0.000     0.000 f  pll/inst/plle2_adv_inst/LOCKED
                         net (fo=2, routed)           0.394     0.394    data_memory/locked
    SLICE_X65Y47         LUT2 (Prop_lut2_I1_O)        0.045     0.439 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       0.680     1.119    data_memory/reset
    SLICE_X65Y45         FDRE                                         r  data_memory/memory_data_reg[268435475][4]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.866    -0.260    data_memory/clk_out1
    SLICE_X65Y45         FDRE                                         r  data_memory/memory_data_reg[268435475][4]/C

Slack:                    inf
  Source:                 pll/inst/plle2_adv_inst/LOCKED
                            (internal pin)
  Destination:            data_memory/memory_data_reg[268435529][10]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.119ns  (logic 0.045ns (4.022%)  route 1.074ns (95.978%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y0       PLLE2_ADV                    0.000     0.000 f  pll/inst/plle2_adv_inst/LOCKED
                         net (fo=2, routed)           0.394     0.394    data_memory/locked
    SLICE_X65Y47         LUT2 (Prop_lut2_I1_O)        0.045     0.439 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       0.680     1.119    data_memory/reset
    SLICE_X64Y45         FDRE                                         r  data_memory/memory_data_reg[268435529][10]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.866    -0.260    data_memory/clk_out1
    SLICE_X64Y45         FDRE                                         r  data_memory/memory_data_reg[268435529][10]/C

Slack:                    inf
  Source:                 pll/inst/plle2_adv_inst/LOCKED
                            (internal pin)
  Destination:            data_memory/memory_data_reg[268435529][7]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.119ns  (logic 0.045ns (4.022%)  route 1.074ns (95.978%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y0       PLLE2_ADV                    0.000     0.000 f  pll/inst/plle2_adv_inst/LOCKED
                         net (fo=2, routed)           0.394     0.394    data_memory/locked
    SLICE_X65Y47         LUT2 (Prop_lut2_I1_O)        0.045     0.439 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       0.680     1.119    data_memory/reset
    SLICE_X64Y45         FDRE                                         r  data_memory/memory_data_reg[268435529][7]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.866    -0.260    data_memory/clk_out1
    SLICE_X64Y45         FDRE                                         r  data_memory/memory_data_reg[268435529][7]/C

Slack:                    inf
  Source:                 pll/inst/plle2_adv_inst/LOCKED
                            (internal pin)
  Destination:            data_memory/memory_data_reg[268435520][10]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.167ns  (logic 0.045ns (3.857%)  route 1.122ns (96.143%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y0       PLLE2_ADV                    0.000     0.000 f  pll/inst/plle2_adv_inst/LOCKED
                         net (fo=2, routed)           0.394     0.394    data_memory/locked
    SLICE_X65Y47         LUT2 (Prop_lut2_I1_O)        0.045     0.439 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       0.728     1.167    data_memory/reset
    SLICE_X60Y46         FDRE                                         r  data_memory/memory_data_reg[268435520][10]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.864    -0.262    data_memory/clk_out1
    SLICE_X60Y46         FDRE                                         r  data_memory/memory_data_reg[268435520][10]/C

Slack:                    inf
  Source:                 pll/inst/plle2_adv_inst/LOCKED
                            (internal pin)
  Destination:            data_memory/memory_data_reg[268435520][4]/R
                            (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.167ns  (logic 0.045ns (3.857%)  route 1.122ns (96.143%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.260ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.203ns
    Phase Error              (PE):    0.156ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLLE2_ADV_X1Y0       PLLE2_ADV                    0.000     0.000 f  pll/inst/plle2_adv_inst/LOCKED
                         net (fo=2, routed)           0.394     0.394    data_memory/locked
    SLICE_X65Y47         LUT2 (Prop_lut2_I1_O)        0.045     0.439 r  data_memory/memory_data[268435967][31]_i_1/O
                         net (fo=17907, routed)       0.728     1.167    data_memory/reset
    SLICE_X60Y46         FDRE                                         r  data_memory/memory_data_reg[268435520][4]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_phase_locked_loop rise edge)
                                                      0.000     0.000 r  
    R4                                                0.000     0.000 r  hardware_clk (IN)
                         net (fo=0)                   0.000     0.000    pll/inst/clk_in1
    R4                   IBUF (Prop_ibuf_I_O)         0.457     0.457 r  pll/inst/clkin1_ibufg/O
                         net (fo=1, routed)           0.481     0.938    pll/inst/clk_in1_phase_locked_loop
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.700 r  pll/inst/plle2_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.546    -1.155    pll/inst/clk_out1_phase_locked_loop
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.126 r  pll/inst/clkout1_buf/O
                         net (fo=18132, routed)       0.864    -0.262    data_memory/clk_out1
    SLICE_X60Y46         FDRE                                         r  data_memory/memory_data_reg[268435520][4]/C





