#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Mon Jul 15 21:30:00 2024
# Process ID: 34208
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1
# Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi
# Journal file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1\vivado.jou
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
#-----------------------------------------------------------
source CPU.tcl -notrace
create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 462.992 ; gain = 184.602
Command: link_design -top CPU -part xc7a35tfgg484-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7a35tfgg484-1
INFO: [Project 1-454] Reading design checkpoint 'd:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp' for cell 'pll'
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.131 . Memory (MB): peak = 916.242 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 3508 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc] for cell 'pll/inst'
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc] for cell 'pll/inst'
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54]
INFO: [Timing 38-2] Deriving generated clocks [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54]
get_clocks: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1599.602 ; gain = 559.164
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst'
Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1599.602 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1599.602 ; gain = 1123.602
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.641 . Memory (MB): peak = 1599.602 ; gain = 0.000

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 2009eb4ca

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1613.895 ; gain = 14.293

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 2009eb4ca

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1979.137 ; gain = 0.000

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2009eb4ca

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 1 Initialization | Checksum: 2009eb4ca

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1979.137 ; gain = 0.000

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 2009eb4ca

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.360 . Memory (MB): peak = 1979.137 ; gain = 0.000

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 2009eb4ca

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.374 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 2 Timer Update And Timing Data Collection | Checksum: 2009eb4ca

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.375 . Memory (MB): peak = 1979.137 ; gain = 0.000

Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 13 inverters resulting in an inversion of 263 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 1362abf1f

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1979.137 ; gain = 0.000
Retarget | Checksum: 1362abf1f
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 14 cells
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 164c5dc3c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.595 . Memory (MB): peak = 1979.137 ; gain = 0.000
Constant propagation | Checksum: 164c5dc3c
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
Phase 5 Sweep | Checksum: 1aad7b8f8

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.753 . Memory (MB): peak = 1979.137 ; gain = 0.000
Sweep | Checksum: 1aad7b8f8
INFO: [Opt 31-389] Phase Sweep created 12 cells and removed 0 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 1aad7b8f8

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.867 . Memory (MB): peak = 1979.137 ; gain = 0.000
BUFG optimization | Checksum: 1aad7b8f8
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 1aad7b8f8

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.876 . Memory (MB): peak = 1979.137 ; gain = 0.000
Shift Register Optimization | Checksum: 1aad7b8f8
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1e3f1f4ce

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.908 . Memory (MB): peak = 1979.137 ; gain = 0.000
Post Processing Netlist | Checksum: 1e3f1f4ce
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2361cfa52

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 9.2 Verifying Netlist Connectivity | Checksum: 2361cfa52

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 9 Finalization | Checksum: 2361cfa52

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |              14  |                                              1  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |              12  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 2361cfa52

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1979.137 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 2361cfa52

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1979.137 ; gain = 0.000

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 2361cfa52

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1979.137 ; gain = 0.000

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1979.137 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 2361cfa52

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1979.137 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
INFO: [runtcl-4] Executing : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx
Command: report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt.
report_drc completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1979.137 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1979.137 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1979.137 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1979.137 ; gain = 0.000
Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1979.137 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1979.137 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1979.137 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_opt.dcp' has been generated.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14ae9822c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1979.137 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1979.137 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b434b971

Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: c5c27cdb

Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: c5c27cdb

Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 1 Placer Initialization | Checksum: c5c27cdb

Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 146e69098

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 151ff6269

Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 151ff6269

Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 2.4 Global Placement Core

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: a33c0039

Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 55 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 25 nets or LUTs. Breaked 0 LUT, combined 25 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2034.871 ; gain = 0.000

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |             25  |                    25  |           0  |           1  |  00:00:00  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            0  |             25  |                    25  |           0  |           4  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: f4053bc8

Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 2.4 Global Placement Core | Checksum: 1099bb7b7

Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 2 Global Placement | Checksum: 1099bb7b7

Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 10f07ac64

Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1626a5454

Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 14fc2b59e

Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 169ab9d86

Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1aa221702

Time (s): cpu = 00:00:08 ; elapsed = 00:00:24 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1a5685b79

Time (s): cpu = 00:00:08 ; elapsed = 00:00:24 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 2169317c7

Time (s): cpu = 00:00:08 ; elapsed = 00:00:24 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 3 Detail Placement | Checksum: 2169317c7

Time (s): cpu = 00:00:08 ; elapsed = 00:00:24 . Memory (MB): peak = 2034.871 ; gain = 55.734

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 2b42d29d8

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.979 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 2a752e597

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.687 . Memory (MB): peak = 2077.816 ; gain = 9.480
INFO: [Place 46-33] Processed net data_memory/reset, BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 2a752e597

Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2079.719 ; gain = 11.383
Phase 4.1.1.1 BUFG Insertion | Checksum: 2b42d29d8

Time (s): cpu = 00:00:10 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.719 ; gain = 100.582

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=2.979. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 249162dd2

Time (s): cpu = 00:00:10 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.719 ; gain = 100.582

Time (s): cpu = 00:00:10 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.719 ; gain = 100.582
Phase 4.1 Post Commit Optimization | Checksum: 249162dd2

Time (s): cpu = 00:00:10 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.719 ; gain = 100.582

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 249162dd2

Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                2x2|                1x1|
|___________|___________________|___________________|
|      South|                1x1|                2x2|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 249162dd2

Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582
Phase 4.3 Placer Reporting | Checksum: 249162dd2

Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2079.719 ; gain = 0.000

Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17f441675

Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582
Ending Placer Task | Checksum: f24d5614

Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582
66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 2079.719 ; gain = 100.582
INFO: [runtcl-4] Executing : report_io -file CPU_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 2079.719 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 2079.719 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2095.105 ; gain = 1.957
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2095.105 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2095.105 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2095.105 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2095.105 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2095.105 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2095.105 ; gain = 1.957
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_placed.dcp' has been generated.
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'

Starting Initial Update Timing Task

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2141.781 ; gain = 46.676
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
75 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 2167.066 ; gain = 6.965
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2167.965 ; gain = 1.836
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2167.965 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2167.965 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2167.965 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2167.965 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2167.965 ; gain = 7.863
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: ddacfa99 ConstDB: 0 ShapeSum: 14a05b7b RouteDB: 0
Post Restoration Checksum: NetGraph: 7bb36a25 | NumContArr: 2f28cab3 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2302e2a12

Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 2284.527 ; gain = 85.477

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2302e2a12

Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 2284.527 ; gain = 85.477

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2302e2a12

Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 2284.527 ; gain = 85.477
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2fed2e595

Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 2302.227 ; gain = 103.176
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.232  | TNS=0.000  | WHS=-0.150 | THS=-18.367|


Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 22010
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 22010
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 2 Router Initialization | Checksum: 32765f03a

Time (s): cpu = 00:00:11 ; elapsed = 00:00:20 . Memory (MB): peak = 2345.152 ; gain = 146.102

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 32765f03a

Time (s): cpu = 00:00:11 ; elapsed = 00:00:20 . Memory (MB): peak = 2345.152 ; gain = 146.102

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 2af1be2f2

Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 2349.547 ; gain = 150.496
Phase 3 Initial Routing | Checksum: 2af1be2f2

Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 2349.547 ; gain = 150.496

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 3351
 Number of Nodes with overlaps = 253
 Number of Nodes with overlaps = 33
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.748  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 1c65aeb4f

Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.629 ; gain = 156.578
Phase 4 Rip-up And Reroute | Checksum: 1c65aeb4f

Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.629 ; gain = 156.578

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 19ccb358b

Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.629 ; gain = 156.578
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.748  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 5.1 Delay CleanUp | Checksum: 19ccb358b

Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.633 ; gain = 156.582

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 19ccb358b

Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.633 ; gain = 156.582
Phase 5 Delay and Skew Optimization | Checksum: 19ccb358b

Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.633 ; gain = 156.582

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1aefd8a0c

Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2355.633 ; gain = 156.582
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.748  | TNS=0.000  | WHS=0.055  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 1aff898c0

Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2355.633 ; gain = 156.582
Phase 6 Post Hold Fix | Checksum: 1aff898c0

Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2355.633 ; gain = 156.582

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 15.1128 %
  Global Horizontal Routing Utilization  = 15.1869 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 1aff898c0

Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2355.633 ; gain = 156.582

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1aff898c0

Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2357.648 ; gain = 158.598

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 17c6dc57b

Time (s): cpu = 00:00:15 ; elapsed = 00:00:34 . Memory (MB): peak = 2357.648 ; gain = 158.598

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=3.748  | TNS=0.000  | WHS=0.055  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 17c6dc57b

Time (s): cpu = 00:00:15 ; elapsed = 00:00:35 . Memory (MB): peak = 2357.648 ; gain = 158.598
INFO: [Route 35-16] Router Completed Successfully

Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: ff332dbf

Time (s): cpu = 00:00:15 ; elapsed = 00:00:35 . Memory (MB): peak = 2357.648 ; gain = 158.598
Ending Routing Task | Checksum: ff332dbf

Time (s): cpu = 00:00:15 ; elapsed = 00:00:36 . Memory (MB): peak = 2357.648 ; gain = 158.598

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
90 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:37 . Memory (MB): peak = 2357.648 ; gain = 189.684
INFO: [runtcl-4] Executing : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
Command: report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx
Command: report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2430.602 ; gain = 72.953
INFO: [runtcl-4] Executing : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
Command: report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
100 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file CPU_route_status.rpt -pb CPU_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file CPU_timing_summary_routed.rpt -pb CPU_timing_summary_routed.pb -rpx CPU_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file CPU_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file CPU_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU_bus_skew_routed.rpt -pb CPU_bus_skew_routed.pb -rpx CPU_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2499.625 ; gain = 4.914
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2499.625 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2499.625 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.218 . Memory (MB): peak = 2499.625 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2499.625 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2499.625 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2499.625 ; gain = 4.914
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_routed.dcp' has been generated.
Command: write_bitstream -force CPU.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [DRC DPIP-1] Input pipelining: DSP execution/alu/result0 input execution/alu/result0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP execution/alu/result0 input execution/alu/result0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP execution/alu/result0__0 input execution/alu/result0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP execution/alu/result0__0 input execution/alu/result0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP execution/alu/result0__1 input execution/alu/result0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPIP-1] Input pipelining: DSP execution/alu/result0__1 input execution/alu/result0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP execution/alu/result0 output execution/alu/result0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP execution/alu/result0__0 output execution/alu/result0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP execution/alu/result0__1 output execution/alu/result0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP execution/alu/result0 multiplier stage execution/alu/result0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP execution/alu/result0__0 multiplier stage execution/alu/result0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP execution/alu/result0__1 multiplier stage execution/alu/result0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 13 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./CPU.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
14 Infos, 13 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 2965.840 ; gain = 466.215
INFO: [Common 17-206] Exiting Vivado at Mon Jul 15 21:32:10 2024...
