`timescale 1ns / 1ps
module test_cpu ();
    reg sim_clk = 0;
    reg reset = 0;
    wire [11:0] bcd_control;
    wire clk_locked;

    initial begin
        forever begin
            #5 sim_clk <= ~sim_clk;
        end
    end

    CPU cpu(
        .hardware_clk(sim_clk),
        .hardware_reset(reset),
        .clock_locked(clk_locked),
        .bcd_control(bcd_control)
    );

    initial begin
        reset = 1;
        #30;
        reset = 0;
    end
endmodule
