`timescale 1ns / 1ps

module RegisterFile (
    input clk,
    input reset,
    input [4:0] read_addr1,
    input [4:0] read_addr2,
    input write_enable,
    input [4:0] write_addr,
    input [31:0] write_data,
    input write_ra,
    input [4:0] write_ra_addr,
    input [31:0] write_ra_data,
    output [31:0] read_output1,
    output [31:0] read_output2
);

    reg [31:0] registers[1:31];
    integer i;

    assign read_output1 = (read_addr1 == 5'b00000) ? 32'h00000000 :
        (read_addr1 == write_ra_addr && write_ra == 1'b1) ? write_ra_data :
        (read_addr1 == write_addr && write_enable == 1'b1) ? write_data : registers[read_addr1];

    assign read_output2 = (read_addr2 == 5'b00000) ? 32'h00000000 :
        (read_addr2 == write_ra_addr && write_ra == 1'b1) ? write_ra_data :
        (read_addr2 == write_addr && write_enable == 1'b1) ? write_data : registers[read_addr2];

    initial begin
        for (i = 1; i < 32; i = i + 1) begin
            registers[i] <= 32'h00000000;
        end
    end

    always @(posedge clk) begin
        if (reset) begin
            for (i = 1; i < 32; i = i + 1) begin
                registers[i] <= 32'h00000000;
            end
        end else begin
            if (write_addr == write_ra_addr) begin
                if (write_ra) begin
                    registers[write_ra_addr] <= write_ra_data;
                end else begin
                    if (write_enable) begin
                        registers[write_addr] <= write_data;
                    end
                end
            end else begin
                if (write_ra) begin
                    registers[write_ra_addr] <= write_ra_data;
                end
                if (write_enable) begin
                    registers[write_addr] <= write_data;
                end
            end
        end
    end

endmodule
