`timescale 1ns / 1ps

module InstructionMemory (
    input [31:0] address,
    output reg [31:0] instruction
);

    always @(*) begin
        case (address[31:2])
            20'd0:   instruction <= 32'h3c010000;
            20'd1:   instruction <= 32'h3421fadd;
            20'd2:   instruction <= 32'h00018020;
            20'd3:   instruction <= 32'h08000003;
            default: instruction <= 32'h00000000;
        endcase
    end

endmodule
