`timescale 1ns / 1ps
module ExecutionForward (
    input [4:0] EX_rs_address,
    input [4:0] EX_rt_address,
    input MEM_register_write,
    input [4:0] MEM_register_write_address,
    input WB_register_write,
    input [4:0] WB_register_write_address,
    output reg [1:0] IDA_source,
    output reg [1:0] IDB_source
);

    always @(*) begin
        if (MEM_register_write == 1'b1 && MEM_register_write_address == EX_rs_address &&
        EX_rs_address != 5'b00000) begin
            IDA_source <= 2'b01;
        end else begin
            if (WB_register_write == 1'b1 && WB_register_write_address == EX_rs_address &&
            EX_rs_address != 5'b00000) begin
                IDA_source <= 2'b10;
            end else begin
                IDA_source <= 2'b00;
            end
        end

        if (MEM_register_write == 1'b1 && MEM_register_write_address == EX_rt_address &&
        EX_rt_address != 5'b00000) begin
            IDB_source <= 2'b01;
        end else begin
            if (WB_register_write == 1'b1 && WB_register_write_address == EX_rt_address &&
            EX_rt_address != 5'b00000) begin
                IDB_source <= 2'b10;
            end else begin
                IDB_source <= 2'b00;
            end
        end
    end
endmodule
