`timescale 1ns / 1ps

module DataMemory (
    input clk,
    input reset,
    input [31:0] address,
    input write_enable,
    input [31:0] write_data,
    output [31:0] read_data,
    output [31:0] bcd_hardwire
);
    parameter integer MEM_SIZE_IN_WORD = 64;
    parameter integer START_ADDRESS = 32'h00000000;

    localparam integer StartAddressInWord = START_ADDRESS / 4;

    reg [31:0] memory_data[MEM_SIZE_IN_WORD + StartAddressInWord - 1 : StartAddressInWord];

    assign bcd_hardwire = memory_data[StartAddressInWord+4];

    assign read_data = memory_data[address[31:2]];

    integer i;

    initial begin
        for (i = StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1) begin
            memory_data[i] <= 32'h00000000;
        end
    end

    always @(posedge clk) begin
        if (reset) begin
            for (i = StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1) begin
                memory_data[i] <= 32'h00000000;
            end
        end else begin
            if (write_enable) begin
                memory_data[address[31:2]] <= write_data;
            end
        end
    end
endmodule
