#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Mon Jul 15 21:28:25 2024
# Process ID: 34260
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1
# Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds
# Journal file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1\vivado.jou
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
#-----------------------------------------------------------
source CPU.tcl -notrace
create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 463.656 ; gain = 184.578
Command: read_checkpoint -auto_incremental -incremental D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
Command: synth_design -top CPU -part xc7a35tfgg484-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Device 21-403] Loading part xc7a35tfgg484-1
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 34600
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Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 1309.031 ; gain = 440.004
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INFO: [Synth 8-6157] synthesizing module 'CPU' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/CPU.v:2]
INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-34260-Viviana/realtime/phase_locked_loop_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-34260-Viviana/realtime/phase_locked_loop_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'InstFetch' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstFetch.v:2]
INFO: [Synth 8-6157] synthesizing module 'InstructionMemory' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'InstructionMemory' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'InstFetch' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstFetch.v:2]
INFO: [Synth 8-6157] synthesizing module 'InstDecode' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstDecode.v:2]
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'RegisterFile' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/RegisterFile.v:3]
INFO: [Synth 8-6155] done synthesizing module 'RegisterFile' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/RegisterFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'ImmediateExtender' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ImmediateExtender.v:3]
INFO: [Synth 8-6155] done synthesizing module 'ImmediateExtender' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ImmediateExtender.v:3]
INFO: [Synth 8-6155] done synthesizing module 'InstDecode' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstDecode.v:2]
INFO: [Synth 8-6157] synthesizing module 'Execution' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/Execution.v:2]
INFO: [Synth 8-6157] synthesizing module 'ALU' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6155] done synthesizing module 'ALU' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6155] done synthesizing module 'Execution' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/Execution.v:2]
INFO: [Synth 8-6157] synthesizing module 'MemoryAccess' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/MemoryAccess.v:2]
INFO: [Synth 8-6155] done synthesizing module 'MemoryAccess' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/MemoryAccess.v:2]
INFO: [Synth 8-6157] synthesizing module 'WriteBack' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/WriteBack.v:2]
INFO: [Synth 8-6155] done synthesizing module 'WriteBack' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/WriteBack.v:2]
INFO: [Synth 8-6157] synthesizing module 'DataMemory' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/DataMemory.v:3]
	Parameter MEM_SIZE_IN_WORD bound to: 512 - type: integer 
	Parameter START_ADDRESS bound to: 1073741824 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'DataMemory' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/DataMemory.v:3]
INFO: [Synth 8-6157] synthesizing module 'ExecutionForward' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ExecutionForward.v:2]
INFO: [Synth 8-6155] done synthesizing module 'ExecutionForward' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ExecutionForward.v:2]
INFO: [Synth 8-6157] synthesizing module 'HazardUnit' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/HazardUnit.v:2]
INFO: [Synth 8-6155] done synthesizing module 'HazardUnit' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/HazardUnit.v:2]
INFO: [Synth 8-6155] done synthesizing module 'CPU' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/CPU.v:2]
WARNING: [Synth 8-7129] Port address[1] in module DataMemory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module DataMemory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module InstructionMemory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module InstructionMemory is either unconnected or has no load
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Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.824 ; gain = 609.797
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.824 ; gain = 609.797
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.824 ; gain = 609.797
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.169 . Memory (MB): peak = 1478.824 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc] for cell 'pll'
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc] for cell 'pll'
Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/CPU_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/CPU_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1583.539 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.061 . Memory (MB): peak = 1583.539 ; gain = 0.000
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
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Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1583.539 ; gain = 714.512
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Start Loading Part and Timing Information
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Loading part: xc7a35tfgg484-1
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1583.539 ; gain = 714.512
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Start Applying 'set_property' XDC Constraints
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Applied set_property IO_BUFFER_TYPE = NONE for hardware_clk. (constraint file  d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc, line 3).
Applied set_property CLOCK_BUFFER_TYPE = NONE for hardware_clk. (constraint file  d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc, line 4).
Applied set_property KEEP_HIERARCHY = SOFT for pll. (constraint file  auto generated constraint).
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1583.539 ; gain = 714.512
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:18 . Memory (MB): peak = 1583.539 ; gain = 714.512
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Start RTL Component Statistics 
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Detailed RTL Component Info : 
+---Adders : 
	   2 Input   32 Bit       Adders := 2     
	   3 Input   32 Bit       Adders := 1     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
	   2 Input      1 Bit         XORs := 1     
+---Registers : 
	               32 Bit    Registers := 554   
	                5 Bit    Registers := 7     
	                1 Bit    Registers := 12    
+---Multipliers : 
	              32x32  Multipliers := 1     
+---Muxes : 
	   2 Input   32 Bit        Muxes := 81    
	   4 Input   32 Bit        Muxes := 3     
	   2 Input    5 Bit        Muxes := 3     
	   6 Input    5 Bit        Muxes := 1     
	   4 Input    5 Bit        Muxes := 1     
	   3 Input    2 Bit        Muxes := 3     
	   2 Input    2 Bit        Muxes := 1     
	   2 Input    1 Bit        Muxes := 703   
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Finished RTL Component Statistics 
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Start Part Resource Summary
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Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
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Finished Part Resource Summary
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Start Cross Boundary and Area Optimization
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WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
DSP Report: Generating DSP alu/result0, operation Mode is: A*B.
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
DSP Report: Generating DSP alu/result0, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
DSP Report: Generating DSP alu/result0, operation Mode is: A*B.
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
DSP Report: Generating DSP alu/result0, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:40 . Memory (MB): peak = 1583.539 ; gain = 714.512
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 Sort Area is CPU__GC0 alu/result0_0 : 0 0 : 3101 5879 : Used 1 time 0
 Sort Area is CPU__GC0 alu/result0_0 : 0 1 : 2778 5879 : Used 1 time 0
 Sort Area is CPU__GC0 alu/result0_3 : 0 0 : 2759 5418 : Used 1 time 0
 Sort Area is CPU__GC0 alu/result0_3 : 0 1 : 2659 5418 : Used 1 time 0
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Start ROM, RAM, DSP, Shift Register and Retiming Reporting
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ROM: Preliminary Mapping Report
+------------------+-------------+---------------+----------------+
|Module Name       | RTL Object  | Depth x Width | Implemented As | 
+------------------+-------------+---------------+----------------+
|InstructionMemory | instruction | 256x32        | LUT            | 
+------------------+-------------+---------------+----------------+


DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping    | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Execution   | A*B            | 18     | 16     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|Execution   | (PCIN>>17)+A*B | 16     | 16     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|Execution   | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|Execution   | (PCIN>>17)+A*B | 18     | 16     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
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Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
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Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:46 . Memory (MB): peak = 1583.539 ; gain = 714.512
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:01:00 . Memory (MB): peak = 1713.750 ; gain = 844.723
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Start Technology Mapping
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Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:01:06 . Memory (MB): peak = 1720.066 ; gain = 851.039
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
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Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:01:11 . Memory (MB): peak = 1720.066 ; gain = 851.039
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Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:01:11 . Memory (MB): peak = 1720.066 ; gain = 851.039
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Start Rebuilding User Hierarchy
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:01:12 . Memory (MB): peak = 1720.066 ; gain = 851.039
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Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:01:12 . Memory (MB): peak = 1720.066 ; gain = 851.039
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:01:13 . Memory (MB): peak = 1720.066 ; gain = 851.039
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Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:01:13 . Memory (MB): peak = 1720.066 ; gain = 851.039
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Start Writing Synthesis Report
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DSP Final Report (the ' indicates corresponding REG is set)
+------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping  | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
+------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Execution   | A*B          | 17     | 15     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|Execution   | A*B          | 17     | 17     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|Execution   | PCIN>>17+A*B | 17     | 15     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
+------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+


Report BlackBoxes: 
+------+------------------+----------+
|      |BlackBox name     |Instances |
+------+------------------+----------+
|1     |phase_locked_loop |         1|
+------+------------------+----------+

Report Cell Usage: 
+------+------------------+------+
|      |Cell              |Count |
+------+------------------+------+
|1     |phase_locked_loop |     1|
|2     |CARRY4            |    39|
|3     |DSP48E1           |     3|
|4     |LUT1              |    15|
|5     |LUT2              |   154|
|6     |LUT3              |   230|
|7     |LUT4              |   281|
|8     |LUT5              |   825|
|9     |LUT6              |  7154|
|10    |MUXF7             |  2377|
|11    |MUXF8             |  1088|
|12    |FDRE              | 17968|
|13    |FDSE              |   152|
|14    |IBUF              |     1|
|15    |OBUF              |    13|
+------+------------------+------+
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:01:13 . Memory (MB): peak = 1720.066 ; gain = 851.039
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Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:01:10 . Memory (MB): peak = 1720.066 ; gain = 746.324
Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:01:13 . Memory (MB): peak = 1720.066 ; gain = 851.039
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.237 . Memory (MB): peak = 1720.066 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 3507 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1720.688 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Synth Design complete | Checksum: 5b34e2bc
INFO: [Common 17-83] Releasing license: Synthesis
51 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:01:19 . Memory (MB): peak = 1720.688 ; gain = 1244.133
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1720.688 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Mon Jul 15 21:29:53 2024...
