Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date         : Mon Jul 15 21:31:49 2024
| Host         : Viviana running 64-bit major release  (build 9200)
| Command      : report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx
| Design       : CPU
| Device       : xc7a35tfgg484-1
| Speed File   : -1
| Design State : Fully Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 3
+----------+----------+-----------------+------------+
| Rule     | Severity | Description     | Violations |
+----------+----------+-----------------+------------+
| SYNTH-10 | Warning  | Wide multiplier | 3          |
+----------+----------+-----------------+------------+

2. REPORT DETAILS
-----------------
SYNTH-10#1 Warning
Wide multiplier  
Detected multiplier at execution/alu/result0 of size 16x18, it is decomposed from a wide multipler into 4 DSP blocks.
Related violations: <none>

SYNTH-10#2 Warning
Wide multiplier  
Detected multiplier at execution/alu/result0__0 of size 18x18, it is decomposed from a wide multipler into 4 DSP blocks.
Related violations: <none>

SYNTH-10#3 Warning
Wide multiplier  
Detected multiplier at execution/alu/result0__1 of size 18x16, it is decomposed from a wide multipler into 4 DSP blocks.
Related violations: <none>


