# compile verilog/system verilog design source files
verilog xil_defaultlib  --include "../../../../PipelineProcessor.ip_user_files/ipstatic" \
"../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v" \
"../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/ALU.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/ControlUnit.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/DataMemory.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/Execution.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/ExecutionForward.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/HazardUnit.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/ImmediateExtender.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/InstDecode.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/InstFetch.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/InstructionMemory.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/MemoryAccess.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/RegisterFile.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/WriteBack.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/CPU.v" \
"../../../../PipelineProcessor.srcs/sim_1/new/test_cpu.v" \

# compile glbl module
verilog xil_defaultlib "glbl.v"

# Do not sort compile order
nosort
