diff --git a/PipelineProcessor.runs/impl_1/CPU.vdi b/PipelineProcessor.runs/impl_1/CPU.vdi index 5d8324e..edc8397 100644 --- a/PipelineProcessor.runs/impl_1/CPU.vdi +++ b/PipelineProcessor.runs/impl_1/CPU.vdi @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Fri Jul 12 00:09:58 2024 -# Process ID: 29956 +# Start of session at: Fri Jul 12 21:05:00 2024 +# Process ID: 22952 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1 # Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi @@ -12,13 +12,14 @@ # Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB #----------------------------------------------------------- source CPU.tcl -notrace +create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 464.035 ; gain = 185.215 Command: link_design -top CPU -part xc7a35tfgg484-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7a35tfgg484-1 INFO: [Project 1-454] Reading design checkpoint 'd:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp' for cell 'pll' -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.109 . Memory (MB): peak = 915.172 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 3483 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.112 . Memory (MB): peak = 915.762 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 3557 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.2 INFO: [Project 1-570] Preparing netlist for logic optimization @@ -27,17 +28,18 @@ Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/Pipelin Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54] INFO: [Timing 38-2] Deriving generated clocks [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54] +get_clocks: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1598.367 ; gain = 557.914 Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst' Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc] Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1598.852 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1598.367 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:10 . Memory (MB): peak = 1598.852 ; gain = 1123.434 +link_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 1598.367 ; gain = 1120.484 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' @@ -48,112 +50,111 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.571 . Memory (MB): peak = 1598.852 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.645 . Memory (MB): peak = 1598.367 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 19815f8ec +Ending Cache Timing Information Task | Checksum: 16cb45a4f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1613.586 ; gain = 14.734 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.434 . Memory (MB): peak = 1612.133 ; gain = 13.766 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup -Phase 1.1 Core Generation And Design Setup | Checksum: 19815f8ec +Phase 1.1 Core Generation And Design Setup | Checksum: 16cb45a4f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1980.477 ; gain = 0.000 Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 19815f8ec +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 16cb45a4f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Phase 1 Initialization | Checksum: 19815f8ec +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Phase 1 Initialization | Checksum: 16cb45a4f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1980.477 ; gain = 0.000 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 19815f8ec +Phase 2.1 Timer Update | Checksum: 16cb45a4f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.348 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.355 . Memory (MB): peak = 1980.477 ; gain = 0.000 Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 19815f8ec +Phase 2.2 Timing Data Collection | Checksum: 16cb45a4f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.363 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Phase 2 Timer Update And Timing Data Collection | Checksum: 19815f8ec +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.379 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Phase 2 Timer Update And Timing Data Collection | Checksum: 16cb45a4f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.364 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.380 . Memory (MB): peak = 1980.477 ; gain = 0.000 Phase 3 Retarget -INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 96 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: 1563adde0 +Phase 3 Retarget | Checksum: 192618621 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.477 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Retarget | Checksum: 1563adde0 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 4 cells +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.517 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Retarget | Checksum: 192618621 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: 2080e885b +Phase 4 Constant propagation | Checksum: 20b011990 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.545 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Constant propagation | Checksum: 2080e885b +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.606 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Constant propagation | Checksum: 20b011990 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep -Phase 5 Sweep | Checksum: 1bd034584 +Phase 5 Sweep | Checksum: 1bc044ae4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.654 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Sweep | Checksum: 1bd034584 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Sweep | Checksum: 1bc044ae4 INFO: [Opt 31-389] Phase Sweep created 12 cells and removed 0 cells Phase 6 BUFG optimization -Phase 6 BUFG optimization | Checksum: 1bd034584 +Phase 6 BUFG optimization | Checksum: 1bc044ae4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1973.746 ; gain = 0.000 -BUFG optimization | Checksum: 1bd034584 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.864 . Memory (MB): peak = 1980.477 ; gain = 0.000 +BUFG optimization | Checksum: 1bc044ae4 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: 1bd034584 +Phase 7 Shift Register Optimization | Checksum: 1bc044ae4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.756 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Shift Register Optimization | Checksum: 1bd034584 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.875 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Shift Register Optimization | Checksum: 1bc044ae4 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: 1408d463e +Phase 8 Post Processing Netlist | Checksum: 24e91c234 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.781 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Post Processing Netlist | Checksum: 1408d463e +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.902 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Post Processing Netlist | Checksum: 24e91c234 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1e5497da9 +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 14de2f7bb -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.927 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Phase 9.2 Verifying Netlist Connectivity | Checksum: 1e5497da9 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Phase 9.2 Verifying Netlist Connectivity | Checksum: 14de2f7bb -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.944 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Phase 9 Finalization | Checksum: 1e5497da9 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Phase 9 Finalization | Checksum: 14de2f7bb -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.945 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000 Opt_design Change Summary ========================= @@ -161,7 +162,7 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 4 | 1 | +| Retarget | 0 | 1 | 1 | | Constant propagation | 0 | 0 | 0 | | Sweep | 12 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | @@ -170,30 +171,30 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- -Ending Logic Optimization Task | Checksum: 1e5497da9 +Ending Logic Optimization Task | Checksum: 14de2f7bb -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.947 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1980.477 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 1e5497da9 +Ending Power Optimization Task | Checksum: 14de2f7bb -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1980.477 ; gain = 0.000 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1e5497da9 +Ending Final Cleanup Task | Checksum: 14de2f7bb -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1980.477 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1e5497da9 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 14de2f7bb -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1980.477 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation -30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully INFO: [runtcl-4] Executing : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx Command: report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx @@ -202,16 +203,16 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt. report_drc completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1980.477 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1973.746 ; gain = 0.000 Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1980.477 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_opt.dcp' has been generated. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -231,59 +232,59 @@ Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12a703c9e +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11b2d87cf -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1973.746 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1980.477 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 9fe0ea66 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e3d58ae7 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.883 . Memory (MB): peak = 1973.746 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: fc45f473 +Phase 1.3 Build Placer Netlist Model | Checksum: 1db20e775 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: fc45f473 +Phase 1.4 Constrain Clocks/Macros | Checksum: 1db20e775 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2031.629 ; gain = 57.883 -Phase 1 Placer Initialization | Checksum: fc45f473 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Phase 1 Placer Initialization | Checksum: 1db20e775 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 2 Global Placement Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 1187634b5 +Phase 2.1 Floorplanning | Checksum: 156b1aef4 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: b5540111 +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1d86be86e -Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 2.3 Post-Processing in Floorplanning -Phase 2.3 Post-Processing in Floorplanning | Checksum: b5540111 +Phase 2.3 Post-Processing in Floorplanning | Checksum: 1d86be86e -Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis -Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 110aaba25 +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1400d07dd -Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:10 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 2.4.2 Physical Synthesis In Placer -INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 101 LUT instances to create LUTNM shape +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 78 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 -INFO: [Physopt 32-1138] End 1 Pass. Optimized 40 nets or LUTs. Breaked 0 LUT, combined 40 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-1138] End 1 Pass. Optimized 37 nets or LUTs. Breaked 0 LUT, combined 37 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell @@ -294,7 +295,7 @@ INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2031.629 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2032.707 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ @@ -303,7 +304,7 @@ Summary of Physical Synthesis Optimizations ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- -| LUT Combining | 0 | 40 | 40 | 0 | 1 | 00:00:00 | +| LUT Combining | 0 | 37 | 37 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | @@ -312,59 +313,59 @@ Summary of Physical Synthesis Optimizations | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 40 | 40 | 0 | 4 | 00:00:00 | +| Total | 0 | 37 | 37 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- -Phase 2.4.2 Physical Synthesis In Placer | Checksum: 16851cd1d +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1f5974df5 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2031.629 ; gain = 57.883 -Phase 2.4 Global Placement Core | Checksum: 168fd7ea9 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Phase 2.4 Global Placement Core | Checksum: 15c812e1b -Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2031.629 ; gain = 57.883 -Phase 2 Global Placement | Checksum: 168fd7ea9 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Phase 2 Global Placement | Checksum: 15c812e1b -Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 12da8b661 +Phase 3.1 Commit Multi Column Macros | Checksum: 1da65e99f -Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:13 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25e8832a5 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d55c087b -Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:14 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 221700b80 +Phase 3.3 Area Swap Optimization | Checksum: 1214d70ca -Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:14 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 171118896 +Phase 3.4 Pipeline Register Optimization | Checksum: 174ca9207 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:14 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 25d9dec9c +Phase 3.5 Small Shape Detail Placement | Checksum: 1eb9f62f7 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:24 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:28 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 16e056078 +Phase 3.6 Re-assign LUT pins | Checksum: 1badb8766 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:24 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: e663db1e +Phase 3.7 Pipeline Register Optimization | Checksum: 1ad982255 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:24 . Memory (MB): peak = 2031.629 ; gain = 57.883 -Phase 3 Detail Placement | Checksum: e663db1e +Time (s): cpu = 00:00:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Phase 3 Detail Placement | Checksum: 1ad982255 -Time (s): cpu = 00:00:10 ; elapsed = 00:00:24 . Memory (MB): peak = 2031.629 ; gain = 57.883 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2032.707 ; gain = 52.230 Phase 4 Post Placement Optimization and Clean-Up @@ -372,7 +373,7 @@ Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 51088c1c +Post Placement Optimization Initialization | Checksum: 25abda1d4 Phase 4.1.1.1 BUFG Insertion @@ -380,34 +381,34 @@ Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=3.262 | TNS=0.000 | -Phase 1 Physical Synthesis Initialization | Checksum: d85dca42 +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.540 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 1a16c95e6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.632 . Memory (MB): peak = 2077.414 ; gain = 14.797 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.702 . Memory (MB): peak = 2079.688 ; gain = 10.484 INFO: [Place 46-33] Processed net data_memory/reset, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. -Ending Physical Synthesis Task | Checksum: d85dca42 +Ending Physical Synthesis Task | Checksum: 1a16c95e6 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2079.488 ; gain = 16.871 -Phase 4.1.1.1 BUFG Insertion | Checksum: 51088c1c +Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2081.648 ; gain = 12.445 +Phase 4.1.1.1 BUFG Insertion | Checksum: 25abda1d4 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 2079.488 ; gain = 105.742 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 Phase 4.1.1.2 Post Placement Timing Optimization -INFO: [Place 30-746] Post Placement Timing Summary WNS=3.262. For the most accurate timing information please run report_timing. -Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: ebcb0a71 +INFO: [Place 30-746] Post Placement Timing Summary WNS=1.540. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 189e73d35 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 2079.488 ; gain = 105.742 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 2079.488 ; gain = 105.742 -Phase 4.1 Post Commit Optimization | Checksum: ebcb0a71 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 +Phase 4.1 Post Commit Optimization | Checksum: 189e73d35 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 2079.488 ; gain = 105.742 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: ebcb0a71 +Phase 4.2 Post Placement Cleanup | Checksum: 189e73d35 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 Phase 4.3 Placer Reporting @@ -417,7 +418,7 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| -| North| 2x2| 4x4| +| North| 2x2| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| @@ -426,42 +427,42 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion | West| 1x1| 1x1| |___________|___________________|___________________| -Phase 4.3.1 Print Estimated Congestion | Checksum: ebcb0a71 +Phase 4.3.1 Print Estimated Congestion | Checksum: 189e73d35 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742 -Phase 4.3 Placer Reporting | Checksum: ebcb0a71 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 +Phase 4.3 Placer Reporting | Checksum: 189e73d35 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2079.488 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2081.648 ; gain = 0.000 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: dc7f2636 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: d7614f21 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742 -Ending Placer Task | Checksum: 0e38a4fc +Time (s): cpu = 00:00:08 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 +Ending Placer Task | Checksum: bc3137e6 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742 -66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +Time (s): cpu = 00:00:08 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 +65 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742 +place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:35 . Memory (MB): peak = 2081.648 ; gain = 101.172 INFO: [runtcl-4] Executing : report_io -file CPU_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 2079.488 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 2081.648 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 2079.488 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 2081.648 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2093.965 ; gain = 0.941 -Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2093.965 ; gain = 0.941 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2093.965 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 2096.543 ; gain = 1.004 +Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.543 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2096.543 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2093.965 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 2093.965 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2093.965 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2093.965 ; gain = 0.941 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2096.543 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 2096.543 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2096.543 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.543 ; gain = 1.004 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_placed.dcp' has been generated. Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -469,23 +470,23 @@ INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc Starting Initial Update Timing Task -Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2141.992 ; gain = 48.027 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2143.457 ; gain = 46.914 INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation -75 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2167.289 ; gain = 7.023 -Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2168.047 ; gain = 0.758 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2168.047 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2168.809 ; gain = 7.066 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2169.680 ; gain = 0.871 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2169.680 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2168.047 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 2168.047 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2168.047 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2168.047 ; gain = 7.781 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 2169.680 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 2169.680 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2169.680 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2169.680 ; gain = 7.938 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -500,30 +501,30 @@ Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design -Checksum: PlaceDB: 4912218 ConstDB: 0 ShapeSum: 9a782e4 RouteDB: 0 -Post Restoration Checksum: NetGraph: 84c40091 | NumContArr: e6c0ef1d | Constraints: c2a8fa9d | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 2f0d6e4e8 +Checksum: PlaceDB: 835e865f ConstDB: 0 ShapeSum: 38d2b187 RouteDB: 0 +Post Restoration Checksum: NetGraph: 3533f183 | NumContArr: bffdc8ea | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 27a83afa7 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 2281.172 ; gain = 79.680 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 2287.406 ; gain = 85.613 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 2f0d6e4e8 +Phase 2.1 Fix Topology Constraints | Checksum: 27a83afa7 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 2281.172 ; gain = 79.680 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 2287.414 ; gain = 85.621 Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 2f0d6e4e8 +Phase 2.2 Pre Route Cleanup | Checksum: 27a83afa7 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 2281.172 ; gain = 79.680 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 2287.414 ; gain = 85.621 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing -Phase 2.3 Update Timing | Checksum: 26b5a1b04 +Phase 2.3 Update Timing | Checksum: 17a8d6394 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 2298.930 ; gain = 97.438 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.420 | TNS=0.000 | WHS=-0.094 | THS=-28.831| +Time (s): cpu = 00:00:08 ; elapsed = 00:00:18 . Memory (MB): peak = 2305.191 ; gain = 103.398 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.776 | TNS=0.000 | WHS=-0.119 | THS=-29.698| Router Utilization Summary @@ -532,93 +533,86 @@ Router Utilization Summary Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. - Number of Failed Nets = 21870 + Number of Failed Nets = 21867 (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 21870 + Number of Unrouted Nets = 21867 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 2 Router Initialization | Checksum: 1e43d66bb +Phase 2 Router Initialization | Checksum: 17e574e9c -Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 2335.145 ; gain = 133.652 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.195 ; gain = 145.402 Phase 3 Initial Routing Phase 3.1 Global Routing -Phase 3.1 Global Routing | Checksum: 1e43d66bb +Phase 3.1 Global Routing | Checksum: 17e574e9c -Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 2335.145 ; gain = 133.652 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.195 ; gain = 145.402 Phase 3.2 Initial Net Routing -Phase 3.2 Initial Net Routing | Checksum: 2f8d11093 +Phase 3.2 Initial Net Routing | Checksum: 272722ad6 -Time (s): cpu = 00:00:09 ; elapsed = 00:00:18 . Memory (MB): peak = 2339.484 ; gain = 137.992 -Phase 3 Initial Routing | Checksum: 2f8d11093 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 2350.590 ; gain = 148.797 +Phase 3 Initial Routing | Checksum: 272722ad6 -Time (s): cpu = 00:00:09 ; elapsed = 00:00:18 . Memory (MB): peak = 2339.484 ; gain = 137.992 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 2350.590 ; gain = 148.797 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 3181 - Number of Nodes with overlaps = 190 - Number of Nodes with overlaps = 29 - Number of Nodes with overlaps = 7 - Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 2990 + Number of Nodes with overlaps = 252 + Number of Nodes with overlaps = 65 + Number of Nodes with overlaps = 17 + Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.975 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.677 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 20c3fb659 +Phase 4.1 Global Iteration 0 | Checksum: 288010d2c -Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 2344.332 ; gain = 142.840 -Phase 4 Rip-up And Reroute | Checksum: 20c3fb659 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949 +Phase 4 Rip-up And Reroute | Checksum: 288010d2c -Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 2344.332 ; gain = 142.840 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp +Phase 5.1 Delay CleanUp | Checksum: 288010d2c -Phase 5.1.1 Update Timing -Phase 5.1.1 Update Timing | Checksum: 2767bd1b6 - -Time (s): cpu = 00:00:12 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.054 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 5.1 Delay CleanUp | Checksum: 2767bd1b6 - -Time (s): cpu = 00:00:12 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 2767bd1b6 +Phase 5.2 Clock Skew Optimization | Checksum: 288010d2c -Time (s): cpu = 00:00:12 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840 -Phase 5 Delay and Skew Optimization | Checksum: 2767bd1b6 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949 +Phase 5 Delay and Skew Optimization | Checksum: 288010d2c -Time (s): cpu = 00:00:12 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 25eb86b71 +Phase 6.1.1 Update Timing | Checksum: 271761283 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.054 | TNS=0.000 | WHS=0.045 | THS=0.000 | +Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2358.742 ; gain = 156.949 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.677 | TNS=0.000 | WHS=0.055 | THS=0.000 | -Phase 6.1 Hold Fix Iter | Checksum: 1cfa691ef +Phase 6.1 Hold Fix Iter | Checksum: 271761283 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840 -Phase 6 Post Hold Fix | Checksum: 1cfa691ef +Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2358.742 ; gain = 156.949 +Phase 6 Post Hold Fix | Checksum: 271761283 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2358.742 ; gain = 156.949 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 14.3318 % - Global Horizontal Routing Utilization = 14.5862 % + Global Vertical Routing Utilization = 13.8992 % + Global Horizontal Routing Utilization = 14.3475 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -628,44 +622,44 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 7 Route finalize | Checksum: 1cfa691ef +Phase 7 Route finalize | Checksum: 271761283 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2358.742 ; gain = 156.949 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 1cfa691ef +Phase 8 Verifying routed nets | Checksum: 271761283 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 2346.379 ; gain = 144.887 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2360.758 ; gain = 158.965 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 1bd3fc6ab +Phase 9 Depositing Routes | Checksum: 20252a6c4 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 2346.379 ; gain = 144.887 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2361.215 ; gain = 159.422 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=3.054 | TNS=0.000 | WHS=0.045 | THS=0.000 | +INFO: [Route 35-57] Estimated Timing Summary | WNS=2.677 | TNS=0.000 | WHS=0.055 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 1bd3fc6ab +Phase 10 Post Router Timing | Checksum: 20252a6c4 -Time (s): cpu = 00:00:14 ; elapsed = 00:00:29 . Memory (MB): peak = 2346.379 ; gain = 144.887 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:34 . Memory (MB): peak = 2361.215 ; gain = 159.422 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing -Phase 11 Post-Route Event Processing | Checksum: c96e4205 +Phase 11 Post-Route Event Processing | Checksum: d1fb966c -Time (s): cpu = 00:00:14 ; elapsed = 00:00:29 . Memory (MB): peak = 2346.379 ; gain = 144.887 -Ending Routing Task | Checksum: c96e4205 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:35 . Memory (MB): peak = 2361.215 ; gain = 159.422 +Ending Routing Task | Checksum: d1fb966c -Time (s): cpu = 00:00:14 ; elapsed = 00:00:30 . Memory (MB): peak = 2346.379 ; gain = 144.887 +Time (s): cpu = 00:00:14 ; elapsed = 00:00:35 . Memory (MB): peak = 2361.215 ; gain = 159.422 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation -90 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +88 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:30 . Memory (MB): peak = 2346.379 ; gain = 178.332 +route_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:36 . Memory (MB): peak = 2361.215 ; gain = 191.535 INFO: [runtcl-4] Executing : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx Command: report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. @@ -678,14 +672,14 @@ INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt. report_methodology completed successfully -report_methodology: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2414.371 ; gain = 67.992 +report_methodology: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2429.797 ; gain = 68.582 INFO: [runtcl-4] Executing : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx Command: report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation -100 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +98 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [runtcl-4] Executing : report_route_status -file CPU_route_status.rpt -pb CPU_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file CPU_timing_summary_routed.rpt -pb CPU_timing_summary_routed.pb -rpx CPU_timing_summary_routed.rpx -warn_on_violation @@ -698,16 +692,16 @@ INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU_bus_sk INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 2476.137 ; gain = 3.938 -Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2476.574 ; gain = 1.379 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2476.574 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 2488.125 ; gain = 4.934 +Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2488.125 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2488.125 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.170 . Memory (MB): peak = 2476.574 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 2476.574 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2476.574 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2476.574 ; gain = 4.375 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.215 . Memory (MB): peak = 2488.125 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2488.125 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2488.125 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2488.125 ; gain = 4.934 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_routed.dcp' has been generated. Command: write_bitstream -force CPU.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -751,5 +745,5 @@ INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT dev INFO: [Common 17-83] Releasing license: Implementation 14 Infos, 13 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 2944.602 ; gain = 468.027 -INFO: [Common 17-206] Exiting Vivado at Fri Jul 12 00:11:53 2024... +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2951.012 ; gain = 462.887 +INFO: [Common 17-206] Exiting Vivado at Fri Jul 12 21:07:14 2024... diff --git a/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt index 179a2c4..d9a8574 100644 --- a/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 00:11:40 2024 +| Date : Fri Jul 12 21:06:59 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_bus_skew -warn_on_violation -file CPU_bus_skew_routed.rpt -pb CPU_bus_skew_routed.pb -rpx CPU_bus_skew_routed.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt index b657a95..297f2d9 100644 --- a/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 00:11:40 2024 +| Date : Fri Jul 12 21:06:59 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_clock_utilization -file CPU_clock_utilization_routed.rpt | Design : CPU @@ -50,7 +50,7 @@ Table of Contents +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+ -| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 6 | 18132 | 0 | 20.000 | clk_out1_phase_locked_loop | pll/inst/clkout1_buf/O | pll/inst/clk_out1 | +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 6 | 18130 | 0 | 20.000 | clk_out1_phase_locked_loop | pll/inst/clkout1_buf/O | pll/inst/clk_out1 | | g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 1 | 0 | 20.000 | clkfbout_phase_locked_loop | pll/inst/clkf_buf/O | pll/inst/clkfbout_buf_phase_locked_loop | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered @@ -78,12 +78,12 @@ Table of Contents +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1725 | 1200 | 600 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3755 | 1500 | 1133 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | -| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2206 | 1200 | 708 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4046 | 1500 | 1149 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | -| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4593 | 1800 | 889 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 1807 | 950 | 526 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | +| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1534 | 1200 | 474 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3394 | 1500 | 972 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2590 | 1200 | 888 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4413 | 1500 | 1301 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4412 | 1800 | 855 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 1787 | 950 | 508 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts @@ -107,7 +107,7 @@ All Modules +-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+ -| g0 | BUFG/O | n/a | clk_out1_phase_locked_loop | 20.000 | {0.000 10.000} | 18132 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | BUFG/O | n/a | clk_out1_phase_locked_loop | 20.000 | {0.000 10.000} | 18130 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types @@ -118,9 +118,9 @@ All Modules +----+-------+-------+-----------------------+ | | X0 | X1 | HORIZONTAL PROG DELAY | +----+-------+-------+-----------------------+ -| Y2 | 4593 | 1807 | 0 | -| Y1 | 2206 | 4046 | 0 | -| Y0 | 1725 | 3755 | 0 | +| Y2 | 4412 | 1787 | 0 | +| Y1 | 2590 | 4413 | 0 | +| Y0 | 1534 | 3394 | 0 | +----+-------+-------+-----------------------+ @@ -153,7 +153,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 1725 | 0 | 1725 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 1534 | 0 | 1534 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -166,7 +166,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+ -| g0 | n/a | BUFG/O | None | 3755 | 0 | 3755 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 3394 | 0 | 3394 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | | g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | pll/inst/clkfbout_buf_phase_locked_loop | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered @@ -180,7 +180,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 2206 | 0 | 2206 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 2590 | 0 | 2590 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -193,7 +193,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 4046 | 0 | 4046 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 4413 | 0 | 4413 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -206,7 +206,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 4593 | 0 | 4593 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 4412 | 0 | 4412 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -219,7 +219,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 1807 | 0 | 1807 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 1787 | 0 | 1787 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads diff --git a/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt b/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt index d40570d..ddb3b28 100644 --- a/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 00:10:49 2024 +| Date : Fri Jul 12 21:06:00 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_control_sets -verbose -file CPU_control_sets_placed.rpt | Design : CPU @@ -27,7 +27,7 @@ Table of Contents | Minimum number of control sets | 547 | | Addition due to synthesis replication | 0 | | Addition due to physical synthesis replication | 0 | -| Unused register locations in slices containing registers | 12 | +| Unused register locations in slices containing registers | 14 | +----------------------------------------------------------+-------+ * Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers ** Run report_qor_suggestions for automated merging and remapping suggestions @@ -60,10 +60,10 @@ Table of Contents +--------------+-----------------------+------------------------+-----------------+--------------+ | No | No | No | 0 | 0 | | No | No | Yes | 0 | 0 | -| No | Yes | No | 712 | 221 | +| No | Yes | No | 710 | 237 | | Yes | No | No | 0 | 0 | | Yes | No | Yes | 0 | 0 | -| Yes | Yes | No | 17420 | 7427 | +| Yes | Yes | No | 17420 | 7064 | +--------------+-----------------------+------------------------+-----------------+--------------+ @@ -73,553 +73,553 @@ Table of Contents +--------------------+------------------------------------------------------------+-----------------------------------+------------------+----------------+--------------+ | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | +--------------------+------------------------------------------------------------+-----------------------------------+------------------+----------------+--------------+ -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_4[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_56[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | write_back/WB_register_write_reg_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[24][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[4][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[3]_3[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[1]_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/E[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[23][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[11][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[18][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[19][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[2][31]_i_1_n_0 | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[17][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[21][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[30][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[4][31]_i_1_n_0 | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[28][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | | pll/inst/clk_out1 | instruction_decode/register_file/registers[3][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[2][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[23][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[17][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[5][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[22][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[26][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[10][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[14][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[16][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[13][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[19][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[30][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[11][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[8][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[21][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[27][31]_i_1_n_0 | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[29][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[7][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[31][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[28][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[25][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/p_0_in | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[18][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[9][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[20][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[12][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/E[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/E[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_10[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_11[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_13[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_15[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_12[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_19[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_21[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_6[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_24[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_5[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_0[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__9_0[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_4[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_4[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__17_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_5[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_0[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_0[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_17[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_7[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_0[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_18[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_20[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_2[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_3[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[16][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[12][31]_i_1_n_0 | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | instruction_decode/register_file/p_0_in | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[13][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[22][31]_i_1_n_0 | data_memory/reset | 19 | 32 | 1.68 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[25][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[31][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[5][31]_i_1_n_0 | data_memory/reset | 20 | 32 | 1.60 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[27][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[10][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[14][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[26][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[29][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[7][31]_i_1_n_0 | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[24][31]_i_1_n_0 | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[8][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[9][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_0[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/E[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_10[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_1[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_0[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_11[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_5[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_13[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_15[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_5[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_5[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_2[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_2[0] | data_memory/reset | 19 | 32 | 1.68 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_4[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_3[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_4[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_2[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__17_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_0[0] | data_memory/reset | 10 | 32 | 3.20 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__26_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_16[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_22[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_27[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_28[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_23[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__14_1[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_14[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_25[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_26[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_3[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_0[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_2[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_0[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_4[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_0[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_13[0] | data_memory/reset | 16 | 32 | 2.00 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__19_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__27_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_0[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_5[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__29_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__31_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_4[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_4[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_1[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_0[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_5[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_4[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_4[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_0[0] | data_memory/reset | 14 | 32 | 2.29 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_1[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[3]_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_8[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_9[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_3[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_0[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__19_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_0[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_2[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_3[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_2[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_6[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_5[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_2[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_14[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_16[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_4[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_2[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_28[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_7[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_8[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_5[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_7[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_11[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_11[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_14[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_15[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_10[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_29[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_26[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_13[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_13[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_20[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_3[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_6[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_1[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_31[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_19[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_10[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_11[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_10[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_16[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_8[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_12[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_17[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__31_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_12[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_22[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_23[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_17[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_12[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_18[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_19[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_30[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_2[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_0[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_18[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_24[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_13[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_14[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_27[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_15[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_6[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_21[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_6[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__9_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_1[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_0[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_7[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_8[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_12[0] | data_memory/reset | 20 | 32 | 1.60 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_2[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_10[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_11[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_14[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_4[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_12[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_0[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__14_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_5[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_6[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_3[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__19_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_4[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_4[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__29_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__19_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__31_2[0] | data_memory/reset | 7 | 32 | 4.57 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_1[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_2[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_5[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_5[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_4[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_1[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__23_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_8[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_9[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_1[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_2[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__19_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__19_3[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_3[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_2[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_7[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_5[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__23_4[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_4[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | write_back/WB_register_write_reg_1[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_16[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_3[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__23_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_5[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_3[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_4[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__23_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_3[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_6[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__27_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_2[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__31_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_3[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_13[0] | data_memory/reset | 10 | 32 | 3.20 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_25[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_5[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_0[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_5[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_6[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_7[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_12[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_22[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_8[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_9[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_10[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_12[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_21[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_25[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_18[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_31[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_0[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_22[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_5[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_4[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_7[0] | data_memory/reset | 20 | 32 | 1.60 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_8[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_10[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_30[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_10[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_12[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_10[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_9[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_11[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_28[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_23[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_7[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_3[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_18[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_13[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_14[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_8[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_17[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_16[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_17[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_5[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_15[0] | data_memory/reset | 10 | 32 | 3.20 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_19[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_13[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_14[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_9[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_15[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_22[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_16[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_18[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_37[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_11[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_19[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_17[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_24[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_32[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_8[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_20[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_23[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_27[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_24[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_25[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_5[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_6[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_13[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_7[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_15[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_16[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_17[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_20[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_23[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_28[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_29[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_30[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_33[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_34[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_35[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_36[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_10[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_11[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_21[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_4[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_14[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_26[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_38[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_4[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_4[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_7[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_24[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_29[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_37[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_8[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_10[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_5[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_9[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_30[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_13[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_6[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_22[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_27[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_35[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_4[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_40[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_7[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_12[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_26[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_32[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_23[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_36[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_39[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_28[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_3[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_41[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_14[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_1[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_31[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_18[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_19[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_23[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_25[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_26[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_27[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_16[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_20[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_33[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_11[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_10[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_11[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_20[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_12[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_6[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_6[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_18[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_13[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_20[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_27[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_15[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_24[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_26[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_29[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_14[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_21[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_2[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_31[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_11[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_0[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_16[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_0[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_9[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_14[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_19[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_24[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_17[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_22[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_4[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_12[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_11[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_13[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_14[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_36[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_8[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_33[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_11[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_12[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_14[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_22[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_25[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_35[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_4[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_29[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_6[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_38[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_10[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_3[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_15[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_30[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_17[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_22[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_24[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_25[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_38[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_6[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_29[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_31[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_32[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_37[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_5[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_7[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_16[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_32[0] | data_memory/reset | 19 | 32 | 1.68 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_17[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_18[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_8[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_19[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_21[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_34[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_20[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_28[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_32[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_6[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_7[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_13[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_20[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_24[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_8[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_48[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_34[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_15[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_4[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_7[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_27[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_49[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_50[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_9[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_33[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_11[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_34[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_20[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_27[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_21[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_20[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_6[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_7[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_24[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_23[0] | data_memory/reset | 19 | 32 | 1.68 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_18[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_19[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_21[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_0[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_23[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_15[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_26[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_28[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_9[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_16[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_13[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_30[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_9[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_31[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_10[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_10[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_11[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_33[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_26[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_35[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_29[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_0[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_25[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_24[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_32[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_7[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_11[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_29[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_30[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_15[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_16[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_19[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_20[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_12[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_18[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_26[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_9[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_27[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_24[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_30[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_31[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_21[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_7[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_9[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_36[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_21[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_22[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_28[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_8[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_27[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_4[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_28[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_17[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_32[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_31[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_13[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_14[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_23[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_34[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_35[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_5[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_36[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_33[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_6[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_25[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_5[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_6[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_22[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_8[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_10[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_34[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_23[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_6[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_64[0] | data_memory/reset | 19 | 32 | 1.68 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_18[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_13[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_19[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_14[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_23[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_27[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_30[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_21[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_29[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_33[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_35[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_39[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_40[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_43[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_46[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_25[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_37[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_47[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_20[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_32[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_48[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_49[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_5[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_50[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_51[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_24[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_36[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_54[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_57[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_44[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_22[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_58[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_60[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_63[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_66[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_45[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_61[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_31[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_55[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_28[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_16[0] | data_memory/reset | 14 | 32 | 2.29 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_4[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_14[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_19[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_5[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_18[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_11[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_12[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_0[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_28[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_6[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_2[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_21[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_38[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_26[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_25[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_31[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_41[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_42[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_17[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_35[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_44[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_43[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_36[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_37[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_46[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_47[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_22[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_5[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_51[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_30[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_8[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_10[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_16[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_13[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_23[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_29[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_39[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_40[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_45[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_52[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_5[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_6[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_7[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_3[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_4[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_9[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_8[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_10[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_11[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_13[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_6[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_8[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_10[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_11[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_5[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_14[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_0[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_13[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_12[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_12[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_4[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_7[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_9[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_14[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_20[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_25[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_15[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_4[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_17[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_35[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_31[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_27[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_21[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_37[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_28[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_38[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_39[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_21[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_28[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_35[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_15[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_18[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_22[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_19[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_24[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_22[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_32[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_30[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_16[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_36[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_6[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_25[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_8[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_62[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_42[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_9[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_53[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_12[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_17[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_41[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_56[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_59[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_15[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_65[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_34[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_26[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_38[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_52[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_7[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_4[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_9[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_8[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_6[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_1[0] | data_memory/reset | 20 | 32 | 1.60 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_35[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_12[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_11[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_23[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_24[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_29[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_32[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_36[0] | data_memory/reset | 18 | 32 | 1.78 | | pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_18[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_19[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_23[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_27[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_11[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_24[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_17[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_27[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_4[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_8[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_30[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_34[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_4[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_0[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_14[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_26[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_7[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_5[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_33[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_29[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_29[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_30[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_31[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_13[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_32[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_33[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_5[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_23[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_16[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_34[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_26[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_36[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_10[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_20[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_34[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_0[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_7[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_46[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_55[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_5[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_41[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_47[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_43[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_49[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_53[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_7[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_11[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_13[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_9[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_15[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_19[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_0[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_6[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_8[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_10[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_13[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_10[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_10[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_12[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_16[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_17[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_6[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_21[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_9[0] | data_memory/reset | 19 | 32 | 1.68 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_22[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_20[0] | data_memory/reset | 20 | 32 | 1.60 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_25[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_28[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_31[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_0[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_33[0] | data_memory/reset | 19 | 32 | 1.68 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_27[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_22[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_30[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_4[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_40[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_45[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_51[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_18[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_35[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_11[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_20[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_16[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_24[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_26[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_28[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_43[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_47[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_49[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_54[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_56[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_14[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_42[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_52[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_44[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_57[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_61[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_9[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_54[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_48[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_60[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_4[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_45[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_51[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_58[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_13[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_17[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_55[0] | data_memory/reset | 13 | 32 | 2.46 | | pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_59[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_58[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_6[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_7[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_8[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_50[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_6[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_60[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_12[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_31[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_61[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_52[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_36[0] | data_memory/reset | 13 | 32 | 2.46 | | pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_62[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_63[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_40[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_63[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_23[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_32[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_41[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_46[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_8[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_57[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_38[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_25[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_48[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_7[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_15[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_33[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_29[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_34[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_39[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_50[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_53[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_19[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_37[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_21[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_44[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_9[0] | data_memory/reset | 11 | 32 | 2.91 | | pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_3[0] | data_memory/reset | 13 | 44 | 3.38 | -| pll/inst/clk_out1 | | instruction_decode/IFID_PC_plus_4 | 32 | 67 | 2.09 | -| pll/inst/clk_out1 | | execution/alu/SR[0] | 50 | 160 | 3.20 | -| pll/inst/clk_out1 | | data_memory/reset | 139 | 485 | 3.49 | +| pll/inst/clk_out1 | | instruction_decode/IFID_PC_plus_4 | 40 | 67 | 1.67 | +| pll/inst/clk_out1 | | instruction_decode/SR[0] | 53 | 160 | 3.02 | +| pll/inst/clk_out1 | | data_memory/reset | 144 | 483 | 3.35 | +--------------------+------------------------------------------------------------+-----------------------------------+------------------+----------------+--------------+ diff --git a/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt b/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt index 56bf871..94dc7bf 100644 --- a/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 00:10:18 2024 +| Date : Fri Jul 12 21:05:24 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt index 15f5c6a..abacd86 100644 --- a/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 00:11:29 2024 +| Date : Fri Jul 12 21:06:47 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt b/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt index 0f614cc..4248b09 100644 --- a/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 00:10:49 2024 +| Date : Fri Jul 12 21:06:00 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_io -file CPU_io_placed.rpt | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt index bfa0207..e9e162b 100644 --- a/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 00:11:34 2024 +| Date : Fri Jul 12 21:06:53 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_opt.dcp b/PipelineProcessor.runs/impl_1/CPU_opt.dcp index 7cea001..5a0b467 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_opt.dcp and b/PipelineProcessor.runs/impl_1/CPU_opt.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_physopt.dcp b/PipelineProcessor.runs/impl_1/CPU_physopt.dcp index 5a869ba..9fd52fe 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_physopt.dcp and b/PipelineProcessor.runs/impl_1/CPU_physopt.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_placed.dcp b/PipelineProcessor.runs/impl_1/CPU_placed.dcp index 96236b1..a1ba698 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_placed.dcp and b/PipelineProcessor.runs/impl_1/CPU_placed.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt index 12e8e78..210b924 100644 --- a/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 00:11:38 2024 +| Date : Fri Jul 12 21:06:57 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx | Design : CPU @@ -30,10 +30,10 @@ Table of Contents ---------- +--------------------------+--------------+ -| Total On-Chip Power (W) | 0.188 | +| Total On-Chip Power (W) | 0.187 | | Design Power Budget (W) | Unspecified* | | Power Budget Margin (W) | NA | -| Dynamic (W) | 0.120 | +| Dynamic (W) | 0.119 | | Device Static (W) | 0.069 | | Effective TJA (C/W) | 2.8 | | Max Ambient (C) | 84.5 | @@ -52,19 +52,19 @@ Table of Contents +----------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +----------------+-----------+----------+-----------+-----------------+ -| Clocks | 0.016 | 5 | --- | --- | -| Slice Logic | 0.003 | 29973 | --- | --- | -| LUT as Logic | 0.003 | 7991 | 20800 | 38.42 | +| Clocks | 0.015 | 5 | --- | --- | +| Slice Logic | 0.002 | 30077 | --- | --- | +| LUT as Logic | 0.002 | 8003 | 20800 | 38.48 | | CARRY4 | <0.001 | 39 | 8150 | 0.48 | -| Register | <0.001 | 18132 | 41600 | 43.59 | -| F7/F8 Muxes | <0.001 | 3440 | 32600 | 10.55 | +| Register | <0.001 | 18130 | 41600 | 43.58 | +| F7/F8 Muxes | <0.001 | 3514 | 32600 | 10.78 | | Others | 0.000 | 12 | --- | --- | -| Signals | 0.002 | 21870 | --- | --- | +| Signals | 0.002 | 21867 | --- | --- | | PLL | 0.099 | 1 | 5 | 20.00 | | DSPs | <0.001 | 3 | 90 | 3.33 | | I/O | <0.001 | 15 | 250 | 6.00 | | Static Power | 0.069 | | | | -| Total | 0.188 | | | | +| Total | 0.187 | | | | +----------------+-----------+----------+-----------+-----------------+ @@ -74,7 +74,7 @@ Table of Contents +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ -| Vccint | 1.000 | 0.039 | 0.030 | 0.010 | NA | Unspecified | NA | +| Vccint | 1.000 | 0.038 | 0.029 | 0.010 | NA | Unspecified | NA | | Vccaux | 1.800 | 0.063 | 0.050 | 0.013 | NA | Unspecified | NA | | Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | @@ -145,14 +145,13 @@ Table of Contents +----------------------+-----------+ | Name | Power (W) | +----------------------+-----------+ -| CPU | 0.120 | +| CPU | 0.119 | | data_memory | 0.014 | | instruction_decode | 0.002 | -| register_file | 0.001 | -| instruction_fetch | 0.001 | +| instruction_fetch | 0.002 | | pll | 0.100 | | inst | 0.100 | -| write_back | 0.002 | +| write_back | 0.001 | +----------------------+-----------+ diff --git a/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb b/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb index b1363ac..b3190bf 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb and b/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_route_status.pb b/PipelineProcessor.runs/impl_1/CPU_route_status.pb index e72b708..3e20761 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_route_status.pb and b/PipelineProcessor.runs/impl_1/CPU_route_status.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_route_status.rpt b/PipelineProcessor.runs/impl_1/CPU_route_status.rpt index c4ca3ca..6d15b26 100644 --- a/PipelineProcessor.runs/impl_1/CPU_route_status.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_route_status.rpt @@ -1,11 +1,11 @@ Design Route Status : # nets : ------------------------------------------- : ----------- : - # of logical nets.......................... : 30198 : - # of nets not needing routing.......... : 8321 : - # of internally routed nets........ : 8321 : - # of routable nets..................... : 21877 : - # of fully routed nets............. : 21877 : + # of logical nets.......................... : 30302 : + # of nets not needing routing.......... : 8428 : + # of internally routed nets........ : 8428 : + # of routable nets..................... : 21874 : + # of fully routed nets............. : 21874 : # of nets with routing errors.......... : 0 : ------------------------------------------- : ----------- : diff --git a/PipelineProcessor.runs/impl_1/CPU_routed.dcp b/PipelineProcessor.runs/impl_1/CPU_routed.dcp index 6280acc..48be280 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_routed.dcp and b/PipelineProcessor.runs/impl_1/CPU_routed.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb index 164b4ac..fd83a94 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb and b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt index 5917b41..c6f288f 100644 --- a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 00:11:39 2024 +| Date : Fri Jul 12 21:06:58 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -report_unconstrained -file CPU_timing_summary_routed.rpt -pb CPU_timing_summary_routed.pb -rpx CPU_timing_summary_routed.rpx -warn_on_violation | Design : CPU @@ -142,7 +142,7 @@ Table of Contents WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 3.054 0.000 0 35779 0.045 0.000 0 35779 3.000 0.000 0 18138 + 2.677 0.000 0 35777 0.055 0.000 0 35777 3.000 0.000 0 18136 All user specified timing constraints are met. @@ -168,7 +168,7 @@ hardware_clk {0.000 5.000} 10.000 100.000 Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- hardware_clk 3.000 0.000 0 1 - clk_out1_phase_locked_loop 3.054 0.000 0 35779 0.045 0.000 0 35779 9.500 0.000 0 18134 + clk_out1_phase_locked_loop 2.677 0.000 0 35777 0.055 0.000 0 35777 9.500 0.000 0 18132 clkfbout_phase_locked_loop 17.845 0.000 0 3 @@ -248,28 +248,28 @@ High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 5.000 From Clock: clk_out1_phase_locked_loop To Clock: clk_out1_phase_locked_loop -Setup : 0 Failing Endpoints, Worst Slack 3.054ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.045ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 2.677ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.055ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 9.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 3.054ns (required time - arrival time) - Source: write_back/WB_register_write_reg/C +Slack (MET) : 2.677ns (required time - arrival time) + Source: execution/EX_rt_address_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[25]/D + Destination: memory_access/MEM_ALU_result_reg[30]_rep/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.758ns (logic 7.998ns (47.725%) route 8.760ns (52.275%)) - Logic Levels: 12 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=3 LUT6=2) - Clock Path Skew: -0.111ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.029ns = ( 17.971 - 20.000 ) - Source Clock Delay (SCD): -2.343ns - Clock Pessimism Removal (CPR): -0.425ns + Data Path Delay: 16.869ns (logic 8.394ns (49.760%) route 8.475ns (50.240%)) + Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) + Clock Path Skew: -0.127ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.034ns = ( 17.966 - 20.000 ) + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -287,40 +287,46 @@ Slack (MET) : 3.054ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.633 -2.343 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_reg/C + net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 + SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X59Y37 FDRE (Prop_fdre_C_Q) 0.419 -1.924 f write_back/WB_register_write_reg/Q - net (fo=16, routed) 1.648 -0.276 write_back/WB_register_write - SLICE_X59Y37 LUT5 (Prop_lut5_I0_O) 0.297 0.021 r write_back/result0_i_49/O - net (fo=3, routed) 0.843 0.864 execution/result0__0 - SLICE_X58Y35 LUT4 (Prop_lut4_I1_O) 0.124 0.988 r execution/MEM_memory_write_data[31]_i_2/O - net (fo=46, routed) 1.291 2.280 execution/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X44Y41 LUT5 (Prop_lut5_I3_O) 0.124 2.404 r execution/MEM_memory_write_data[11]_i_1/O - net (fo=9, routed) 1.257 3.661 execution/EX_memory_write_data[11] - SLICE_X51Y32 LUT3 (Prop_lut3_I2_O) 0.124 3.785 r execution/result0_i_21/O - net (fo=16, routed) 0.855 4.640 execution/alu/result0__1_0[11] - DSP48_X1Y10 DSP48E1 (Prop_dsp48e1_B[11]_PCOUT[47]) - 3.851 8.491 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.493 execution/alu/result0__0_n_106 - DSP48_X1Y11 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[3]) - 1.518 10.011 r execution/alu/result0__1/P[3] - net (fo=2, routed) 0.982 10.993 execution/alu/result0__1_n_102 - SLICE_X55Y27 LUT2 (Prop_lut2_I0_O) 0.124 11.117 r execution/alu/i__carry__0_i_4__1/O - net (fo=1, routed) 0.000 11.117 execution/alu/i__carry__0_i_4__1_n_0 - SLICE_X55Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 11.649 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.649 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X55Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 11.983 r execution/alu/result0_inferred__11/i__carry__1/O[1] - net (fo=1, routed) 0.692 12.675 execution/alu/result0_inferred__11/i__carry__1_n_6 - SLICE_X62Y29 LUT6 (Prop_lut6_I5_O) 0.303 12.978 r execution/alu/MEM_ALU_result[25]_i_10/O - net (fo=1, routed) 0.641 13.619 execution/alu/MEM_ALU_result[25]_i_10_n_0 - SLICE_X63Y29 LUT5 (Prop_lut5_I4_O) 0.124 13.743 f execution/alu/MEM_ALU_result[25]_i_5/O - net (fo=1, routed) 0.548 14.291 execution/alu/MEM_ALU_result[25]_i_5_n_0 - SLICE_X57Y30 LUT6 (Prop_lut6_I5_O) 0.124 14.415 r execution/alu/MEM_ALU_result[25]_i_1/O - net (fo=1, routed) 0.000 14.415 memory_access/prev_ALU_result[25] - SLICE_X57Y30 FDRE r memory_access/MEM_ALU_result_reg[25]/D + SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q + net (fo=4, routed) 1.044 -0.850 execution/Q[2] + SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O + net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 + SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O + net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 + SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O + net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] + SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O + net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] + DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) + 4.053 7.660 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 + DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.180 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 + SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O + net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 + SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.018 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.018 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 11.257 r execution/alu/result0_inferred__11/i__carry__2/O[2] + net (fo=1, routed) 0.449 11.706 execution/alu/result0_inferred__11/i__carry__2_n_5 + SLICE_X8Y36 LUT6 (Prop_lut6_I5_O) 0.302 12.008 r execution/alu/MEM_ALU_result[30]_i_6/O + net (fo=1, routed) 0.727 12.735 execution/alu/MEM_ALU_result[30]_i_6_n_0 + SLICE_X12Y36 LUT6 (Prop_lut6_I5_O) 0.124 12.859 r execution/alu/MEM_ALU_result[30]_i_3/O + net (fo=1, routed) 0.000 12.859 execution/alu/MEM_ALU_result[30]_i_3_n_0 + SLICE_X12Y36 MUXF7 (Prop_muxf7_I1_O) 0.214 13.073 r execution/alu/MEM_ALU_result_reg[30]_i_1/O + net (fo=3, routed) 1.385 14.457 memory_access/prev_ALU_result[30] + SLICE_X13Y59 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -333,119 +339,31 @@ Slack (MET) : 3.054ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.442 17.971 memory_access/clk_out1 - SLICE_X57Y30 FDRE r memory_access/MEM_ALU_result_reg[25]/C - clock pessimism -0.425 17.546 - clock uncertainty -0.108 17.438 - SLICE_X57Y30 FDRE (Setup_fdre_C_D) 0.031 17.469 memory_access/MEM_ALU_result_reg[25] + net (fo=18130, routed) 1.438 17.966 memory_access/clk_out1 + SLICE_X13Y59 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/C + clock pessimism -0.505 17.461 + clock uncertainty -0.108 17.354 + SLICE_X13Y59 FDRE (Setup_fdre_C_D) -0.220 17.134 memory_access/MEM_ALU_result_reg[30]_rep ------------------------------------------------------------------- - required time 17.469 - arrival time -14.415 + required time 17.134 + arrival time -14.457 ------------------------------------------------------------------- - slack 3.054 + slack 2.677 -Slack (MET) : 3.197ns (required time - arrival time) - Source: write_back/WB_register_write_reg/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[26]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.618ns (logic 7.902ns (47.551%) route 8.716ns (52.449%)) - Logic Levels: 12 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=3 LUT6=2) - Clock Path Skew: -0.108ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.026ns = ( 17.974 - 20.000 ) - Source Clock Delay (SCD): -2.343ns - Clock Pessimism Removal (CPR): -0.425ns - Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.633 -2.343 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X59Y37 FDRE (Prop_fdre_C_Q) 0.419 -1.924 f write_back/WB_register_write_reg/Q - net (fo=16, routed) 1.648 -0.276 write_back/WB_register_write - SLICE_X59Y37 LUT5 (Prop_lut5_I0_O) 0.297 0.021 r write_back/result0_i_49/O - net (fo=3, routed) 0.843 0.864 execution/result0__0 - SLICE_X58Y35 LUT4 (Prop_lut4_I1_O) 0.124 0.988 r execution/MEM_memory_write_data[31]_i_2/O - net (fo=46, routed) 1.291 2.280 execution/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X44Y41 LUT5 (Prop_lut5_I3_O) 0.124 2.404 r execution/MEM_memory_write_data[11]_i_1/O - net (fo=9, routed) 1.257 3.661 execution/EX_memory_write_data[11] - SLICE_X51Y32 LUT3 (Prop_lut3_I2_O) 0.124 3.785 r execution/result0_i_21/O - net (fo=16, routed) 0.855 4.640 execution/alu/result0__1_0[11] - DSP48_X1Y10 DSP48E1 (Prop_dsp48e1_B[11]_PCOUT[47]) - 3.851 8.491 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.493 execution/alu/result0__0_n_106 - DSP48_X1Y11 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[3]) - 1.518 10.011 r execution/alu/result0__1/P[3] - net (fo=2, routed) 0.982 10.993 execution/alu/result0__1_n_102 - SLICE_X55Y27 LUT2 (Prop_lut2_I0_O) 0.124 11.117 r execution/alu/i__carry__0_i_4__1/O - net (fo=1, routed) 0.000 11.117 execution/alu/i__carry__0_i_4__1_n_0 - SLICE_X55Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 11.649 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.649 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X55Y28 CARRY4 (Prop_carry4_CI_O[2]) - 0.239 11.888 r execution/alu/result0_inferred__11/i__carry__1/O[2] - net (fo=1, routed) 0.710 12.598 execution/alu/result0_inferred__11/i__carry__1_n_5 - SLICE_X62Y29 LUT6 (Prop_lut6_I5_O) 0.302 12.900 r execution/alu/MEM_ALU_result[26]_i_9/O - net (fo=1, routed) 0.433 13.333 execution/alu/MEM_ALU_result[26]_i_9_n_0 - SLICE_X62Y29 LUT5 (Prop_lut5_I4_O) 0.124 13.457 f execution/alu/MEM_ALU_result[26]_i_3/O - net (fo=1, routed) 0.694 14.151 execution/alu/MEM_ALU_result[26]_i_3_n_0 - SLICE_X57Y32 LUT6 (Prop_lut6_I3_O) 0.124 14.275 r execution/alu/MEM_ALU_result[26]_i_1/O - net (fo=1, routed) 0.000 14.275 memory_access/prev_ALU_result[26] - SLICE_X57Y32 FDRE r memory_access/MEM_ALU_result_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 20.000 20.000 r - R4 0.000 20.000 r hardware_clk (IN) - net (fo=0) 0.000 20.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.445 17.974 memory_access/clk_out1 - SLICE_X57Y32 FDRE r memory_access/MEM_ALU_result_reg[26]/C - clock pessimism -0.425 17.549 - clock uncertainty -0.108 17.441 - SLICE_X57Y32 FDRE (Setup_fdre_C_D) 0.031 17.472 memory_access/MEM_ALU_result_reg[26] - ------------------------------------------------------------------- - required time 17.472 - arrival time -14.275 - ------------------------------------------------------------------- - slack 3.197 - -Slack (MET) : 3.483ns (required time - arrival time) - Source: write_back/WB_register_write_reg/C +Slack (MET) : 2.829ns (required time - arrival time) + Source: execution/EX_rt_address_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[30]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.363ns (logic 7.892ns (48.232%) route 8.471ns (51.768%)) - Logic Levels: 12 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=2 LUT6=2) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.963ns = ( 18.037 - 20.000 ) - Source Clock Delay (SCD): -2.343ns - Clock Pessimism Removal (CPR): -0.411ns + Data Path Delay: 16.733ns (logic 8.394ns (50.165%) route 8.339ns (49.835%)) + Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) + Clock Path Skew: -0.127ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.034ns = ( 17.966 - 20.000 ) + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -463,41 +381,46 @@ Slack (MET) : 3.483ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.633 -2.343 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_reg/C + net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 + SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X59Y37 FDRE (Prop_fdre_C_Q) 0.419 -1.924 f write_back/WB_register_write_reg/Q - net (fo=16, routed) 1.648 -0.276 write_back/WB_register_write - SLICE_X59Y37 LUT5 (Prop_lut5_I0_O) 0.297 0.021 r write_back/result0_i_49/O - net (fo=3, routed) 0.843 0.864 execution/result0__0 - SLICE_X58Y35 LUT4 (Prop_lut4_I1_O) 0.124 0.988 r execution/MEM_memory_write_data[31]_i_2/O - net (fo=46, routed) 1.291 2.280 execution/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X44Y41 LUT5 (Prop_lut5_I3_O) 0.124 2.404 r execution/MEM_memory_write_data[11]_i_1/O - net (fo=9, routed) 1.257 3.661 execution/EX_memory_write_data[11] - SLICE_X51Y32 LUT3 (Prop_lut3_I2_O) 0.124 3.785 r execution/result0_i_21/O - net (fo=16, routed) 0.855 4.640 execution/alu/result0__1_0[11] - DSP48_X1Y10 DSP48E1 (Prop_dsp48e1_B[11]_PCOUT[47]) - 3.851 8.491 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.493 execution/alu/result0__0_n_106 - DSP48_X1Y11 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[3]) - 1.518 10.011 r execution/alu/result0__1/P[3] - net (fo=2, routed) 0.982 10.993 execution/alu/result0__1_n_102 - SLICE_X55Y27 LUT2 (Prop_lut2_I0_O) 0.124 11.117 r execution/alu/i__carry__0_i_4__1/O - net (fo=1, routed) 0.000 11.117 execution/alu/i__carry__0_i_4__1_n_0 - SLICE_X55Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 11.649 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.649 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X55Y28 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.763 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.763 execution/alu/result0_inferred__11/i__carry__1_n_0 - SLICE_X55Y29 CARRY4 (Prop_carry4_CI_O[2]) - 0.239 12.002 r execution/alu/result0_inferred__11/i__carry__2/O[2] - net (fo=1, routed) 0.306 12.309 execution/alu/result0_inferred__11/i__carry__2_n_5 - SLICE_X57Y29 LUT6 (Prop_lut6_I4_O) 0.302 12.611 f execution/alu/MEM_ALU_result[30]_i_3/O - net (fo=2, routed) 0.588 13.199 execution/alu/MEM_ALU_result[30]_i_3_n_0 - SLICE_X57Y31 LUT6 (Prop_lut6_I1_O) 0.124 13.323 r execution/alu/MEM_ALU_result[30]_i_1/O - net (fo=1, routed) 0.697 14.020 memory_access/prev_ALU_result[30] - SLICE_X60Y31 FDRE r memory_access/MEM_ALU_result_reg[30]/D + SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q + net (fo=4, routed) 1.044 -0.850 execution/Q[2] + SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O + net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 + SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O + net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 + SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O + net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] + SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O + net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] + DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) + 4.053 7.660 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 + DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.180 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 + SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O + net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 + SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.018 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.018 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 11.257 r execution/alu/result0_inferred__11/i__carry__2/O[2] + net (fo=1, routed) 0.449 11.706 execution/alu/result0_inferred__11/i__carry__2_n_5 + SLICE_X8Y36 LUT6 (Prop_lut6_I5_O) 0.302 12.008 r execution/alu/MEM_ALU_result[30]_i_6/O + net (fo=1, routed) 0.727 12.735 execution/alu/MEM_ALU_result[30]_i_6_n_0 + SLICE_X12Y36 LUT6 (Prop_lut6_I5_O) 0.124 12.859 r execution/alu/MEM_ALU_result[30]_i_3/O + net (fo=1, routed) 0.000 12.859 execution/alu/MEM_ALU_result[30]_i_3_n_0 + SLICE_X12Y36 MUXF7 (Prop_muxf7_I1_O) 0.214 13.073 r execution/alu/MEM_ALU_result_reg[30]_i_1/O + net (fo=3, routed) 1.248 14.321 memory_access/prev_ALU_result[30] + SLICE_X12Y60 FDRE r memory_access/MEM_ALU_result_reg[30]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -510,31 +433,31 @@ Slack (MET) : 3.483ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.508 18.037 memory_access/clk_out1 - SLICE_X60Y31 FDRE r memory_access/MEM_ALU_result_reg[30]/C - clock pessimism -0.411 17.626 - clock uncertainty -0.108 17.518 - SLICE_X60Y31 FDRE (Setup_fdre_C_D) -0.016 17.502 memory_access/MEM_ALU_result_reg[30] + net (fo=18130, routed) 1.438 17.966 memory_access/clk_out1 + SLICE_X12Y60 FDRE r memory_access/MEM_ALU_result_reg[30]/C + clock pessimism -0.505 17.461 + clock uncertainty -0.108 17.354 + SLICE_X12Y60 FDRE (Setup_fdre_C_D) -0.204 17.150 memory_access/MEM_ALU_result_reg[30] ------------------------------------------------------------------- - required time 17.502 - arrival time -14.020 + required time 17.150 + arrival time -14.321 ------------------------------------------------------------------- - slack 3.483 + slack 2.829 -Slack (MET) : 3.570ns (required time - arrival time) - Source: write_back/WB_register_write_reg/C +Slack (MET) : 3.117ns (required time - arrival time) + Source: execution/EX_rt_address_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[21]/D + Destination: memory_access/MEM_ALU_result_reg[30]_rep__0/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.240ns (logic 8.016ns (49.358%) route 8.224ns (50.642%)) - Logic Levels: 12 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=3 LUT6=2) - Clock Path Skew: -0.111ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.029ns = ( 17.971 - 20.000 ) - Source Clock Delay (SCD): -2.343ns - Clock Pessimism Removal (CPR): -0.425ns + Data Path Delay: 16.446ns (logic 8.394ns (51.039%) route 8.052ns (48.961%)) + Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) + Clock Path Skew: -0.125ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.032ns = ( 17.968 - 20.000 ) + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -552,40 +475,46 @@ Slack (MET) : 3.570ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.633 -2.343 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_reg/C + net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 + SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X59Y37 FDRE (Prop_fdre_C_Q) 0.419 -1.924 f write_back/WB_register_write_reg/Q - net (fo=16, routed) 1.648 -0.276 write_back/WB_register_write - SLICE_X59Y37 LUT5 (Prop_lut5_I0_O) 0.297 0.021 r write_back/result0_i_49/O - net (fo=3, routed) 0.843 0.864 execution/result0__0 - SLICE_X58Y35 LUT4 (Prop_lut4_I1_O) 0.124 0.988 r execution/MEM_memory_write_data[31]_i_2/O - net (fo=46, routed) 1.291 2.280 execution/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X44Y41 LUT5 (Prop_lut5_I3_O) 0.124 2.404 r execution/MEM_memory_write_data[11]_i_1/O - net (fo=9, routed) 1.257 3.661 execution/EX_memory_write_data[11] - SLICE_X51Y32 LUT3 (Prop_lut3_I2_O) 0.124 3.785 r execution/result0_i_21/O - net (fo=16, routed) 0.855 4.640 execution/alu/result0__1_0[11] - DSP48_X1Y10 DSP48E1 (Prop_dsp48e1_B[11]_PCOUT[47]) - 3.851 8.491 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.493 execution/alu/result0__0_n_106 - DSP48_X1Y11 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 10.011 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.605 10.615 execution/alu/result0__1_n_105 - SLICE_X55Y26 LUT2 (Prop_lut2_I0_O) 0.124 10.739 r execution/alu/i__carry_i_3__1/O - net (fo=1, routed) 0.000 10.739 execution/alu/i__carry_i_3__1_n_0 - SLICE_X55Y26 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 11.289 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.289 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X55Y27 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 11.623 r execution/alu/result0_inferred__11/i__carry__0/O[1] - net (fo=1, routed) 0.657 12.281 execution/alu/result0_inferred__11/i__carry__0_n_6 - SLICE_X60Y27 LUT6 (Prop_lut6_I5_O) 0.303 12.584 r execution/alu/MEM_ALU_result[21]_i_8/O - net (fo=1, routed) 0.466 13.049 execution/alu/MEM_ALU_result[21]_i_8_n_0 - SLICE_X60Y27 LUT5 (Prop_lut5_I4_O) 0.124 13.173 r execution/alu/MEM_ALU_result[21]_i_3/O - net (fo=1, routed) 0.600 13.773 execution/alu/MEM_ALU_result[21]_i_3_n_0 - SLICE_X55Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.897 r execution/alu/MEM_ALU_result[21]_i_1/O - net (fo=1, routed) 0.000 13.897 memory_access/prev_ALU_result[21] - SLICE_X55Y31 FDRE r memory_access/MEM_ALU_result_reg[21]/D + SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q + net (fo=4, routed) 1.044 -0.850 execution/Q[2] + SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O + net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 + SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O + net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 + SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O + net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] + SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O + net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] + DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) + 4.053 7.660 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 + DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.180 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 + SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O + net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 + SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.018 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.018 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 11.257 r execution/alu/result0_inferred__11/i__carry__2/O[2] + net (fo=1, routed) 0.449 11.706 execution/alu/result0_inferred__11/i__carry__2_n_5 + SLICE_X8Y36 LUT6 (Prop_lut6_I5_O) 0.302 12.008 r execution/alu/MEM_ALU_result[30]_i_6/O + net (fo=1, routed) 0.727 12.735 execution/alu/MEM_ALU_result[30]_i_6_n_0 + SLICE_X12Y36 LUT6 (Prop_lut6_I5_O) 0.124 12.859 r execution/alu/MEM_ALU_result[30]_i_3/O + net (fo=1, routed) 0.000 12.859 execution/alu/MEM_ALU_result[30]_i_3_n_0 + SLICE_X12Y36 MUXF7 (Prop_muxf7_I1_O) 0.214 13.073 r execution/alu/MEM_ALU_result_reg[30]_i_1/O + net (fo=3, routed) 0.962 14.034 memory_access/prev_ALU_result[30] + SLICE_X12Y55 FDRE r memory_access/MEM_ALU_result_reg[30]_rep__0/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -598,31 +527,31 @@ Slack (MET) : 3.570ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.442 17.971 memory_access/clk_out1 - SLICE_X55Y31 FDRE r memory_access/MEM_ALU_result_reg[21]/C - clock pessimism -0.425 17.546 - clock uncertainty -0.108 17.438 - SLICE_X55Y31 FDRE (Setup_fdre_C_D) 0.029 17.467 memory_access/MEM_ALU_result_reg[21] + net (fo=18130, routed) 1.440 17.968 memory_access/clk_out1 + SLICE_X12Y55 FDRE r memory_access/MEM_ALU_result_reg[30]_rep__0/C + clock pessimism -0.505 17.463 + clock uncertainty -0.108 17.356 + SLICE_X12Y55 FDRE (Setup_fdre_C_D) -0.204 17.152 memory_access/MEM_ALU_result_reg[30]_rep__0 ------------------------------------------------------------------- - required time 17.467 - arrival time -13.897 + required time 17.152 + arrival time -14.034 ------------------------------------------------------------------- - slack 3.570 + slack 3.117 -Slack (MET) : 3.694ns (required time - arrival time) - Source: write_back/WB_register_write_reg/C +Slack (MET) : 4.099ns (required time - arrival time) + Source: execution/EX_rt_address_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[19]/D + Destination: memory_access/MEM_ALU_result_reg[29]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.117ns (logic 7.775ns (48.240%) route 8.342ns (51.760%)) - Logic Levels: 11 (CARRY4=1 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=2 LUT6=3) - Clock Path Skew: -0.112ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) - Source Clock Delay (SCD): -2.343ns - Clock Pessimism Removal (CPR): -0.425ns + Data Path Delay: 15.744ns (logic 8.521ns (54.123%) route 7.223ns (45.877%)) + Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) + Clock Path Skew: -0.113ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.028ns = ( 17.972 - 20.000 ) + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): -0.497ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -640,37 +569,46 @@ Slack (MET) : 3.694ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.633 -2.343 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_reg/C + net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 + SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X59Y37 FDRE (Prop_fdre_C_Q) 0.419 -1.924 f write_back/WB_register_write_reg/Q - net (fo=16, routed) 1.648 -0.276 write_back/WB_register_write - SLICE_X59Y37 LUT5 (Prop_lut5_I0_O) 0.297 0.021 r write_back/result0_i_49/O - net (fo=3, routed) 0.843 0.864 execution/result0__0 - SLICE_X58Y35 LUT4 (Prop_lut4_I1_O) 0.124 0.988 r execution/MEM_memory_write_data[31]_i_2/O - net (fo=46, routed) 1.291 2.280 execution/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X44Y41 LUT5 (Prop_lut5_I3_O) 0.124 2.404 r execution/MEM_memory_write_data[11]_i_1/O - net (fo=9, routed) 1.257 3.661 execution/EX_memory_write_data[11] - SLICE_X51Y32 LUT3 (Prop_lut3_I2_O) 0.124 3.785 r execution/result0_i_21/O - net (fo=16, routed) 0.855 4.640 execution/alu/result0__1_0[11] - DSP48_X1Y10 DSP48E1 (Prop_dsp48e1_B[11]_PCOUT[47]) - 3.851 8.491 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.493 execution/alu/result0__0_n_106 - DSP48_X1Y11 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 10.011 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.605 10.615 execution/alu/result0__1_n_105 - SLICE_X55Y26 LUT2 (Prop_lut2_I0_O) 0.124 10.739 r execution/alu/i__carry_i_3__1/O - net (fo=1, routed) 0.000 10.739 execution/alu/i__carry_i_3__1_n_0 - SLICE_X55Y26 CARRY4 (Prop_carry4_S[1]_O[3]) - 0.640 11.379 r execution/alu/result0_inferred__11/i__carry/O[3] - net (fo=1, routed) 0.694 12.073 execution/alu/result0_inferred__11/i__carry_n_4 - SLICE_X59Y26 LUT6 (Prop_lut6_I5_O) 0.306 12.379 r execution/alu/MEM_ALU_result[19]_i_10/O - net (fo=1, routed) 0.304 12.683 execution/alu/MEM_ALU_result[19]_i_10_n_0 - SLICE_X60Y26 LUT6 (Prop_lut6_I5_O) 0.124 12.807 f execution/alu/MEM_ALU_result[19]_i_5/O - net (fo=1, routed) 0.843 13.650 execution/alu/MEM_ALU_result[19]_i_5_n_0 - SLICE_X53Y29 LUT6 (Prop_lut6_I5_O) 0.124 13.774 r execution/alu/MEM_ALU_result[19]_i_1/O - net (fo=1, routed) 0.000 13.774 memory_access/prev_ALU_result[19] - SLICE_X53Y29 FDRE r memory_access/MEM_ALU_result_reg[19]/D + SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q + net (fo=4, routed) 1.044 -0.850 execution/Q[2] + SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O + net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 + SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O + net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 + SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O + net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] + SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O + net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] + DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) + 4.053 7.660 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 + DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.180 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 + SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O + net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 + SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.018 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.018 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 11.352 r execution/alu/result0_inferred__11/i__carry__2/O[1] + net (fo=1, routed) 0.595 11.947 execution/alu/result0_inferred__11/i__carry__2_n_6 + SLICE_X8Y35 LUT6 (Prop_lut6_I5_O) 0.303 12.250 r execution/alu/MEM_ALU_result[29]_i_6/O + net (fo=1, routed) 0.713 12.963 execution/alu/MEM_ALU_result[29]_i_6_n_0 + SLICE_X13Y33 LUT6 (Prop_lut6_I5_O) 0.124 13.087 r execution/alu/MEM_ALU_result[29]_i_3/O + net (fo=1, routed) 0.000 13.087 execution/alu/MEM_ALU_result[29]_i_3_n_0 + SLICE_X13Y33 MUXF7 (Prop_muxf7_I1_O) 0.245 13.332 r execution/alu/MEM_ALU_result_reg[29]_i_1/O + net (fo=1, routed) 0.000 13.332 memory_access/prev_ALU_result[29] + SLICE_X13Y33 FDRE r memory_access/MEM_ALU_result_reg[29]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -683,119 +621,31 @@ Slack (MET) : 3.694ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.441 17.970 memory_access/clk_out1 - SLICE_X53Y29 FDRE r memory_access/MEM_ALU_result_reg[19]/C - clock pessimism -0.425 17.545 - clock uncertainty -0.108 17.437 - SLICE_X53Y29 FDRE (Setup_fdre_C_D) 0.031 17.468 memory_access/MEM_ALU_result_reg[19] + net (fo=18130, routed) 1.443 17.972 memory_access/clk_out1 + SLICE_X13Y33 FDRE r memory_access/MEM_ALU_result_reg[29]/C + clock pessimism -0.497 17.475 + clock uncertainty -0.108 17.367 + SLICE_X13Y33 FDRE (Setup_fdre_C_D) 0.064 17.431 memory_access/MEM_ALU_result_reg[29] ------------------------------------------------------------------- - required time 17.468 - arrival time -13.774 + required time 17.431 + arrival time -13.332 ------------------------------------------------------------------- - slack 3.694 + slack 4.099 -Slack (MET) : 3.790ns (required time - arrival time) - Source: write_back/WB_register_write_reg/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[20]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.019ns (logic 7.900ns (49.316%) route 8.119ns (50.684%)) - Logic Levels: 12 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=3 LUT6=2) - Clock Path Skew: -0.112ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) - Source Clock Delay (SCD): -2.343ns - Clock Pessimism Removal (CPR): -0.425ns - Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.633 -2.343 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X59Y37 FDRE (Prop_fdre_C_Q) 0.419 -1.924 f write_back/WB_register_write_reg/Q - net (fo=16, routed) 1.648 -0.276 write_back/WB_register_write - SLICE_X59Y37 LUT5 (Prop_lut5_I0_O) 0.297 0.021 r write_back/result0_i_49/O - net (fo=3, routed) 0.843 0.864 execution/result0__0 - SLICE_X58Y35 LUT4 (Prop_lut4_I1_O) 0.124 0.988 r execution/MEM_memory_write_data[31]_i_2/O - net (fo=46, routed) 1.291 2.280 execution/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X44Y41 LUT5 (Prop_lut5_I3_O) 0.124 2.404 r execution/MEM_memory_write_data[11]_i_1/O - net (fo=9, routed) 1.257 3.661 execution/EX_memory_write_data[11] - SLICE_X51Y32 LUT3 (Prop_lut3_I2_O) 0.124 3.785 r execution/result0_i_21/O - net (fo=16, routed) 0.855 4.640 execution/alu/result0__1_0[11] - DSP48_X1Y10 DSP48E1 (Prop_dsp48e1_B[11]_PCOUT[47]) - 3.851 8.491 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.493 execution/alu/result0__0_n_106 - DSP48_X1Y11 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 10.011 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.605 10.615 execution/alu/result0__1_n_105 - SLICE_X55Y26 LUT2 (Prop_lut2_I0_O) 0.124 10.739 r execution/alu/i__carry_i_3__1/O - net (fo=1, routed) 0.000 10.739 execution/alu/i__carry_i_3__1_n_0 - SLICE_X55Y26 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 11.289 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.289 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X55Y27 CARRY4 (Prop_carry4_CI_O[0]) - 0.222 11.511 r execution/alu/result0_inferred__11/i__carry__0/O[0] - net (fo=1, routed) 0.671 12.183 execution/alu/result0_inferred__11/i__carry__0_n_7 - SLICE_X58Y27 LUT6 (Prop_lut6_I5_O) 0.299 12.482 r execution/alu/MEM_ALU_result[20]_i_9/O - net (fo=1, routed) 0.161 12.643 execution/alu/MEM_ALU_result[20]_i_9_n_0 - SLICE_X58Y27 LUT5 (Prop_lut5_I4_O) 0.124 12.767 f execution/alu/MEM_ALU_result[20]_i_5/O - net (fo=1, routed) 0.785 13.552 execution/alu/MEM_ALU_result[20]_i_5_n_0 - SLICE_X48Y31 LUT6 (Prop_lut6_I5_O) 0.124 13.676 r execution/alu/MEM_ALU_result[20]_i_1/O - net (fo=1, routed) 0.000 13.676 memory_access/prev_ALU_result[20] - SLICE_X48Y31 FDRE r memory_access/MEM_ALU_result_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 20.000 20.000 r - R4 0.000 20.000 r hardware_clk (IN) - net (fo=0) 0.000 20.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.441 17.970 memory_access/clk_out1 - SLICE_X48Y31 FDRE r memory_access/MEM_ALU_result_reg[20]/C - clock pessimism -0.425 17.545 - clock uncertainty -0.108 17.437 - SLICE_X48Y31 FDRE (Setup_fdre_C_D) 0.029 17.466 memory_access/MEM_ALU_result_reg[20] - ------------------------------------------------------------------- - required time 17.466 - arrival time -13.676 - ------------------------------------------------------------------- - slack 3.790 - -Slack (MET) : 3.916ns (required time - arrival time) - Source: write_back/WB_register_write_reg/C +Slack (MET) : 4.315ns (required time - arrival time) + Source: execution/EX_rt_address_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[27]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.024ns (logic 7.856ns (49.026%) route 8.168ns (50.974%)) - Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=2 LUT6=2) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.963ns = ( 18.037 - 20.000 ) - Source Clock Delay (SCD): -2.343ns - Clock Pessimism Removal (CPR): -0.411ns + Data Path Delay: 15.578ns (logic 8.391ns (53.863%) route 7.187ns (46.137%)) + Logic Levels: 13 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) + Clock Path Skew: -0.112ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.027ns = ( 17.973 - 20.000 ) + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): -0.497ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -813,38 +663,43 @@ Slack (MET) : 3.916ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.633 -2.343 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_reg/C + net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 + SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X59Y37 FDRE (Prop_fdre_C_Q) 0.419 -1.924 f write_back/WB_register_write_reg/Q - net (fo=16, routed) 1.648 -0.276 write_back/WB_register_write - SLICE_X59Y37 LUT5 (Prop_lut5_I0_O) 0.297 0.021 r write_back/result0_i_49/O - net (fo=3, routed) 0.843 0.864 execution/result0__0 - SLICE_X58Y35 LUT4 (Prop_lut4_I1_O) 0.124 0.988 r execution/MEM_memory_write_data[31]_i_2/O - net (fo=46, routed) 1.291 2.280 execution/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X44Y41 LUT5 (Prop_lut5_I3_O) 0.124 2.404 r execution/MEM_memory_write_data[11]_i_1/O - net (fo=9, routed) 1.257 3.661 execution/EX_memory_write_data[11] - SLICE_X51Y32 LUT3 (Prop_lut3_I2_O) 0.124 3.785 r execution/result0_i_21/O - net (fo=16, routed) 0.855 4.640 execution/alu/result0__1_0[11] - DSP48_X1Y10 DSP48E1 (Prop_dsp48e1_B[11]_PCOUT[47]) - 3.851 8.491 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.493 execution/alu/result0__0_n_106 - DSP48_X1Y11 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[3]) - 1.518 10.011 r execution/alu/result0__1/P[3] - net (fo=2, routed) 0.982 10.993 execution/alu/result0__1_n_102 - SLICE_X55Y27 LUT2 (Prop_lut2_I0_O) 0.124 11.117 r execution/alu/i__carry__0_i_4__1/O - net (fo=1, routed) 0.000 11.117 execution/alu/i__carry__0_i_4__1_n_0 - SLICE_X55Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 11.649 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.649 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X55Y28 CARRY4 (Prop_carry4_CI_O[3]) - 0.313 11.962 r execution/alu/result0_inferred__11/i__carry__1/O[3] - net (fo=1, routed) 0.556 12.518 execution/alu/result0_inferred__11/i__carry__1_n_4 - SLICE_X60Y28 LUT6 (Prop_lut6_I5_O) 0.306 12.824 r execution/alu/MEM_ALU_result[27]_i_4/O - net (fo=1, routed) 0.733 13.557 execution/alu/MEM_ALU_result[27]_i_4_n_0 - SLICE_X60Y31 LUT6 (Prop_lut6_I2_O) 0.124 13.681 r execution/alu/MEM_ALU_result[27]_i_1/O - net (fo=1, routed) 0.000 13.681 memory_access/prev_ALU_result[27] - SLICE_X60Y31 FDRE r memory_access/MEM_ALU_result_reg[27]/D + SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q + net (fo=4, routed) 1.044 -0.850 execution/Q[2] + SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O + net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 + SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O + net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 + SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O + net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] + SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O + net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] + DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) + 4.053 7.660 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 + DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.180 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 + SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O + net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 + SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 11.217 r execution/alu/result0_inferred__11/i__carry__1/O[3] + net (fo=1, routed) 0.673 11.890 execution/alu/result0_inferred__11/i__carry__1_n_4 + SLICE_X8Y35 LUT6 (Prop_lut6_I5_O) 0.306 12.196 r execution/alu/MEM_ALU_result[27]_i_6/O + net (fo=1, routed) 0.599 12.795 execution/alu/MEM_ALU_result[27]_i_6_n_0 + SLICE_X14Y34 LUT6 (Prop_lut6_I5_O) 0.124 12.919 r execution/alu/MEM_ALU_result[27]_i_3/O + net (fo=1, routed) 0.000 12.919 execution/alu/MEM_ALU_result[27]_i_3_n_0 + SLICE_X14Y34 MUXF7 (Prop_muxf7_I1_O) 0.247 13.166 r execution/alu/MEM_ALU_result_reg[27]_i_1/O + net (fo=1, routed) 0.000 13.166 memory_access/prev_ALU_result[27] + SLICE_X14Y34 FDRE r memory_access/MEM_ALU_result_reg[27]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -857,31 +712,31 @@ Slack (MET) : 3.916ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.508 18.037 memory_access/clk_out1 - SLICE_X60Y31 FDRE r memory_access/MEM_ALU_result_reg[27]/C - clock pessimism -0.411 17.626 - clock uncertainty -0.108 17.518 - SLICE_X60Y31 FDRE (Setup_fdre_C_D) 0.079 17.597 memory_access/MEM_ALU_result_reg[27] + net (fo=18130, routed) 1.444 17.973 memory_access/clk_out1 + SLICE_X14Y34 FDRE r memory_access/MEM_ALU_result_reg[27]/C + clock pessimism -0.497 17.476 + clock uncertainty -0.108 17.368 + SLICE_X14Y34 FDRE (Setup_fdre_C_D) 0.113 17.481 memory_access/MEM_ALU_result_reg[27] ------------------------------------------------------------------- - required time 17.597 - arrival time -13.681 + required time 17.481 + arrival time -13.166 ------------------------------------------------------------------- - slack 3.916 + slack 4.315 -Slack (MET) : 3.939ns (required time - arrival time) - Source: write_back/WB_register_write_reg/C +Slack (MET) : 4.357ns (required time - arrival time) + Source: execution/EX_rt_address_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[28]/D + Destination: memory_access/MEM_ALU_result_reg[25]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.001ns (logic 7.872ns (49.196%) route 8.129ns (50.804%)) - Logic Levels: 12 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=2 LUT6=2) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.963ns = ( 18.037 - 20.000 ) - Source Clock Delay (SCD): -2.343ns - Clock Pessimism Removal (CPR): -0.411ns + Data Path Delay: 15.537ns (logic 8.376ns (53.910%) route 7.161ns (46.090%)) + Logic Levels: 13 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) + Clock Path Skew: -0.111ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.026ns = ( 17.974 - 20.000 ) + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): -0.497ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -899,41 +754,43 @@ Slack (MET) : 3.939ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.633 -2.343 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_reg/C + net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 + SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X59Y37 FDRE (Prop_fdre_C_Q) 0.419 -1.924 f write_back/WB_register_write_reg/Q - net (fo=16, routed) 1.648 -0.276 write_back/WB_register_write - SLICE_X59Y37 LUT5 (Prop_lut5_I0_O) 0.297 0.021 r write_back/result0_i_49/O - net (fo=3, routed) 0.843 0.864 execution/result0__0 - SLICE_X58Y35 LUT4 (Prop_lut4_I1_O) 0.124 0.988 r execution/MEM_memory_write_data[31]_i_2/O - net (fo=46, routed) 1.291 2.280 execution/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X44Y41 LUT5 (Prop_lut5_I3_O) 0.124 2.404 r execution/MEM_memory_write_data[11]_i_1/O - net (fo=9, routed) 1.257 3.661 execution/EX_memory_write_data[11] - SLICE_X51Y32 LUT3 (Prop_lut3_I2_O) 0.124 3.785 r execution/result0_i_21/O - net (fo=16, routed) 0.855 4.640 execution/alu/result0__1_0[11] - DSP48_X1Y10 DSP48E1 (Prop_dsp48e1_B[11]_PCOUT[47]) - 3.851 8.491 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.493 execution/alu/result0__0_n_106 - DSP48_X1Y11 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[3]) - 1.518 10.011 r execution/alu/result0__1/P[3] - net (fo=2, routed) 0.982 10.993 execution/alu/result0__1_n_102 - SLICE_X55Y27 LUT2 (Prop_lut2_I0_O) 0.124 11.117 r execution/alu/i__carry__0_i_4__1/O - net (fo=1, routed) 0.000 11.117 execution/alu/i__carry__0_i_4__1_n_0 - SLICE_X55Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 11.649 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.649 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X55Y28 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.763 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.763 execution/alu/result0_inferred__11/i__carry__1_n_0 - SLICE_X55Y29 CARRY4 (Prop_carry4_CI_O[0]) - 0.222 11.985 r execution/alu/result0_inferred__11/i__carry__2/O[0] - net (fo=1, routed) 0.795 12.781 execution/alu/result0_inferred__11/i__carry__2_n_7 - SLICE_X60Y29 LUT6 (Prop_lut6_I4_O) 0.299 13.080 f execution/alu/MEM_ALU_result[28]_i_3/O - net (fo=1, routed) 0.455 13.534 execution/alu/MEM_ALU_result[28]_i_3_n_0 - SLICE_X60Y31 LUT6 (Prop_lut6_I1_O) 0.124 13.658 r execution/alu/MEM_ALU_result[28]_i_1/O - net (fo=1, routed) 0.000 13.658 memory_access/prev_ALU_result[28] - SLICE_X60Y31 FDRE r memory_access/MEM_ALU_result_reg[28]/D + SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q + net (fo=4, routed) 1.044 -0.850 execution/Q[2] + SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O + net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 + SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O + net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 + SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O + net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] + SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O + net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] + DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) + 4.053 7.660 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 + DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.180 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 + SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O + net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 + SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 11.238 r execution/alu/result0_inferred__11/i__carry__1/O[1] + net (fo=1, routed) 0.665 11.903 execution/alu/result0_inferred__11/i__carry__1_n_6 + SLICE_X9Y35 LUT6 (Prop_lut6_I5_O) 0.303 12.206 r execution/alu/MEM_ALU_result[25]_i_6/O + net (fo=1, routed) 0.581 12.787 execution/alu/MEM_ALU_result[25]_i_6_n_0 + SLICE_X12Y35 LUT6 (Prop_lut6_I5_O) 0.124 12.911 r execution/alu/MEM_ALU_result[25]_i_3/O + net (fo=1, routed) 0.000 12.911 execution/alu/MEM_ALU_result[25]_i_3_n_0 + SLICE_X12Y35 MUXF7 (Prop_muxf7_I1_O) 0.214 13.125 r execution/alu/MEM_ALU_result_reg[25]_i_1/O + net (fo=1, routed) 0.000 13.125 memory_access/prev_ALU_result[25] + SLICE_X12Y35 FDRE r memory_access/MEM_ALU_result_reg[25]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -946,31 +803,31 @@ Slack (MET) : 3.939ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.508 18.037 memory_access/clk_out1 - SLICE_X60Y31 FDRE r memory_access/MEM_ALU_result_reg[28]/C - clock pessimism -0.411 17.626 - clock uncertainty -0.108 17.518 - SLICE_X60Y31 FDRE (Setup_fdre_C_D) 0.079 17.597 memory_access/MEM_ALU_result_reg[28] + net (fo=18130, routed) 1.445 17.974 memory_access/clk_out1 + SLICE_X12Y35 FDRE r memory_access/MEM_ALU_result_reg[25]/C + clock pessimism -0.497 17.477 + clock uncertainty -0.108 17.369 + SLICE_X12Y35 FDRE (Setup_fdre_C_D) 0.113 17.482 memory_access/MEM_ALU_result_reg[25] ------------------------------------------------------------------- - required time 17.597 - arrival time -13.658 + required time 17.482 + arrival time -13.125 ------------------------------------------------------------------- - slack 3.939 + slack 4.357 -Slack (MET) : 3.981ns (required time - arrival time) - Source: write_back/WB_register_write_reg/C +Slack (MET) : 4.410ns (required time - arrival time) + Source: execution/EX_rt_address_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[3]_rep__6/D + Destination: memory_access/MEM_ALU_result_reg[19]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 15.669ns (logic 4.992ns (31.859%) route 10.677ns (68.141%)) - Logic Levels: 7 (DSP48E1=1 LUT3=1 LUT4=1 LUT5=2 LUT6=2) - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.037ns = ( 17.963 - 20.000 ) - Source Clock Delay (SCD): -2.343ns - Clock Pessimism Removal (CPR): -0.505ns + Data Path Delay: 15.497ns (logic 8.024ns (51.779%) route 7.473ns (48.221%)) + Logic Levels: 11 (CARRY4=1 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) + Clock Path Skew: -0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.965ns = ( 18.035 - 20.000 ) + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): -0.497ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -988,27 +845,37 @@ Slack (MET) : 3.981ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.633 -2.343 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_reg/C + net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 + SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X59Y37 FDRE (Prop_fdre_C_Q) 0.419 -1.924 f write_back/WB_register_write_reg/Q - net (fo=16, routed) 1.648 -0.276 write_back/WB_register_write - SLICE_X59Y37 LUT5 (Prop_lut5_I0_O) 0.297 0.021 r write_back/result0_i_49/O - net (fo=3, routed) 0.843 0.864 execution/result0__0 - SLICE_X58Y35 LUT4 (Prop_lut4_I1_O) 0.124 0.988 r execution/MEM_memory_write_data[31]_i_2/O - net (fo=46, routed) 1.291 2.280 execution/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X44Y41 LUT5 (Prop_lut5_I3_O) 0.124 2.404 r execution/MEM_memory_write_data[11]_i_1/O - net (fo=9, routed) 1.257 3.661 execution/EX_memory_write_data[11] - SLICE_X51Y32 LUT3 (Prop_lut3_I2_O) 0.124 3.785 r execution/result0_i_21/O - net (fo=16, routed) 0.855 4.640 execution/alu/result0__1_0[11] - DSP48_X1Y10 DSP48E1 (Prop_dsp48e1_B[11]_P[3]) - 3.656 8.296 r execution/alu/result0__0/P[3] - net (fo=1, routed) 1.145 9.441 execution/alu/result0__0_n_102 - SLICE_X47Y26 LUT6 (Prop_lut6_I5_O) 0.124 9.565 r execution/alu/MEM_ALU_result[3]_i_5/O - net (fo=34, routed) 3.163 12.729 execution/alu/MEM_ALU_result[3]_i_5_n_0 - SLICE_X29Y90 LUT6 (Prop_lut6_I5_O) 0.124 12.853 r execution/alu/MEM_ALU_result[3]_rep_i_1__6/O - net (fo=1, routed) 0.474 13.326 memory_access/MEM_ALU_result_reg[3]_rep__6_1 - SLICE_X29Y89 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__6/D + SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q + net (fo=4, routed) 1.044 -0.850 execution/Q[2] + SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O + net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 + SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O + net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 + SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O + net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] + SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O + net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] + DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) + 4.053 7.660 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 + DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.180 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 + SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O + net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 + SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_O[3]) + 0.640 10.880 r execution/alu/result0_inferred__11/i__carry/O[3] + net (fo=1, routed) 0.973 11.853 execution/alu/result0_inferred__11/i__carry_n_4 + SLICE_X4Y34 LUT6 (Prop_lut6_I5_O) 0.306 12.159 r execution/alu/MEM_ALU_result[19]_i_6/O + net (fo=1, routed) 0.585 12.744 execution/alu/MEM_ALU_result[19]_i_6_n_0 + SLICE_X7Y30 LUT6 (Prop_lut6_I5_O) 0.124 12.868 r execution/alu/MEM_ALU_result[19]_i_3/O + net (fo=1, routed) 0.000 12.868 execution/alu/MEM_ALU_result[19]_i_3_n_0 + SLICE_X7Y30 MUXF7 (Prop_muxf7_I1_O) 0.217 13.085 r execution/alu/MEM_ALU_result_reg[19]_i_1/O + net (fo=1, routed) 0.000 13.085 memory_access/prev_ALU_result[19] + SLICE_X7Y30 FDRE r memory_access/MEM_ALU_result_reg[19]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1021,31 +888,31 @@ Slack (MET) : 3.981ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.435 17.963 memory_access/clk_out1 - SLICE_X29Y89 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__6/C - clock pessimism -0.505 17.458 - clock uncertainty -0.108 17.351 - SLICE_X29Y89 FDRE (Setup_fdre_C_D) -0.043 17.308 memory_access/MEM_ALU_result_reg[3]_rep__6 + net (fo=18130, routed) 1.506 18.035 memory_access/clk_out1 + SLICE_X7Y30 FDRE r memory_access/MEM_ALU_result_reg[19]/C + clock pessimism -0.497 17.538 + clock uncertainty -0.108 17.430 + SLICE_X7Y30 FDRE (Setup_fdre_C_D) 0.064 17.494 memory_access/MEM_ALU_result_reg[19] ------------------------------------------------------------------- - required time 17.308 - arrival time -13.326 + required time 17.494 + arrival time -13.085 ------------------------------------------------------------------- - slack 3.981 + slack 4.410 -Slack (MET) : 4.056ns (required time - arrival time) - Source: write_back/WB_register_write_reg/C +Slack (MET) : 4.445ns (required time - arrival time) + Source: execution/EX_rt_address_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[3]_rep__1/D + Destination: memory_access/MEM_ALU_result_reg[31]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 15.531ns (logic 4.992ns (32.143%) route 10.539ns (67.857%)) - Logic Levels: 7 (DSP48E1=1 LUT3=1 LUT4=1 LUT5=2 LUT6=2) - Clock Path Skew: -0.201ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.039ns = ( 17.961 - 20.000 ) - Source Clock Delay (SCD): -2.343ns - Clock Pessimism Removal (CPR): -0.505ns + Data Path Delay: 15.401ns (logic 8.475ns (55.030%) route 6.926ns (44.970%)) + Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) + Clock Path Skew: -0.111ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.026ns = ( 17.974 - 20.000 ) + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): -0.497ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -1063,27 +930,46 @@ Slack (MET) : 4.056ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.633 -2.343 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_reg/C + net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 + SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X59Y37 FDRE (Prop_fdre_C_Q) 0.419 -1.924 f write_back/WB_register_write_reg/Q - net (fo=16, routed) 1.648 -0.276 write_back/WB_register_write - SLICE_X59Y37 LUT5 (Prop_lut5_I0_O) 0.297 0.021 r write_back/result0_i_49/O - net (fo=3, routed) 0.843 0.864 execution/result0__0 - SLICE_X58Y35 LUT4 (Prop_lut4_I1_O) 0.124 0.988 r execution/MEM_memory_write_data[31]_i_2/O - net (fo=46, routed) 1.291 2.280 execution/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X44Y41 LUT5 (Prop_lut5_I3_O) 0.124 2.404 r execution/MEM_memory_write_data[11]_i_1/O - net (fo=9, routed) 1.257 3.661 execution/EX_memory_write_data[11] - SLICE_X51Y32 LUT3 (Prop_lut3_I2_O) 0.124 3.785 r execution/result0_i_21/O - net (fo=16, routed) 0.855 4.640 execution/alu/result0__1_0[11] - DSP48_X1Y10 DSP48E1 (Prop_dsp48e1_B[11]_P[3]) - 3.656 8.296 r execution/alu/result0__0/P[3] - net (fo=1, routed) 1.145 9.441 execution/alu/result0__0_n_102 - SLICE_X47Y26 LUT6 (Prop_lut6_I5_O) 0.124 9.565 r execution/alu/MEM_ALU_result[3]_i_5/O - net (fo=34, routed) 2.840 12.405 execution/alu/MEM_ALU_result[3]_i_5_n_0 - SLICE_X37Y89 LUT6 (Prop_lut6_I5_O) 0.124 12.529 r execution/alu/MEM_ALU_result[3]_rep_i_1__1/O - net (fo=1, routed) 0.659 13.188 memory_access/MEM_ALU_result_reg[3]_rep__1_1 - SLICE_X36Y89 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__1/D + SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q + net (fo=4, routed) 1.044 -0.850 execution/Q[2] + SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O + net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 + SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O + net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 + SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O + net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] + SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O + net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] + DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) + 4.053 7.660 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 + DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.180 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 + SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O + net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 + SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.018 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.018 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 11.331 r execution/alu/result0_inferred__11/i__carry__2/O[3] + net (fo=1, routed) 0.608 11.939 execution/alu/result0_inferred__11/i__carry__2_n_4 + SLICE_X15Y36 LUT6 (Prop_lut6_I5_O) 0.306 12.245 r execution/alu/MEM_ALU_result[31]_i_8/O + net (fo=1, routed) 0.403 12.648 execution/alu/MEM_ALU_result[31]_i_8_n_0 + SLICE_X15Y36 LUT6 (Prop_lut6_I5_O) 0.124 12.772 r execution/alu/MEM_ALU_result[31]_i_4/O + net (fo=1, routed) 0.000 12.772 execution/alu/MEM_ALU_result[31]_i_4_n_0 + SLICE_X15Y36 MUXF7 (Prop_muxf7_I1_O) 0.217 12.989 r execution/alu/MEM_ALU_result_reg[31]_i_1/O + net (fo=1, routed) 0.000 12.989 memory_access/prev_ALU_result[31] + SLICE_X15Y36 FDRE r memory_access/MEM_ALU_result_reg[31]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1096,16 +982,192 @@ Slack (MET) : 4.056ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.433 17.961 memory_access/clk_out1 - SLICE_X36Y89 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__1/C - clock pessimism -0.505 17.456 - clock uncertainty -0.108 17.349 - SLICE_X36Y89 FDRE (Setup_fdre_C_D) -0.105 17.244 memory_access/MEM_ALU_result_reg[3]_rep__1 + net (fo=18130, routed) 1.445 17.974 memory_access/clk_out1 + SLICE_X15Y36 FDRE r memory_access/MEM_ALU_result_reg[31]/C + clock pessimism -0.497 17.477 + clock uncertainty -0.108 17.369 + SLICE_X15Y36 FDRE (Setup_fdre_C_D) 0.064 17.433 memory_access/MEM_ALU_result_reg[31] ------------------------------------------------------------------- - required time 17.244 - arrival time -13.188 + required time 17.433 + arrival time -12.989 ------------------------------------------------------------------- - slack 4.056 + slack 4.445 + +Slack (MET) : 4.467ns (required time - arrival time) + Source: execution/EX_rt_address_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: memory_access/MEM_ALU_result_reg[22]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 15.375ns (logic 8.197ns (53.313%) route 7.178ns (46.687%)) + Logic Levels: 12 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) + Clock Path Skew: -0.114ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.029ns = ( 17.971 - 20.000 ) + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): -0.497ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 + SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q + net (fo=4, routed) 1.044 -0.850 execution/Q[2] + SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O + net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 + SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O + net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 + SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O + net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] + SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O + net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] + DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) + 4.053 7.660 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 + DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.180 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 + SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O + net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 + SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y34 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 11.029 r execution/alu/result0_inferred__11/i__carry__0/O[2] + net (fo=1, routed) 0.555 11.584 execution/alu/result0_inferred__11/i__carry__0_n_5 + SLICE_X9Y35 LUT6 (Prop_lut6_I5_O) 0.302 11.886 r execution/alu/MEM_ALU_result[22]_i_6/O + net (fo=1, routed) 0.708 12.594 execution/alu/MEM_ALU_result[22]_i_6_n_0 + SLICE_X13Y32 LUT6 (Prop_lut6_I5_O) 0.124 12.718 r execution/alu/MEM_ALU_result[22]_i_3/O + net (fo=1, routed) 0.000 12.718 execution/alu/MEM_ALU_result[22]_i_3_n_0 + SLICE_X13Y32 MUXF7 (Prop_muxf7_I1_O) 0.245 12.963 r execution/alu/MEM_ALU_result_reg[22]_i_1/O + net (fo=1, routed) 0.000 12.963 memory_access/prev_ALU_result[22] + SLICE_X13Y32 FDRE r memory_access/MEM_ALU_result_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 20.000 20.000 r + R4 0.000 20.000 r hardware_clk (IN) + net (fo=0) 0.000 20.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.442 17.971 memory_access/clk_out1 + SLICE_X13Y32 FDRE r memory_access/MEM_ALU_result_reg[22]/C + clock pessimism -0.497 17.474 + clock uncertainty -0.108 17.366 + SLICE_X13Y32 FDRE (Setup_fdre_C_D) 0.064 17.430 memory_access/MEM_ALU_result_reg[22] + ------------------------------------------------------------------- + required time 17.430 + arrival time -12.963 + ------------------------------------------------------------------- + slack 4.467 + +Slack (MET) : 4.471ns (required time - arrival time) + Source: execution/EX_rt_address_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: memory_access/MEM_ALU_result_reg[21]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 15.371ns (logic 8.265ns (53.769%) route 7.106ns (46.231%)) + Logic Levels: 12 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) + Clock Path Skew: -0.114ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.029ns = ( 17.971 - 20.000 ) + Source Clock Delay (SCD): -2.412ns + Clock Pessimism Removal (CPR): -0.497ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 + SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q + net (fo=4, routed) 1.044 -0.850 execution/Q[2] + SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O + net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 + SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O + net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 + SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O + net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] + SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O + net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] + DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) + 4.053 7.660 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 + DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.180 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 + SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O + net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 + SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y34 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 11.124 r execution/alu/result0_inferred__11/i__carry__0/O[1] + net (fo=1, routed) 0.589 11.714 execution/alu/result0_inferred__11/i__carry__0_n_6 + SLICE_X8Y34 LUT6 (Prop_lut6_I5_O) 0.303 12.017 r execution/alu/MEM_ALU_result[21]_i_6/O + net (fo=1, routed) 0.602 12.618 execution/alu/MEM_ALU_result[21]_i_6_n_0 + SLICE_X13Y32 LUT6 (Prop_lut6_I5_O) 0.124 12.742 r execution/alu/MEM_ALU_result[21]_i_3/O + net (fo=1, routed) 0.000 12.742 execution/alu/MEM_ALU_result[21]_i_3_n_0 + SLICE_X13Y32 MUXF7 (Prop_muxf7_I1_O) 0.217 12.959 r execution/alu/MEM_ALU_result_reg[21]_i_1/O + net (fo=1, routed) 0.000 12.959 memory_access/prev_ALU_result[21] + SLICE_X13Y32 FDRE r memory_access/MEM_ALU_result_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 20.000 20.000 r + R4 0.000 20.000 r hardware_clk (IN) + net (fo=0) 0.000 20.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.442 17.971 memory_access/clk_out1 + SLICE_X13Y32 FDRE r memory_access/MEM_ALU_result_reg[21]/C + clock pessimism -0.497 17.474 + clock uncertainty -0.108 17.366 + SLICE_X13Y32 FDRE (Setup_fdre_C_D) 0.064 17.430 memory_access/MEM_ALU_result_reg[21] + ------------------------------------------------------------------- + required time 17.430 + arrival time -12.959 + ------------------------------------------------------------------- + slack 4.471 @@ -1113,349 +1175,19 @@ Slack (MET) : 4.056ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.045ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[16]_rep__2/C +Slack (MET) : 0.055ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[15]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435675][16]/D + Destination: data_memory/memory_data_reg[268435959][15]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.371ns (logic 0.141ns (37.998%) route 0.230ns (62.002%)) + Data Path Delay: 0.388ns (logic 0.141ns (36.319%) route 0.247ns (63.681%)) Logic Levels: 0 Clock Path Skew: 0.263ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.297ns - Source Clock Delay (SCD): -0.526ns - Clock Pessimism Removal (CPR): -0.034ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.561 -0.526 memory_access/clk_out1 - SLICE_X37Y10 FDRE r memory_access/MEM_memory_write_data_reg[16]_rep__2/C - ------------------------------------------------------------------- ------------------- - SLICE_X37Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.385 r memory_access/MEM_memory_write_data_reg[16]_rep__2/Q - net (fo=64, routed) 0.230 -0.155 data_memory/memory_data_reg[268435649][31]_0[16] - SLICE_X34Y10 FDRE r data_memory/memory_data_reg[268435675][16]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.829 -0.297 data_memory/clk_out1 - SLICE_X34Y10 FDRE r data_memory/memory_data_reg[268435675][16]/C - clock pessimism 0.034 -0.263 - SLICE_X34Y10 FDRE (Hold_fdre_C_D) 0.063 -0.200 data_memory/memory_data_reg[268435675][16] - ------------------------------------------------------------------- - required time 0.200 - arrival time -0.155 - ------------------------------------------------------------------- - slack 0.045 - -Slack (MET) : 0.050ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[14]_rep__3/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435586][14]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.385ns (logic 0.141ns (36.659%) route 0.244ns (63.341%)) - Logic Levels: 0 - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.297ns - Source Clock Delay (SCD): -0.528ns - Clock Pessimism Removal (CPR): -0.034ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.559 -0.528 memory_access/clk_out1 - SLICE_X37Y36 FDRE r memory_access/MEM_memory_write_data_reg[14]_rep__3/C - ------------------------------------------------------------------- ------------------- - SLICE_X37Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.387 r memory_access/MEM_memory_write_data_reg[14]_rep__3/Q - net (fo=64, routed) 0.244 -0.144 data_memory/memory_data_reg[268435585][31]_0[14] - SLICE_X35Y38 FDRE r data_memory/memory_data_reg[268435586][14]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.829 -0.297 data_memory/clk_out1 - SLICE_X35Y38 FDRE r data_memory/memory_data_reg[268435586][14]/C - clock pessimism 0.034 -0.263 - SLICE_X35Y38 FDRE (Hold_fdre_C_D) 0.070 -0.193 data_memory/memory_data_reg[268435586][14] - ------------------------------------------------------------------- - required time 0.193 - arrival time -0.144 - ------------------------------------------------------------------- - slack 0.050 - -Slack (MET) : 0.064ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[14]_rep__2/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435669][14]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.401ns (logic 0.141ns (35.133%) route 0.260ns (64.867%)) - Logic Levels: 0 - Clock Path Skew: 0.267ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.295ns - Source Clock Delay (SCD): -0.528ns - Clock Pessimism Removal (CPR): -0.034ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.559 -0.528 memory_access/clk_out1 - SLICE_X37Y36 FDRE r memory_access/MEM_memory_write_data_reg[14]_rep__2/C - ------------------------------------------------------------------- ------------------- - SLICE_X37Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.387 r memory_access/MEM_memory_write_data_reg[14]_rep__2/Q - net (fo=64, routed) 0.260 -0.127 data_memory/memory_data_reg[268435649][31]_0[14] - SLICE_X29Y39 FDRE r data_memory/memory_data_reg[268435669][14]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.831 -0.295 data_memory/clk_out1 - SLICE_X29Y39 FDRE r data_memory/memory_data_reg[268435669][14]/C - clock pessimism 0.034 -0.261 - SLICE_X29Y39 FDRE (Hold_fdre_C_D) 0.070 -0.191 data_memory/memory_data_reg[268435669][14] - ------------------------------------------------------------------- - required time 0.191 - arrival time -0.127 - ------------------------------------------------------------------- - slack 0.064 - -Slack (MET) : 0.068ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[28]_rep__3/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435616][28]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.345ns (logic 0.128ns (37.133%) route 0.217ns (62.867%)) - Logic Levels: 0 - Clock Path Skew: 0.258ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.534ns - Clock Pessimism Removal (CPR): -0.034ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.553 -0.534 memory_access/clk_out1 - SLICE_X39Y27 FDRE r memory_access/MEM_memory_write_data_reg[28]_rep__3/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y27 FDRE (Prop_fdre_C_Q) 0.128 -0.406 r memory_access/MEM_memory_write_data_reg[28]_rep__3/Q - net (fo=64, routed) 0.217 -0.190 data_memory/memory_data_reg[268435585][31]_0[28] - SLICE_X35Y26 FDRE r data_memory/memory_data_reg[268435616][28]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.816 -0.310 data_memory/clk_out1 - SLICE_X35Y26 FDRE r data_memory/memory_data_reg[268435616][28]/C - clock pessimism 0.034 -0.276 - SLICE_X35Y26 FDRE (Hold_fdre_C_D) 0.019 -0.257 data_memory/memory_data_reg[268435616][28] - ------------------------------------------------------------------- - required time 0.257 - arrival time -0.190 - ------------------------------------------------------------------- - slack 0.068 - -Slack (MET) : 0.088ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[27]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435959][27]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.290ns (logic 0.128ns (44.169%) route 0.162ns (55.831%)) - Logic Levels: 0 - Clock Path Skew: 0.184ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.290ns - Source Clock Delay (SCD): -0.441ns - Clock Pessimism Removal (CPR): -0.034ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.646 -0.441 memory_access/clk_out1 - SLICE_X53Y100 FDRE r memory_access/MEM_memory_write_data_reg[27]/C - ------------------------------------------------------------------- ------------------- - SLICE_X53Y100 FDRE (Prop_fdre_C_Q) 0.128 -0.313 r memory_access/MEM_memory_write_data_reg[27]/Q - net (fo=64, routed) 0.162 -0.151 data_memory/memory_data_reg[268435905][31]_0[27] - SLICE_X51Y99 FDRE r data_memory/memory_data_reg[268435959][27]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.835 -0.290 data_memory/clk_out1 - SLICE_X51Y99 FDRE r data_memory/memory_data_reg[268435959][27]/C - clock pessimism 0.034 -0.256 - SLICE_X51Y99 FDRE (Hold_fdre_C_D) 0.017 -0.239 data_memory/memory_data_reg[268435959][27] - ------------------------------------------------------------------- - required time 0.239 - arrival time -0.151 - ------------------------------------------------------------------- - slack 0.088 - -Slack (MET) : 0.092ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[9]_rep__4/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435551][9]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.425ns (logic 0.164ns (38.562%) route 0.261ns (61.438%)) - Logic Levels: 0 - Clock Path Skew: 0.267ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.296ns - Source Clock Delay (SCD): -0.524ns - Clock Pessimism Removal (CPR): -0.039ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.563 -0.524 memory_access/clk_out1 - SLICE_X34Y49 FDRE r memory_access/MEM_memory_write_data_reg[9]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X34Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.360 r memory_access/MEM_memory_write_data_reg[9]_rep__4/Q - net (fo=64, routed) 0.261 -0.099 data_memory/memory_data_reg[268435521][31]_0[9] - SLICE_X37Y56 FDRE r data_memory/memory_data_reg[268435551][9]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.829 -0.296 data_memory/clk_out1 - SLICE_X37Y56 FDRE r data_memory/memory_data_reg[268435551][9]/C - clock pessimism 0.039 -0.257 - SLICE_X37Y56 FDRE (Hold_fdre_C_D) 0.066 -0.191 data_memory/memory_data_reg[268435551][9] - ------------------------------------------------------------------- - required time 0.191 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.092 - -Slack (MET) : 0.095ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[4]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435916][4]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.372ns (logic 0.128ns (34.454%) route 0.244ns (65.546%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.209ns - Source Clock Delay (SCD): -0.443ns + Destination Clock Delay (DCD): -0.215ns + Source Clock Delay (SCD): -0.448ns Clock Pessimism Removal (CPR): -0.030ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1470,12 +1202,12 @@ Slack (MET) : 0.095ns (arrival time - required time) -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.644 -0.443 memory_access/clk_out1 - SLICE_X32Y101 FDRE r memory_access/MEM_memory_write_data_reg[4]/C + net (fo=18130, routed) 0.639 -0.448 memory_access/clk_out1 + SLICE_X35Y112 FDRE r memory_access/MEM_memory_write_data_reg[15]/C ------------------------------------------------------------------- ------------------- - SLICE_X32Y101 FDRE (Prop_fdre_C_Q) 0.128 -0.315 r memory_access/MEM_memory_write_data_reg[4]/Q - net (fo=64, routed) 0.244 -0.071 data_memory/memory_data_reg[268435905][31]_0[4] - SLICE_X37Y101 FDRE r data_memory/memory_data_reg[268435916][4]/D + SLICE_X35Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.307 r memory_access/MEM_memory_write_data_reg[15]/Q + net (fo=64, routed) 0.247 -0.059 data_memory/memory_data_reg[268435905][31]_0[15] + SLICE_X39Y114 FDRE r data_memory/memory_data_reg[268435959][15]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1488,30 +1220,30 @@ Slack (MET) : 0.095ns (arrival time - required time) -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.917 -0.209 data_memory/clk_out1 - SLICE_X37Y101 FDRE r data_memory/memory_data_reg[268435916][4]/C - clock pessimism 0.030 -0.179 - SLICE_X37Y101 FDRE (Hold_fdre_C_D) 0.013 -0.166 data_memory/memory_data_reg[268435916][4] + net (fo=18130, routed) 0.911 -0.215 data_memory/clk_out1 + SLICE_X39Y114 FDRE r data_memory/memory_data_reg[268435959][15]/C + clock pessimism 0.030 -0.185 + SLICE_X39Y114 FDRE (Hold_fdre_C_D) 0.070 -0.115 data_memory/memory_data_reg[268435959][15] ------------------------------------------------------------------- - required time 0.166 - arrival time -0.071 + required time 0.115 + arrival time -0.059 ------------------------------------------------------------------- - slack 0.095 + slack 0.055 -Slack (MET) : 0.106ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[15]_rep/C +Slack (MET) : 0.063ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[15]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435884][15]/D + Destination: data_memory/memory_data_reg[268435932][15]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.360ns (logic 0.141ns (39.148%) route 0.219ns (60.852%)) + Data Path Delay: 0.398ns (logic 0.141ns (35.387%) route 0.257ns (64.613%)) Logic Levels: 0 - Clock Path Skew: 0.184ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.290ns - Source Clock Delay (SCD): -0.441ns - Clock Pessimism Removal (CPR): -0.034ns + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.212ns + Source Clock Delay (SCD): -0.448ns + Clock Pessimism Removal (CPR): -0.030ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1525,12 +1257,12 @@ Slack (MET) : 0.106ns (arrival time - required time) -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.646 -0.441 memory_access/clk_out1 - SLICE_X53Y100 FDRE r memory_access/MEM_memory_write_data_reg[15]_rep/C + net (fo=18130, routed) 0.639 -0.448 memory_access/clk_out1 + SLICE_X35Y112 FDRE r memory_access/MEM_memory_write_data_reg[15]/C ------------------------------------------------------------------- ------------------- - SLICE_X53Y100 FDRE (Prop_fdre_C_Q) 0.141 -0.300 r memory_access/MEM_memory_write_data_reg[15]_rep/Q - net (fo=64, routed) 0.219 -0.081 data_memory/memory_data_reg[268435841][31]_0[15] - SLICE_X53Y99 FDRE r data_memory/memory_data_reg[268435884][15]/D + SLICE_X35Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.307 r memory_access/MEM_memory_write_data_reg[15]/Q + net (fo=64, routed) 0.257 -0.049 data_memory/memory_data_reg[268435905][31]_0[15] + SLICE_X39Y110 FDRE r data_memory/memory_data_reg[268435932][15]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1543,30 +1275,195 @@ Slack (MET) : 0.106ns (arrival time - required time) -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.835 -0.290 data_memory/clk_out1 - SLICE_X53Y99 FDRE r data_memory/memory_data_reg[268435884][15]/C - clock pessimism 0.034 -0.256 - SLICE_X53Y99 FDRE (Hold_fdre_C_D) 0.070 -0.186 data_memory/memory_data_reg[268435884][15] + net (fo=18130, routed) 0.914 -0.212 data_memory/clk_out1 + SLICE_X39Y110 FDRE r data_memory/memory_data_reg[268435932][15]/C + clock pessimism 0.030 -0.182 + SLICE_X39Y110 FDRE (Hold_fdre_C_D) 0.070 -0.112 data_memory/memory_data_reg[268435932][15] ------------------------------------------------------------------- - required time 0.186 - arrival time -0.081 + required time 0.112 + arrival time -0.049 ------------------------------------------------------------------- - slack 0.106 + slack 0.063 -Slack (MET) : 0.106ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[21]_rep__5/C +Slack (MET) : 0.066ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[21]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435478][21]/D + Destination: data_memory/memory_data_reg[268435959][21]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.438ns (logic 0.141ns (32.208%) route 0.297ns (67.792%)) + Data Path Delay: 0.395ns (logic 0.141ns (35.729%) route 0.254ns (64.271%)) + Logic Levels: 0 + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.215ns + Source Clock Delay (SCD): -0.448ns + Clock Pessimism Removal (CPR): -0.030ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.639 -0.448 memory_access/clk_out1 + SLICE_X35Y112 FDRE r memory_access/MEM_memory_write_data_reg[21]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.307 r memory_access/MEM_memory_write_data_reg[21]/Q + net (fo=64, routed) 0.254 -0.053 data_memory/memory_data_reg[268435905][31]_0[21] + SLICE_X39Y114 FDRE r data_memory/memory_data_reg[268435959][21]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.911 -0.215 data_memory/clk_out1 + SLICE_X39Y114 FDRE r data_memory/memory_data_reg[268435959][21]/C + clock pessimism 0.030 -0.185 + SLICE_X39Y114 FDRE (Hold_fdre_C_D) 0.066 -0.119 data_memory/memory_data_reg[268435959][21] + ------------------------------------------------------------------- + required time 0.119 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.066 + +Slack (MET) : 0.069ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[22]/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435937][22]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.401ns (logic 0.141ns (35.127%) route 0.260ns (64.873%)) + Logic Levels: 0 + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.215ns + Source Clock Delay (SCD): -0.448ns + Clock Pessimism Removal (CPR): -0.030ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.639 -0.448 memory_access/clk_out1 + SLICE_X35Y112 FDRE r memory_access/MEM_memory_write_data_reg[22]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.307 r memory_access/MEM_memory_write_data_reg[22]/Q + net (fo=64, routed) 0.260 -0.046 data_memory/memory_data_reg[268435905][31]_0[22] + SLICE_X36Y114 FDRE r data_memory/memory_data_reg[268435937][22]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.911 -0.215 data_memory/clk_out1 + SLICE_X36Y114 FDRE r data_memory/memory_data_reg[268435937][22]/C + clock pessimism 0.030 -0.185 + SLICE_X36Y114 FDRE (Hold_fdre_C_D) 0.070 -0.115 data_memory/memory_data_reg[268435937][22] + ------------------------------------------------------------------- + required time 0.115 + arrival time -0.046 + ------------------------------------------------------------------- + slack 0.069 + +Slack (MET) : 0.072ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[24]_rep__1/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435769][24]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.407ns (logic 0.141ns (34.609%) route 0.266ns (65.391%)) + Logic Levels: 0 + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.222ns + Source Clock Delay (SCD): -0.458ns + Clock Pessimism Removal (CPR): -0.030ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.629 -0.458 memory_access/clk_out1 + SLICE_X37Y125 FDRE r memory_access/MEM_memory_write_data_reg[24]_rep__1/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y125 FDRE (Prop_fdre_C_Q) 0.141 -0.317 r memory_access/MEM_memory_write_data_reg[24]_rep__1/Q + net (fo=64, routed) 0.266 -0.050 data_memory/memory_data_reg[268435713][31]_0[24] + SLICE_X32Y128 FDRE r data_memory/memory_data_reg[268435769][24]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.904 -0.222 data_memory/clk_out1 + SLICE_X32Y128 FDRE r data_memory/memory_data_reg[268435769][24]/C + clock pessimism 0.030 -0.192 + SLICE_X32Y128 FDRE (Hold_fdre_C_D) 0.070 -0.122 data_memory/memory_data_reg[268435769][24] + ------------------------------------------------------------------- + required time 0.122 + arrival time -0.050 + ------------------------------------------------------------------- + slack 0.072 + +Slack (MET) : 0.076ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[21]/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435923][21]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.403ns (logic 0.141ns (34.960%) route 0.262ns (65.040%)) Logic Levels: 0 Clock Path Skew: 0.262ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.302ns - Source Clock Delay (SCD): -0.530ns - Clock Pessimism Removal (CPR): -0.034ns + Destination Clock Delay (DCD): -0.216ns + Source Clock Delay (SCD): -0.448ns + Clock Pessimism Removal (CPR): -0.030ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1580,12 +1477,12 @@ Slack (MET) : 0.106ns (arrival time - required time) -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.557 -0.530 memory_access/clk_out1 - SLICE_X40Y63 FDRE r memory_access/MEM_memory_write_data_reg[21]_rep__5/C + net (fo=18130, routed) 0.639 -0.448 memory_access/clk_out1 + SLICE_X35Y112 FDRE r memory_access/MEM_memory_write_data_reg[21]/C ------------------------------------------------------------------- ------------------- - SLICE_X40Y63 FDRE (Prop_fdre_C_Q) 0.141 -0.389 r memory_access/MEM_memory_write_data_reg[21]_rep__5/Q - net (fo=64, routed) 0.297 -0.092 data_memory/memory_data_reg[268435457][31]_0[21] - SLICE_X35Y63 FDRE r data_memory/memory_data_reg[268435478][21]/D + SLICE_X35Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.307 r memory_access/MEM_memory_write_data_reg[21]/Q + net (fo=64, routed) 0.262 -0.044 data_memory/memory_data_reg[268435905][31]_0[21] + SLICE_X36Y115 FDRE r data_memory/memory_data_reg[268435923][21]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1598,30 +1495,30 @@ Slack (MET) : 0.106ns (arrival time - required time) -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.823 -0.302 data_memory/clk_out1 - SLICE_X35Y63 FDRE r data_memory/memory_data_reg[268435478][21]/C - clock pessimism 0.034 -0.268 - SLICE_X35Y63 FDRE (Hold_fdre_C_D) 0.070 -0.198 data_memory/memory_data_reg[268435478][21] + net (fo=18130, routed) 0.910 -0.216 data_memory/clk_out1 + SLICE_X36Y115 FDRE r data_memory/memory_data_reg[268435923][21]/C + clock pessimism 0.030 -0.186 + SLICE_X36Y115 FDRE (Hold_fdre_C_D) 0.066 -0.120 data_memory/memory_data_reg[268435923][21] ------------------------------------------------------------------- - required time 0.198 - arrival time -0.092 + required time 0.120 + arrival time -0.044 ------------------------------------------------------------------- - slack 0.106 + slack 0.076 -Slack (MET) : 0.106ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[31]_rep__2/C +Slack (MET) : 0.078ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[16]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435708][31]/D + Destination: data_memory/memory_data_reg[268435941][16]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.422ns (logic 0.141ns (33.375%) route 0.281ns (66.625%)) + Data Path Delay: 0.403ns (logic 0.141ns (35.011%) route 0.262ns (64.989%)) Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.296ns - Source Clock Delay (SCD): -0.526ns - Clock Pessimism Removal (CPR): -0.034ns + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.212ns + Source Clock Delay (SCD): -0.448ns + Clock Pessimism Removal (CPR): -0.030ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1635,12 +1532,12 @@ Slack (MET) : 0.106ns (arrival time - required time) -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.561 -0.526 memory_access/clk_out1 - SLICE_X37Y10 FDRE r memory_access/MEM_memory_write_data_reg[31]_rep__2/C + net (fo=18130, routed) 0.639 -0.448 memory_access/clk_out1 + SLICE_X35Y112 FDRE r memory_access/MEM_memory_write_data_reg[16]/C ------------------------------------------------------------------- ------------------- - SLICE_X37Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.385 r memory_access/MEM_memory_write_data_reg[31]_rep__2/Q - net (fo=64, routed) 0.281 -0.104 data_memory/memory_data_reg[268435649][31]_0[31] - SLICE_X34Y9 FDRE r data_memory/memory_data_reg[268435708][31]/D + SLICE_X35Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.307 r memory_access/MEM_memory_write_data_reg[16]/Q + net (fo=64, routed) 0.262 -0.045 data_memory/memory_data_reg[268435905][31]_0[16] + SLICE_X38Y111 FDRE r data_memory/memory_data_reg[268435941][16]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1653,15 +1550,180 @@ Slack (MET) : 0.106ns (arrival time - required time) -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.830 -0.296 data_memory/clk_out1 - SLICE_X34Y9 FDRE r data_memory/memory_data_reg[268435708][31]/C - clock pessimism 0.034 -0.262 - SLICE_X34Y9 FDRE (Hold_fdre_C_D) 0.052 -0.210 data_memory/memory_data_reg[268435708][31] + net (fo=18130, routed) 0.914 -0.212 data_memory/clk_out1 + SLICE_X38Y111 FDRE r data_memory/memory_data_reg[268435941][16]/C + clock pessimism 0.030 -0.182 + SLICE_X38Y111 FDRE (Hold_fdre_C_D) 0.059 -0.123 data_memory/memory_data_reg[268435941][16] ------------------------------------------------------------------- - required time 0.210 - arrival time -0.104 + required time 0.123 + arrival time -0.045 ------------------------------------------------------------------- - slack 0.106 + slack 0.078 + +Slack (MET) : 0.080ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[21]_rep/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435900][21]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.415ns (logic 0.141ns (33.997%) route 0.274ns (66.003%)) + Logic Levels: 0 + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.223ns + Source Clock Delay (SCD): -0.458ns + Clock Pessimism Removal (CPR): -0.030ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.629 -0.458 memory_access/clk_out1 + SLICE_X37Y125 FDRE r memory_access/MEM_memory_write_data_reg[21]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y125 FDRE (Prop_fdre_C_Q) 0.141 -0.317 r memory_access/MEM_memory_write_data_reg[21]_rep/Q + net (fo=64, routed) 0.274 -0.043 data_memory/memory_data_reg[268435841][31]_0[21] + SLICE_X35Y127 FDRE r data_memory/memory_data_reg[268435900][21]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.903 -0.223 data_memory/clk_out1 + SLICE_X35Y127 FDRE r data_memory/memory_data_reg[268435900][21]/C + clock pessimism 0.030 -0.193 + SLICE_X35Y127 FDRE (Hold_fdre_C_D) 0.070 -0.123 data_memory/memory_data_reg[268435900][21] + ------------------------------------------------------------------- + required time 0.123 + arrival time -0.043 + ------------------------------------------------------------------- + slack 0.080 + +Slack (MET) : 0.085ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[18]_rep__0/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435832][18]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.608%) route 0.279ns (66.392%)) + Logic Levels: 0 + Clock Path Skew: 0.269ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.219ns + Source Clock Delay (SCD): -0.458ns + Clock Pessimism Removal (CPR): -0.030ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.629 -0.458 memory_access/clk_out1 + SLICE_X37Y125 FDRE r memory_access/MEM_memory_write_data_reg[18]_rep__0/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y125 FDRE (Prop_fdre_C_Q) 0.141 -0.317 r memory_access/MEM_memory_write_data_reg[18]_rep__0/Q + net (fo=64, routed) 0.279 -0.038 data_memory/memory_data_reg[268435777][31]_0[18] + SLICE_X35Y131 FDRE r data_memory/memory_data_reg[268435832][18]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.907 -0.219 data_memory/clk_out1 + SLICE_X35Y131 FDRE r data_memory/memory_data_reg[268435832][18]/C + clock pessimism 0.030 -0.189 + SLICE_X35Y131 FDRE (Hold_fdre_C_D) 0.066 -0.123 data_memory/memory_data_reg[268435832][18] + ------------------------------------------------------------------- + required time 0.123 + arrival time -0.038 + ------------------------------------------------------------------- + slack 0.085 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[15]_rep__3/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435605][15]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.355ns (logic 0.128ns (36.020%) route 0.227ns (63.980%)) + Logic Levels: 0 + Clock Path Skew: 0.274ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.288ns + Source Clock Delay (SCD): -0.523ns + Clock Pessimism Removal (CPR): -0.039ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.564 -0.523 memory_access/clk_out1 + SLICE_X51Y54 FDRE r memory_access/MEM_memory_write_data_reg[15]_rep__3/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y54 FDRE (Prop_fdre_C_Q) 0.128 -0.395 r memory_access/MEM_memory_write_data_reg[15]_rep__3/Q + net (fo=64, routed) 0.227 -0.168 data_memory/memory_data_reg[268435585][31]_0[15] + SLICE_X55Y49 FDRE r data_memory/memory_data_reg[268435605][15]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.838 -0.288 data_memory/clk_out1 + SLICE_X55Y49 FDRE r data_memory/memory_data_reg[268435605][15]/C + clock pessimism 0.039 -0.249 + SLICE_X55Y49 FDRE (Hold_fdre_C_D) -0.008 -0.257 data_memory/memory_data_reg[268435605][15] + ------------------------------------------------------------------- + required time 0.257 + arrival time -0.168 + ------------------------------------------------------------------- + slack 0.089 @@ -1677,35 +1739,35 @@ Sources: { pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y0 pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 20.000 18.751 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKOUT0 -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X50Y52 data_memory/memory_data_reg[268435456][0]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X29Y51 data_memory/memory_data_reg[268435456][10]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X45Y73 data_memory/memory_data_reg[268435456][11]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X30Y63 data_memory/memory_data_reg[268435456][12]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X35Y61 data_memory/memory_data_reg[268435456][13]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X61Y62 data_memory/memory_data_reg[268435456][14]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X29Y74 data_memory/memory_data_reg[268435456][15]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X65Y71 data_memory/memory_data_reg[268435456][16]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X58Y77 data_memory/memory_data_reg[268435456][0]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X37Y56 data_memory/memory_data_reg[268435456][10]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X10Y58 data_memory/memory_data_reg[268435456][11]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X57Y56 data_memory/memory_data_reg[268435456][12]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X37Y56 data_memory/memory_data_reg[268435456][13]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X37Y75 data_memory/memory_data_reg[268435456][14]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X58Y77 data_memory/memory_data_reg[268435456][15]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X44Y77 data_memory/memory_data_reg[268435456][16]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 20.000 140.000 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKOUT0 -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X50Y52 data_memory/memory_data_reg[268435456][0]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X50Y52 data_memory/memory_data_reg[268435456][0]/C -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X29Y51 data_memory/memory_data_reg[268435456][10]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X29Y51 data_memory/memory_data_reg[268435456][10]/C -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X45Y73 data_memory/memory_data_reg[268435456][11]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X45Y73 data_memory/memory_data_reg[268435456][11]/C -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X30Y63 data_memory/memory_data_reg[268435456][12]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X30Y63 data_memory/memory_data_reg[268435456][12]/C -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X35Y61 data_memory/memory_data_reg[268435456][13]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X35Y61 data_memory/memory_data_reg[268435456][13]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X50Y52 data_memory/memory_data_reg[268435456][0]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X50Y52 data_memory/memory_data_reg[268435456][0]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X29Y51 data_memory/memory_data_reg[268435456][10]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X29Y51 data_memory/memory_data_reg[268435456][10]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X45Y73 data_memory/memory_data_reg[268435456][11]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X45Y73 data_memory/memory_data_reg[268435456][11]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X30Y63 data_memory/memory_data_reg[268435456][12]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X30Y63 data_memory/memory_data_reg[268435456][12]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X35Y61 data_memory/memory_data_reg[268435456][13]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X35Y61 data_memory/memory_data_reg[268435456][13]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X58Y77 data_memory/memory_data_reg[268435456][0]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X58Y77 data_memory/memory_data_reg[268435456][0]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][10]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][10]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X10Y58 data_memory/memory_data_reg[268435456][11]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X10Y58 data_memory/memory_data_reg[268435456][11]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X57Y56 data_memory/memory_data_reg[268435456][12]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X57Y56 data_memory/memory_data_reg[268435456][12]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][13]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][13]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X58Y77 data_memory/memory_data_reg[268435456][0]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X58Y77 data_memory/memory_data_reg[268435456][0]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][10]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][10]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X10Y58 data_memory/memory_data_reg[268435456][11]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X10Y58 data_memory/memory_data_reg[268435456][11]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X57Y56 data_memory/memory_data_reg[268435456][12]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X57Y56 data_memory/memory_data_reg[268435456][12]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][13]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][13]/C @@ -1747,78 +1809,6 @@ Min Delay 12 Endpoints Max Delay Paths -------------------------------------------------------------------------------------- -Slack: inf - Source: data_memory/memory_data_reg[268435460][2]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[2] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 7.363ns (logic 3.983ns (54.097%) route 3.380ns (45.903%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.621 -2.355 data_memory/clk_out1 - SLICE_X65Y63 FDRE r data_memory/memory_data_reg[268435460][2]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y63 FDRE (Prop_fdre_C_Q) 0.456 -1.899 r data_memory/memory_data_reg[268435460][2]_lopt_replica/Q - net (fo=1, routed) 3.380 1.480 lopt_4 - V5 OBUF (Prop_obuf_I_O) 3.527 5.007 r bcd_control_OBUF[2]_inst/O - net (fo=0) 0.000 5.007 bcd_control[2] - V5 r bcd_control[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][4]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[4] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 7.258ns (logic 4.011ns (55.264%) route 3.247ns (44.736%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.567 -2.409 data_memory/clk_out1 - SLICE_X43Y48 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X43Y48 FDRE (Prop_fdre_C_Q) 0.456 -1.953 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q - net (fo=1, routed) 3.247 1.294 lopt_6 - T5 OBUF (Prop_obuf_I_O) 3.555 4.849 r bcd_control_OBUF[4]_inst/O - net (fo=0) 0.000 4.849 bcd_control[4] - T5 r bcd_control[4] (OUT) - ------------------------------------------------------------------- ------------------- - Slack: inf Source: data_memory/memory_data_reg[268435460][8]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -1826,7 +1816,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 7.058ns (logic 4.024ns (57.007%) route 3.034ns (42.993%)) + Data Path Delay: 7.652ns (logic 4.162ns (54.388%) route 3.490ns (45.612%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -1845,16 +1835,88 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.555 -2.421 data_memory/clk_out1 - SLICE_X44Y55 FDRE r data_memory/memory_data_reg[268435460][8]_lopt_replica/C + net (fo=18130, routed) 1.553 -2.423 data_memory/clk_out1 + SLICE_X36Y56 FDRE r data_memory/memory_data_reg[268435460][8]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X44Y55 FDRE (Prop_fdre_C_Q) 0.456 -1.965 r data_memory/memory_data_reg[268435460][8]_lopt_replica/Q - net (fo=1, routed) 3.034 1.069 lopt_10 - Y3 OBUF (Prop_obuf_I_O) 3.568 4.637 r bcd_control_OBUF[8]_inst/O - net (fo=0) 0.000 4.637 bcd_control[8] + SLICE_X36Y56 FDRE (Prop_fdre_C_Q) 0.419 -2.004 r data_memory/memory_data_reg[268435460][8]_lopt_replica/Q + net (fo=1, routed) 3.490 1.486 lopt_10 + Y3 OBUF (Prop_obuf_I_O) 3.743 5.228 r bcd_control_OBUF[8]_inst/O + net (fo=0) 0.000 5.228 bcd_control[8] Y3 r bcd_control[8] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: data_memory/memory_data_reg[268435460][11]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[11] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 7.408ns (logic 4.054ns (54.728%) route 3.354ns (45.272%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.550 -2.426 data_memory/clk_out1 + SLICE_X10Y65 FDRE r data_memory/memory_data_reg[268435460][11]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y65 FDRE (Prop_fdre_C_Q) 0.518 -1.908 r data_memory/memory_data_reg[268435460][11]_lopt_replica/Q + net (fo=1, routed) 3.354 1.445 lopt_2 + M2 OBUF (Prop_obuf_I_O) 3.536 4.982 r bcd_control_OBUF[11]_inst/O + net (fo=0) 0.000 4.982 bcd_control[11] + M2 r bcd_control[11] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][2]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 7.111ns (logic 3.983ns (56.015%) route 3.128ns (43.985%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.626 -2.350 data_memory/clk_out1 + SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][2]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.456 -1.894 r data_memory/memory_data_reg[268435460][2]_lopt_replica/Q + net (fo=1, routed) 3.128 1.233 lopt_4 + V5 OBUF (Prop_obuf_I_O) 3.527 4.760 r bcd_control_OBUF[2]_inst/O + net (fo=0) 0.000 4.760 bcd_control[2] + V5 r bcd_control[2] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: data_memory/memory_data_reg[268435460][3]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -1862,7 +1924,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 6.718ns (logic 4.012ns (59.720%) route 2.706ns (40.280%)) + Data Path Delay: 7.072ns (logic 4.150ns (58.677%) route 2.922ns (41.323%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -1881,24 +1943,24 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.639 -2.337 data_memory/clk_out1 - SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C + net (fo=18130, routed) 1.626 -2.350 data_memory/clk_out1 + SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y48 FDRE (Prop_fdre_C_Q) 0.456 -1.881 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q - net (fo=1, routed) 2.706 0.825 lopt_5 - U5 OBUF (Prop_obuf_I_O) 3.556 4.381 r bcd_control_OBUF[3]_inst/O - net (fo=0) 0.000 4.381 bcd_control[3] + SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.419 -1.931 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q + net (fo=1, routed) 2.922 0.991 lopt_5 + U5 OBUF (Prop_obuf_I_O) 3.731 4.722 r bcd_control_OBUF[3]_inst/O + net (fo=0) 0.000 4.722 bcd_control[3] U5 r bcd_control[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: data_memory/memory_data_reg[268435460][10]_lopt_replica/C + Source: data_memory/memory_data_reg[268435460][4]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[10] + Destination: bcd_control[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 6.786ns (logic 4.000ns (58.945%) route 2.786ns (41.055%)) + Data Path Delay: 6.913ns (logic 4.147ns (59.987%) route 2.766ns (40.013%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -1917,14 +1979,14 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.554 -2.422 data_memory/clk_out1 - SLICE_X32Y51 FDRE r data_memory/memory_data_reg[268435460][10]_lopt_replica/C + net (fo=18130, routed) 1.626 -2.350 data_memory/clk_out1 + SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X32Y51 FDRE (Prop_fdre_C_Q) 0.456 -1.966 r data_memory/memory_data_reg[268435460][10]_lopt_replica/Q - net (fo=1, routed) 2.786 0.820 lopt_1 - P2 OBUF (Prop_obuf_I_O) 3.544 4.363 r bcd_control_OBUF[10]_inst/O - net (fo=0) 0.000 4.363 bcd_control[10] - P2 r bcd_control[10] (OUT) + SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.419 -1.931 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q + net (fo=1, routed) 2.766 0.835 lopt_6 + T5 OBUF (Prop_obuf_I_O) 3.728 4.563 r bcd_control_OBUF[4]_inst/O + net (fo=0) 0.000 4.563 bcd_control[4] + T5 r bcd_control[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -1934,7 +1996,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 6.339ns (logic 4.010ns (63.255%) route 2.329ns (36.745%)) + Data Path Delay: 6.854ns (logic 4.148ns (60.513%) route 2.706ns (39.487%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -1953,13 +2015,13 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.639 -2.337 data_memory/clk_out1 - SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C + net (fo=18130, routed) 1.626 -2.350 data_memory/clk_out1 + SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y48 FDRE (Prop_fdre_C_Q) 0.456 -1.881 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q - net (fo=1, routed) 2.329 0.448 lopt_8 - W4 OBUF (Prop_obuf_I_O) 3.554 4.002 r bcd_control_OBUF[6]_inst/O - net (fo=0) 0.000 4.002 bcd_control[6] + SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.419 -1.931 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q + net (fo=1, routed) 2.706 0.775 lopt_8 + W4 OBUF (Prop_obuf_I_O) 3.729 4.504 r bcd_control_OBUF[6]_inst/O + net (fo=0) 0.000 4.504 bcd_control[6] W4 r bcd_control[6] (OUT) ------------------------------------------------------------------- ------------------- @@ -1970,7 +2032,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 6.079ns (logic 4.006ns (65.911%) route 2.072ns (34.089%)) + Data Path Delay: 6.714ns (logic 4.006ns (59.673%) route 2.708ns (40.327%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -1989,24 +2051,24 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.639 -2.337 data_memory/clk_out1 - SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435460][7]_lopt_replica/C + net (fo=18130, routed) 1.559 -2.417 data_memory/clk_out1 + SLICE_X55Y56 FDRE r data_memory/memory_data_reg[268435460][7]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y48 FDRE (Prop_fdre_C_Q) 0.456 -1.881 r data_memory/memory_data_reg[268435460][7]_lopt_replica/Q - net (fo=1, routed) 2.072 0.191 lopt_9 - V3 OBUF (Prop_obuf_I_O) 3.550 3.742 r bcd_control_OBUF[7]_inst/O - net (fo=0) 0.000 3.742 bcd_control[7] + SLICE_X55Y56 FDRE (Prop_fdre_C_Q) 0.456 -1.961 r data_memory/memory_data_reg[268435460][7]_lopt_replica/Q + net (fo=1, routed) 2.708 0.746 lopt_9 + V3 OBUF (Prop_obuf_I_O) 3.550 4.297 r bcd_control_OBUF[7]_inst/O + net (fo=0) 0.000 4.297 bcd_control[7] V3 r bcd_control[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: data_memory/memory_data_reg[268435460][1]_lopt_replica/C + Source: data_memory/memory_data_reg[268435460][0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[1] + Destination: bcd_control[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 5.851ns (logic 3.991ns (68.204%) route 1.860ns (31.796%)) + Data Path Delay: 6.587ns (logic 4.059ns (61.625%) route 2.528ns (38.375%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2025,24 +2087,24 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.626 -2.350 data_memory/clk_out1 - SLICE_X63Y55 FDRE r data_memory/memory_data_reg[268435460][1]_lopt_replica/C + net (fo=18130, routed) 1.542 -2.434 data_memory/clk_out1 + SLICE_X56Y72 FDRE r data_memory/memory_data_reg[268435460][0]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X63Y55 FDRE (Prop_fdre_C_Q) 0.456 -1.894 r data_memory/memory_data_reg[268435460][1]_lopt_replica/Q - net (fo=1, routed) 1.860 -0.034 lopt_3 - P5 OBUF (Prop_obuf_I_O) 3.535 3.501 r bcd_control_OBUF[1]_inst/O - net (fo=0) 0.000 3.501 bcd_control[1] - P5 r bcd_control[1] (OUT) + SLICE_X56Y72 FDRE (Prop_fdre_C_Q) 0.518 -1.916 r data_memory/memory_data_reg[268435460][0]_lopt_replica/Q + net (fo=1, routed) 2.528 0.611 lopt + N2 OBUF (Prop_obuf_I_O) 3.541 4.152 r bcd_control_OBUF[0]_inst/O + net (fo=0) 0.000 4.152 bcd_control[0] + N2 r bcd_control[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: data_memory/memory_data_reg[268435460][11]_lopt_replica/C + Source: data_memory/memory_data_reg[268435460][5]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[11] + Destination: bcd_control[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 5.805ns (logic 3.992ns (68.771%) route 1.813ns (31.229%)) + Data Path Delay: 6.129ns (logic 4.014ns (65.490%) route 2.115ns (34.510%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2061,14 +2123,14 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.613 -2.363 data_memory/clk_out1 - SLICE_X65Y70 FDRE r data_memory/memory_data_reg[268435460][11]_lopt_replica/C + net (fo=18130, routed) 1.559 -2.417 data_memory/clk_out1 + SLICE_X55Y56 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y70 FDRE (Prop_fdre_C_Q) 0.456 -1.907 r data_memory/memory_data_reg[268435460][11]_lopt_replica/Q - net (fo=1, routed) 1.813 -0.094 lopt_2 - M2 OBUF (Prop_obuf_I_O) 3.536 3.442 r bcd_control_OBUF[11]_inst/O - net (fo=0) 0.000 3.442 bcd_control[11] - M2 r bcd_control[11] (OUT) + SLICE_X55Y56 FDRE (Prop_fdre_C_Q) 0.456 -1.961 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q + net (fo=1, routed) 2.115 0.154 lopt_7 + P1 OBUF (Prop_obuf_I_O) 3.558 3.712 r bcd_control_OBUF[5]_inst/O + net (fo=0) 0.000 3.712 bcd_control[5] + P1 r bcd_control[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -2078,7 +2140,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 5.684ns (logic 4.016ns (70.660%) route 1.668ns (29.340%)) + Data Path Delay: 5.813ns (logic 4.016ns (69.089%) route 1.797ns (30.911%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2097,13 +2159,13 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.624 -2.352 data_memory/clk_out1 - SLICE_X65Y59 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C + net (fo=18130, routed) 1.624 -2.352 data_memory/clk_out1 + SLICE_X62Y59 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y59 FDRE (Prop_fdre_C_Q) 0.456 -1.896 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q - net (fo=1, routed) 1.668 -0.229 lopt_11 - R1 OBUF (Prop_obuf_I_O) 3.560 3.332 r bcd_control_OBUF[9]_inst/O - net (fo=0) 0.000 3.332 bcd_control[9] + SLICE_X62Y59 FDRE (Prop_fdre_C_Q) 0.456 -1.896 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q + net (fo=1, routed) 1.797 -0.099 lopt_11 + R1 OBUF (Prop_obuf_I_O) 3.560 3.461 r bcd_control_OBUF[9]_inst/O + net (fo=0) 0.000 3.461 bcd_control[9] R1 r bcd_control[9] (OUT) ------------------------------------------------------------------- ------------------- @@ -2114,13 +2176,13 @@ Slack: inf Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf - Source: data_memory/memory_data_reg[268435460][0]_lopt_replica/C + Source: data_memory/memory_data_reg[268435460][10]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[0] + Destination: bcd_control[10] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 1.709ns (logic 1.383ns (80.886%) route 0.327ns (19.114%)) + Data Path Delay: 1.716ns (logic 1.386ns (80.750%) route 0.330ns (19.250%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2139,122 +2201,14 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.593 -0.494 data_memory/clk_out1 - SLICE_X63Y55 FDRE r data_memory/memory_data_reg[268435460][0]_lopt_replica/C + net (fo=18130, routed) 0.593 -0.494 data_memory/clk_out1 + SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][10]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X63Y55 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][0]_lopt_replica/Q - net (fo=1, routed) 0.327 -0.026 lopt - N2 OBUF (Prop_obuf_I_O) 1.242 1.215 r bcd_control_OBUF[0]_inst/O - net (fo=0) 0.000 1.215 bcd_control[0] - N2 r bcd_control[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][5]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[5] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.732ns (logic 1.400ns (80.813%) route 0.332ns (19.187%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.592 -0.495 data_memory/clk_out1 - SLICE_X65Y59 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y59 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q - net (fo=1, routed) 0.332 -0.022 lopt_7 - P1 OBUF (Prop_obuf_I_O) 1.259 1.237 r bcd_control_OBUF[5]_inst/O - net (fo=0) 0.000 1.237 bcd_control[5] - P1 r bcd_control[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][9]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[9] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.739ns (logic 1.402ns (80.633%) route 0.337ns (19.367%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.592 -0.495 data_memory/clk_out1 - SLICE_X65Y59 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y59 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q - net (fo=1, routed) 0.337 -0.017 lopt_11 - R1 OBUF (Prop_obuf_I_O) 1.261 1.244 r bcd_control_OBUF[9]_inst/O - net (fo=0) 0.000 1.244 bcd_control[9] - R1 r bcd_control[9] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][11]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[11] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.758ns (logic 1.378ns (78.391%) route 0.380ns (21.609%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.584 -0.503 data_memory/clk_out1 - SLICE_X65Y70 FDRE r data_memory/memory_data_reg[268435460][11]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y70 FDRE (Prop_fdre_C_Q) 0.141 -0.362 r data_memory/memory_data_reg[268435460][11]_lopt_replica/Q - net (fo=1, routed) 0.380 0.018 lopt_2 - M2 OBUF (Prop_obuf_I_O) 1.237 1.255 r bcd_control_OBUF[11]_inst/O - net (fo=0) 0.000 1.255 bcd_control[11] - M2 r bcd_control[11] (OUT) + SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][10]_lopt_replica/Q + net (fo=1, routed) 0.330 -0.023 lopt_1 + P2 OBUF (Prop_obuf_I_O) 1.245 1.222 r bcd_control_OBUF[10]_inst/O + net (fo=0) 0.000 1.222 bcd_control[10] + P2 r bcd_control[10] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -2264,7 +2218,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 1.775ns (logic 1.376ns (77.555%) route 0.398ns (22.445%)) + Data Path Delay: 1.726ns (logic 1.376ns (79.733%) route 0.350ns (20.267%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2283,16 +2237,124 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.593 -0.494 data_memory/clk_out1 - SLICE_X63Y55 FDRE r data_memory/memory_data_reg[268435460][1]_lopt_replica/C + net (fo=18130, routed) 0.593 -0.494 data_memory/clk_out1 + SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][1]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X63Y55 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][1]_lopt_replica/Q - net (fo=1, routed) 0.398 0.045 lopt_3 - P5 OBUF (Prop_obuf_I_O) 1.235 1.281 r bcd_control_OBUF[1]_inst/O - net (fo=0) 0.000 1.281 bcd_control[1] + SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][1]_lopt_replica/Q + net (fo=1, routed) 0.350 -0.003 lopt_3 + P5 OBUF (Prop_obuf_I_O) 1.235 1.232 r bcd_control_OBUF[1]_inst/O + net (fo=0) 0.000 1.232 bcd_control[1] P5 r bcd_control[1] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: data_memory/memory_data_reg[268435460][9]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[9] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.783ns (logic 1.402ns (78.632%) route 0.381ns (21.368%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.592 -0.495 data_memory/clk_out1 + SLICE_X62Y59 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y59 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q + net (fo=1, routed) 0.381 0.027 lopt_11 + R1 OBUF (Prop_obuf_I_O) 1.261 1.288 r bcd_control_OBUF[9]_inst/O + net (fo=0) 0.000 1.288 bcd_control[9] + R1 r bcd_control[9] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][5]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[5] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.961ns (logic 1.400ns (71.380%) route 0.561ns (28.620%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.564 -0.523 data_memory/clk_out1 + SLICE_X55Y56 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X55Y56 FDRE (Prop_fdre_C_Q) 0.141 -0.382 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q + net (fo=1, routed) 0.561 0.179 lopt_7 + P1 OBUF (Prop_obuf_I_O) 1.259 1.438 r bcd_control_OBUF[5]_inst/O + net (fo=0) 0.000 1.438 bcd_control[5] + P1 r bcd_control[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][0]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.124ns (logic 1.406ns (66.173%) route 0.719ns (33.827%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.556 -0.531 data_memory/clk_out1 + SLICE_X56Y72 FDRE r data_memory/memory_data_reg[268435460][0]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y72 FDRE (Prop_fdre_C_Q) 0.164 -0.367 r data_memory/memory_data_reg[268435460][0]_lopt_replica/Q + net (fo=1, routed) 0.719 0.351 lopt + N2 OBUF (Prop_obuf_I_O) 1.242 1.593 r bcd_control_OBUF[0]_inst/O + net (fo=0) 0.000 1.593 bcd_control[0] + N2 r bcd_control[0] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: data_memory/memory_data_reg[268435460][7]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -2300,7 +2362,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 1.896ns (logic 1.392ns (73.414%) route 0.504ns (26.586%)) + Data Path Delay: 2.218ns (logic 1.392ns (62.774%) route 0.826ns (37.226%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2319,13 +2381,13 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.596 -0.491 data_memory/clk_out1 - SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435460][7]_lopt_replica/C + net (fo=18130, routed) 0.564 -0.523 data_memory/clk_out1 + SLICE_X55Y56 FDRE r data_memory/memory_data_reg[268435460][7]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.350 r data_memory/memory_data_reg[268435460][7]_lopt_replica/Q - net (fo=1, routed) 0.504 0.154 lopt_9 - V3 OBUF (Prop_obuf_I_O) 1.251 1.405 r bcd_control_OBUF[7]_inst/O - net (fo=0) 0.000 1.405 bcd_control[7] + SLICE_X55Y56 FDRE (Prop_fdre_C_Q) 0.141 -0.382 r data_memory/memory_data_reg[268435460][7]_lopt_replica/Q + net (fo=1, routed) 0.826 0.443 lopt_9 + V3 OBUF (Prop_obuf_I_O) 1.251 1.695 r bcd_control_OBUF[7]_inst/O + net (fo=0) 0.000 1.695 bcd_control[7] V3 r bcd_control[7] (OUT) ------------------------------------------------------------------- ------------------- @@ -2336,7 +2398,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.010ns (logic 1.395ns (69.401%) route 0.615ns (30.599%)) + Data Path Delay: 2.197ns (logic 1.435ns (65.337%) route 0.761ns (34.663%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2355,16 +2417,52 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.596 -0.491 data_memory/clk_out1 - SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C + net (fo=18130, routed) 0.593 -0.494 data_memory/clk_out1 + SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.350 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q - net (fo=1, routed) 0.615 0.265 lopt_8 - W4 OBUF (Prop_obuf_I_O) 1.254 1.519 r bcd_control_OBUF[6]_inst/O - net (fo=0) 0.000 1.519 bcd_control[6] + SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.128 -0.366 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q + net (fo=1, routed) 0.761 0.395 lopt_8 + W4 OBUF (Prop_obuf_I_O) 1.307 1.702 r bcd_control_OBUF[6]_inst/O + net (fo=0) 0.000 1.702 bcd_control[6] W4 r bcd_control[6] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: data_memory/memory_data_reg[268435460][4]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[4] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.250ns (logic 1.437ns (63.854%) route 0.813ns (36.146%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 0.593 -0.494 data_memory/clk_out1 + SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.128 -0.366 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q + net (fo=1, routed) 0.813 0.447 lopt_6 + T5 OBUF (Prop_obuf_I_O) 1.309 1.756 r bcd_control_OBUF[4]_inst/O + net (fo=0) 0.000 1.756 bcd_control[4] + T5 r bcd_control[4] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: data_memory/memory_data_reg[268435460][3]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -2372,7 +2470,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.169ns (logic 1.397ns (64.418%) route 0.772ns (35.582%)) + Data Path Delay: 2.307ns (logic 1.438ns (62.353%) route 0.868ns (37.647%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2391,24 +2489,24 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.596 -0.491 data_memory/clk_out1 - SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C + net (fo=18130, routed) 0.593 -0.494 data_memory/clk_out1 + SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.350 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q - net (fo=1, routed) 0.772 0.422 lopt_5 - U5 OBUF (Prop_obuf_I_O) 1.256 1.678 r bcd_control_OBUF[3]_inst/O - net (fo=0) 0.000 1.678 bcd_control[3] + SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.128 -0.366 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q + net (fo=1, routed) 0.868 0.502 lopt_5 + U5 OBUF (Prop_obuf_I_O) 1.310 1.813 r bcd_control_OBUF[3]_inst/O + net (fo=0) 0.000 1.813 bcd_control[3] U5 r bcd_control[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: data_memory/memory_data_reg[268435460][10]_lopt_replica/C + Source: data_memory/memory_data_reg[268435460][2]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[10] + Destination: bcd_control[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.276ns (logic 1.386ns (60.891%) route 0.890ns (39.109%)) + Data Path Delay: 2.341ns (logic 1.369ns (58.462%) route 0.973ns (41.538%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2427,50 +2525,14 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.562 -0.525 data_memory/clk_out1 - SLICE_X32Y51 FDRE r data_memory/memory_data_reg[268435460][10]_lopt_replica/C + net (fo=18130, routed) 0.593 -0.494 data_memory/clk_out1 + SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][2]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X32Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.384 r data_memory/memory_data_reg[268435460][10]_lopt_replica/Q - net (fo=1, routed) 0.890 0.506 lopt_1 - P2 OBUF (Prop_obuf_I_O) 1.245 1.750 r bcd_control_OBUF[10]_inst/O - net (fo=0) 0.000 1.750 bcd_control[10] - P2 r bcd_control[10] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][8]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[8] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.411ns (logic 1.409ns (58.455%) route 1.001ns (41.545%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.562 -0.525 data_memory/clk_out1 - SLICE_X44Y55 FDRE r data_memory/memory_data_reg[268435460][8]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X44Y55 FDRE (Prop_fdre_C_Q) 0.141 -0.384 r data_memory/memory_data_reg[268435460][8]_lopt_replica/Q - net (fo=1, routed) 1.001 0.617 lopt_10 - Y3 OBUF (Prop_obuf_I_O) 1.268 1.885 r bcd_control_OBUF[8]_inst/O - net (fo=0) 0.000 1.885 bcd_control[8] - Y3 r bcd_control[8] (OUT) + SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][2]_lopt_replica/Q + net (fo=1, routed) 0.973 0.619 lopt_4 + V5 OBUF (Prop_obuf_I_O) 1.228 1.847 r bcd_control_OBUF[2]_inst/O + net (fo=0) 0.000 1.847 bcd_control[2] + V5 r bcd_control[2] (OUT) ------------------------------------------------------------------- ------------------- @@ -2564,8 +2626,8 @@ Path Group: (none) From Clock: To Clock: clk_out1_phase_locked_loop -Max Delay 18132 Endpoints -Min Delay 18132 Endpoints +Max Delay 18130 Endpoints +Min Delay 18130 Endpoints -------------------------------------------------------------------------------------- @@ -2574,14 +2636,14 @@ Max Delay Paths Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435794][27]/R + Destination: data_memory/memory_data_reg[268435729][19]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 15.250ns (logic 1.650ns (10.818%) route 13.601ns (89.182%)) + Data Path Delay: 16.258ns (logic 1.650ns (10.148%) route 14.608ns (89.852%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.787ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.787ns + Clock Path Skew: -1.857ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.857ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2594,10 +2656,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=3, routed) 5.320 6.846 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X63Y38 LUT2 (Prop_lut2_I0_O) 0.124 6.970 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 8.280 15.250 data_memory/reset - SLICE_X1Y147 FDRE r data_memory/memory_data_reg[268435794][27]/R + net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 9.760 16.258 data_memory/reset + SLICE_X22Y148 FDRE r data_memory/memory_data_reg[268435729][19]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2610,17 +2672,353 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.684 -1.787 data_memory/clk_out1 - SLICE_X1Y147 FDRE r data_memory/memory_data_reg[268435794][27]/C + net (fo=18130, routed) 1.614 -1.857 data_memory/clk_out1 + SLICE_X22Y148 FDRE r data_memory/memory_data_reg[268435729][19]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435799][27]/R + Destination: data_memory/memory_data_reg[268435828][27]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 15.116ns (logic 1.650ns (10.914%) route 13.466ns (89.086%)) + Data Path Delay: 16.253ns (logic 1.650ns (10.150%) route 14.603ns (89.850%)) + Logic Levels: 2 (IBUF=1 LUT2=1) + Clock Path Skew: -1.857ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.857ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + B22 0.000 0.000 r hardware_reset (IN) + net (fo=0) 0.000 0.000 hardware_reset + B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O + net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 9.756 16.253 data_memory/reset + SLICE_X23Y148 FDRE r data_memory/memory_data_reg[268435828][27]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.614 -1.857 data_memory/clk_out1 + SLICE_X23Y148 FDRE r data_memory/memory_data_reg[268435828][27]/C + +Slack: inf + Source: hardware_reset + (input port) + Destination: data_memory/memory_data_reg[268435752][20]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 16.253ns (logic 1.650ns (10.151%) route 14.603ns (89.849%)) + Logic Levels: 2 (IBUF=1 LUT2=1) + Clock Path Skew: -1.857ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.857ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + B22 0.000 0.000 r hardware_reset (IN) + net (fo=0) 0.000 0.000 hardware_reset + B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O + net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 9.755 16.253 data_memory/reset + SLICE_X18Y146 FDRE r data_memory/memory_data_reg[268435752][20]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.614 -1.857 data_memory/clk_out1 + SLICE_X18Y146 FDRE r data_memory/memory_data_reg[268435752][20]/C + +Slack: inf + Source: hardware_reset + (input port) + Destination: data_memory/memory_data_reg[268435752][27]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 16.253ns (logic 1.650ns (10.151%) route 14.603ns (89.849%)) + Logic Levels: 2 (IBUF=1 LUT2=1) + Clock Path Skew: -1.857ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.857ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + B22 0.000 0.000 r hardware_reset (IN) + net (fo=0) 0.000 0.000 hardware_reset + B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O + net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 9.755 16.253 data_memory/reset + SLICE_X18Y146 FDRE r data_memory/memory_data_reg[268435752][27]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.614 -1.857 data_memory/clk_out1 + SLICE_X18Y146 FDRE r data_memory/memory_data_reg[268435752][27]/C + +Slack: inf + Source: hardware_reset + (input port) + Destination: data_memory/memory_data_reg[268435746][20]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 16.248ns (logic 1.650ns (10.153%) route 14.598ns (89.847%)) + Logic Levels: 2 (IBUF=1 LUT2=1) + Clock Path Skew: -1.857ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.857ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + B22 0.000 0.000 r hardware_reset (IN) + net (fo=0) 0.000 0.000 hardware_reset + B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O + net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 9.751 16.248 data_memory/reset + SLICE_X19Y146 FDRE r data_memory/memory_data_reg[268435746][20]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.614 -1.857 data_memory/clk_out1 + SLICE_X19Y146 FDRE r data_memory/memory_data_reg[268435746][20]/C + +Slack: inf + Source: hardware_reset + (input port) + Destination: data_memory/memory_data_reg[268435728][15]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 16.218ns (logic 1.650ns (10.172%) route 14.568ns (89.828%)) + Logic Levels: 2 (IBUF=1 LUT2=1) + Clock Path Skew: -1.856ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.856ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + B22 0.000 0.000 r hardware_reset (IN) + net (fo=0) 0.000 0.000 hardware_reset + B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O + net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 9.721 16.218 data_memory/reset + SLICE_X11Y145 FDRE r data_memory/memory_data_reg[268435728][15]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.615 -1.856 data_memory/clk_out1 + SLICE_X11Y145 FDRE r data_memory/memory_data_reg[268435728][15]/C + +Slack: inf + Source: hardware_reset + (input port) + Destination: data_memory/memory_data_reg[268435728][27]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 16.218ns (logic 1.650ns (10.172%) route 14.568ns (89.828%)) + Logic Levels: 2 (IBUF=1 LUT2=1) + Clock Path Skew: -1.856ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.856ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + B22 0.000 0.000 r hardware_reset (IN) + net (fo=0) 0.000 0.000 hardware_reset + B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O + net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 9.721 16.218 data_memory/reset + SLICE_X11Y145 FDRE r data_memory/memory_data_reg[268435728][27]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.615 -1.856 data_memory/clk_out1 + SLICE_X11Y145 FDRE r data_memory/memory_data_reg[268435728][27]/C + +Slack: inf + Source: hardware_reset + (input port) + Destination: data_memory/memory_data_reg[268435728][29]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 16.218ns (logic 1.650ns (10.172%) route 14.568ns (89.828%)) + Logic Levels: 2 (IBUF=1 LUT2=1) + Clock Path Skew: -1.856ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.856ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + B22 0.000 0.000 r hardware_reset (IN) + net (fo=0) 0.000 0.000 hardware_reset + B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O + net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 9.721 16.218 data_memory/reset + SLICE_X11Y145 FDRE r data_memory/memory_data_reg[268435728][29]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.615 -1.856 data_memory/clk_out1 + SLICE_X11Y145 FDRE r data_memory/memory_data_reg[268435728][29]/C + +Slack: inf + Source: hardware_reset + (input port) + Destination: data_memory/memory_data_reg[268435733][27]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 16.218ns (logic 1.650ns (10.172%) route 14.568ns (89.828%)) + Logic Levels: 2 (IBUF=1 LUT2=1) + Clock Path Skew: -1.856ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.856ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + B22 0.000 0.000 r hardware_reset (IN) + net (fo=0) 0.000 0.000 hardware_reset + B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O + net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 9.721 16.218 data_memory/reset + SLICE_X10Y145 FDRE r data_memory/memory_data_reg[268435733][27]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O + net (fo=18130, routed) 1.615 -1.856 data_memory/clk_out1 + SLICE_X10Y145 FDRE r data_memory/memory_data_reg[268435733][27]/C + +Slack: inf + Source: hardware_reset + (input port) + Destination: data_memory/memory_data_reg[268435757][29]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 16.075ns (logic 1.650ns (10.262%) route 14.426ns (89.738%)) Logic Levels: 2 (IBUF=1 LUT2=1) Clock Path Skew: -1.788ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.788ns @@ -2636,10 +3034,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=3, routed) 5.320 6.846 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X63Y38 LUT2 (Prop_lut2_I0_O) 0.124 6.970 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 8.146 15.116 data_memory/reset - SLICE_X0Y146 FDRE r data_memory/memory_data_reg[268435799][27]/R + net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 9.578 16.075 data_memory/reset + SLICE_X0Y146 FDRE r data_memory/memory_data_reg[268435757][29]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2652,344 +3050,8 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.683 -1.788 data_memory/clk_out1 - SLICE_X0Y146 FDRE r data_memory/memory_data_reg[268435799][27]/C - -Slack: inf - Source: hardware_reset - (input port) - Destination: data_memory/memory_data_reg[268435801][27]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 15.112ns (logic 1.650ns (10.917%) route 13.462ns (89.083%)) - Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.788ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.788ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - B22 0.000 0.000 r hardware_reset (IN) - net (fo=0) 0.000 0.000 hardware_reset - B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=3, routed) 5.320 6.846 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X63Y38 LUT2 (Prop_lut2_I0_O) 0.124 6.970 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 8.142 15.112 data_memory/reset - SLICE_X1Y146 FDRE r data_memory/memory_data_reg[268435801][27]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.683 -1.788 data_memory/clk_out1 - SLICE_X1Y146 FDRE r data_memory/memory_data_reg[268435801][27]/C - -Slack: inf - Source: hardware_reset - (input port) - Destination: data_memory/memory_data_reg[268435793][27]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 15.083ns (logic 1.650ns (10.938%) route 13.433ns (89.062%)) - Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.787ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.787ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - B22 0.000 0.000 r hardware_reset (IN) - net (fo=0) 0.000 0.000 hardware_reset - B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=3, routed) 5.320 6.846 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X63Y38 LUT2 (Prop_lut2_I0_O) 0.124 6.970 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 8.113 15.083 data_memory/reset - SLICE_X3Y147 FDRE r data_memory/memory_data_reg[268435793][27]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.684 -1.787 data_memory/clk_out1 - SLICE_X3Y147 FDRE r data_memory/memory_data_reg[268435793][27]/C - -Slack: inf - Source: hardware_reset - (input port) - Destination: data_memory/memory_data_reg[268435796][27]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 15.083ns (logic 1.650ns (10.938%) route 13.433ns (89.062%)) - Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.787ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.787ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - B22 0.000 0.000 r hardware_reset (IN) - net (fo=0) 0.000 0.000 hardware_reset - B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=3, routed) 5.320 6.846 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X63Y38 LUT2 (Prop_lut2_I0_O) 0.124 6.970 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 8.113 15.083 data_memory/reset - SLICE_X2Y147 FDRE r data_memory/memory_data_reg[268435796][27]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.684 -1.787 data_memory/clk_out1 - SLICE_X2Y147 FDRE r data_memory/memory_data_reg[268435796][27]/C - -Slack: inf - Source: hardware_reset - (input port) - Destination: data_memory/memory_data_reg[268435835][28]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 15.020ns (logic 1.650ns (10.983%) route 13.370ns (89.017%)) - Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.789ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.789ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - B22 0.000 0.000 r hardware_reset (IN) - net (fo=0) 0.000 0.000 hardware_reset - B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=3, routed) 5.320 6.846 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X63Y38 LUT2 (Prop_lut2_I0_O) 0.124 6.970 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 8.050 15.020 data_memory/reset - SLICE_X0Y142 FDRE r data_memory/memory_data_reg[268435835][28]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.682 -1.789 data_memory/clk_out1 - SLICE_X0Y142 FDRE r data_memory/memory_data_reg[268435835][28]/C - -Slack: inf - Source: hardware_reset - (input port) - Destination: data_memory/memory_data_reg[268435811][11]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 15.016ns (logic 1.650ns (10.987%) route 13.366ns (89.013%)) - Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.789ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.789ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - B22 0.000 0.000 r hardware_reset (IN) - net (fo=0) 0.000 0.000 hardware_reset - B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=3, routed) 5.320 6.846 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X63Y38 LUT2 (Prop_lut2_I0_O) 0.124 6.970 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 8.046 15.016 data_memory/reset - SLICE_X1Y142 FDRE r data_memory/memory_data_reg[268435811][11]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.682 -1.789 data_memory/clk_out1 - SLICE_X1Y142 FDRE r data_memory/memory_data_reg[268435811][11]/C - -Slack: inf - Source: hardware_reset - (input port) - Destination: data_memory/memory_data_reg[268435811][27]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 15.016ns (logic 1.650ns (10.987%) route 13.366ns (89.013%)) - Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.789ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.789ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - B22 0.000 0.000 r hardware_reset (IN) - net (fo=0) 0.000 0.000 hardware_reset - B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=3, routed) 5.320 6.846 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X63Y38 LUT2 (Prop_lut2_I0_O) 0.124 6.970 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 8.046 15.016 data_memory/reset - SLICE_X1Y142 FDRE r data_memory/memory_data_reg[268435811][27]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.682 -1.789 data_memory/clk_out1 - SLICE_X1Y142 FDRE r data_memory/memory_data_reg[268435811][27]/C - -Slack: inf - Source: hardware_reset - (input port) - Destination: data_memory/memory_data_reg[268435779][27]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 15.000ns (logic 1.650ns (10.998%) route 13.351ns (89.002%)) - Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.788ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.788ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - B22 0.000 0.000 r hardware_reset (IN) - net (fo=0) 0.000 0.000 hardware_reset - B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=3, routed) 5.320 6.846 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X63Y38 LUT2 (Prop_lut2_I0_O) 0.124 6.970 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 8.030 15.000 data_memory/reset - SLICE_X2Y143 FDRE r data_memory/memory_data_reg[268435779][27]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.683 -1.788 data_memory/clk_out1 - SLICE_X2Y143 FDRE r data_memory/memory_data_reg[268435779][27]/C - -Slack: inf - Source: hardware_reset - (input port) - Destination: data_memory/memory_data_reg[268435814][27]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 15.000ns (logic 1.650ns (10.998%) route 13.351ns (89.002%)) - Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.788ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.788ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - B22 0.000 0.000 r hardware_reset (IN) - net (fo=0) 0.000 0.000 hardware_reset - B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=3, routed) 5.320 6.846 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X63Y38 LUT2 (Prop_lut2_I0_O) 0.124 6.970 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 8.030 15.000 data_memory/reset - SLICE_X3Y143 FDRE r data_memory/memory_data_reg[268435814][27]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.683 -1.788 data_memory/clk_out1 - SLICE_X3Y143 FDRE r data_memory/memory_data_reg[268435814][27]/C + net (fo=18130, routed) 1.683 -1.788 data_memory/clk_out1 + SLICE_X0Y146 FDRE r data_memory/memory_data_reg[268435757][29]/C @@ -3000,11 +3062,11 @@ Min Delay Paths Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: memory_access/MEM_register_write_reg/R + Destination: data_memory/memory_data_reg[268435654][14]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.126ns (logic 0.045ns (3.996%) route 1.081ns (96.004%)) + Data Path Delay: 0.964ns (logic 0.045ns (4.670%) route 0.919ns (95.330%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3014,10 +3076,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=3, routed) 0.730 0.730 data_memory/locked - SLICE_X63Y38 LUT2 (Prop_lut2_I1_O) 0.045 0.775 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.351 1.126 memory_access/reset - SLICE_X59Y37 FDRE r memory_access/MEM_register_write_reg/R + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 0.525 0.964 data_memory/reset + SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435654][14]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3030,17 +3092,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.860 -0.266 memory_access/clk_out1 - SLICE_X59Y37 FDRE r memory_access/MEM_register_write_reg/C + net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435654][14]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: write_back/WB_register_write_destination_reg[3]_rep/R + Destination: data_memory/memory_data_reg[268435654][26]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.126ns (logic 0.045ns (3.996%) route 1.081ns (96.004%)) + Data Path Delay: 0.964ns (logic 0.045ns (4.670%) route 0.919ns (95.330%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3050,10 +3112,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=3, routed) 0.730 0.730 data_memory/locked - SLICE_X63Y38 LUT2 (Prop_lut2_I1_O) 0.045 0.775 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.351 1.126 write_back/reset - SLICE_X59Y37 FDRE r write_back/WB_register_write_destination_reg[3]_rep/R + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 0.525 0.964 data_memory/reset + SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435654][26]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3066,17 +3128,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.860 -0.266 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_destination_reg[3]_rep/C + net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435654][26]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: write_back/WB_register_write_destination_reg[3]_rep__0/R + Destination: data_memory/memory_data_reg[268435654][2]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.126ns (logic 0.045ns (3.996%) route 1.081ns (96.004%)) + Data Path Delay: 0.964ns (logic 0.045ns (4.670%) route 0.919ns (95.330%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3086,10 +3148,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=3, routed) 0.730 0.730 data_memory/locked - SLICE_X63Y38 LUT2 (Prop_lut2_I1_O) 0.045 0.775 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.351 1.126 write_back/reset - SLICE_X59Y37 FDRE r write_back/WB_register_write_destination_reg[3]_rep__0/R + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 0.525 0.964 data_memory/reset + SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435654][2]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3102,17 +3164,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.860 -0.266 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_destination_reg[3]_rep__0/C + net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435654][2]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: write_back/WB_register_write_destination_reg[4]/R + Destination: data_memory/memory_data_reg[268435661][14]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.126ns (logic 0.045ns (3.996%) route 1.081ns (96.004%)) + Data Path Delay: 0.964ns (logic 0.045ns (4.670%) route 0.919ns (95.330%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3122,10 +3184,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=3, routed) 0.730 0.730 data_memory/locked - SLICE_X63Y38 LUT2 (Prop_lut2_I1_O) 0.045 0.775 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.351 1.126 write_back/reset - SLICE_X59Y37 FDRE r write_back/WB_register_write_destination_reg[4]/R + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 0.525 0.964 data_memory/reset + SLICE_X64Y48 FDRE r data_memory/memory_data_reg[268435661][14]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3138,17 +3200,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.860 -0.266 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_destination_reg[4]/C + net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X64Y48 FDRE r data_memory/memory_data_reg[268435661][14]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: write_back/WB_register_write_reg/R + Destination: data_memory/memory_data_reg[268435652][14]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.126ns (logic 0.045ns (3.996%) route 1.081ns (96.004%)) + Data Path Delay: 1.024ns (logic 0.045ns (4.392%) route 0.979ns (95.608%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3158,10 +3220,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=3, routed) 0.730 0.730 data_memory/locked - SLICE_X63Y38 LUT2 (Prop_lut2_I1_O) 0.045 0.775 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.351 1.126 write_back/reset - SLICE_X59Y37 FDRE r write_back/WB_register_write_reg/R + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 0.586 1.024 data_memory/reset + SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435652][14]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3174,17 +3236,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.860 -0.266 write_back/clk_out1 - SLICE_X59Y37 FDRE r write_back/WB_register_write_reg/C + net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435652][14]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: memory_access/MEM_ALU_result_reg[0]/R + Destination: data_memory/memory_data_reg[268435652][26]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.132ns (logic 0.045ns (3.975%) route 1.087ns (96.025%)) + Data Path Delay: 1.024ns (logic 0.045ns (4.392%) route 0.979ns (95.608%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3194,10 +3256,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=3, routed) 0.730 0.730 data_memory/locked - SLICE_X63Y38 LUT2 (Prop_lut2_I1_O) 0.045 0.775 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.357 1.132 memory_access/reset - SLICE_X61Y32 FDRE r memory_access/MEM_ALU_result_reg[0]/R + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 0.586 1.024 data_memory/reset + SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435652][26]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3210,17 +3272,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.856 -0.270 memory_access/clk_out1 - SLICE_X61Y32 FDRE r memory_access/MEM_ALU_result_reg[0]/C + net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435652][26]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: instruction_decode/register_file/registers_reg[13][28]/R + Destination: data_memory/memory_data_reg[268435652][2]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.186ns (logic 0.045ns (3.796%) route 1.141ns (96.204%)) + Data Path Delay: 1.024ns (logic 0.045ns (4.392%) route 0.979ns (95.608%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3230,10 +3292,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=3, routed) 0.730 0.730 data_memory/locked - SLICE_X63Y38 LUT2 (Prop_lut2_I1_O) 0.045 0.775 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.411 1.186 instruction_decode/register_file/reset - SLICE_X63Y38 FDRE r instruction_decode/register_file/registers_reg[13][28]/R + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 0.586 1.024 data_memory/reset + SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435652][2]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3246,17 +3308,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.864 -0.262 instruction_decode/register_file/clk_out1 - SLICE_X63Y38 FDRE r instruction_decode/register_file/registers_reg[13][28]/C + net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435652][2]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: instruction_decode/register_file/registers_reg[8][28]/R + Destination: data_memory/memory_data_reg[268435656][26]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.190ns (logic 0.045ns (3.782%) route 1.145ns (96.218%)) + Data Path Delay: 1.024ns (logic 0.045ns (4.392%) route 0.979ns (95.608%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3266,10 +3328,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=3, routed) 0.730 0.730 data_memory/locked - SLICE_X63Y38 LUT2 (Prop_lut2_I1_O) 0.045 0.775 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.415 1.190 instruction_decode/register_file/reset - SLICE_X62Y38 FDRE r instruction_decode/register_file/registers_reg[8][28]/R + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 0.586 1.024 data_memory/reset + SLICE_X64Y49 FDRE r data_memory/memory_data_reg[268435656][26]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3282,17 +3344,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.864 -0.262 instruction_decode/register_file/clk_out1 - SLICE_X62Y38 FDRE r instruction_decode/register_file/registers_reg[8][28]/C + net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X64Y49 FDRE r data_memory/memory_data_reg[268435656][26]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: instruction_decode/register_file/registers_reg[9][10]/R + Destination: data_memory/memory_data_reg[268435652][19]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.223ns (logic 0.045ns (3.679%) route 1.178ns (96.321%)) + Data Path Delay: 1.042ns (logic 0.045ns (4.319%) route 0.997ns (95.681%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3302,10 +3364,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=3, routed) 0.730 0.730 data_memory/locked - SLICE_X63Y38 LUT2 (Prop_lut2_I1_O) 0.045 0.775 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.448 1.223 instruction_decode/register_file/reset - SLICE_X63Y39 FDRE r instruction_decode/register_file/registers_reg[9][10]/R + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 0.603 1.042 data_memory/reset + SLICE_X64Y55 FDRE r data_memory/memory_data_reg[268435652][19]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3318,17 +3380,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.864 -0.262 instruction_decode/register_file/clk_out1 - SLICE_X63Y39 FDRE r instruction_decode/register_file/registers_reg[9][10]/C + net (fo=18130, routed) 0.863 -0.262 data_memory/clk_out1 + SLICE_X64Y55 FDRE r data_memory/memory_data_reg[268435652][19]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: instruction_decode/register_file/registers_reg[12][10]/R + Destination: data_memory/memory_data_reg[268435710][15]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.228ns (logic 0.045ns (3.666%) route 1.183ns (96.334%)) + Data Path Delay: 1.049ns (logic 0.045ns (4.288%) route 1.004ns (95.712%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3338,10 +3400,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=3, routed) 0.730 0.730 data_memory/locked - SLICE_X63Y38 LUT2 (Prop_lut2_I1_O) 0.045 0.775 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.453 1.228 instruction_decode/register_file/reset - SLICE_X62Y39 FDRE r instruction_decode/register_file/registers_reg[12][10]/R + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17905, routed) 0.611 1.049 data_memory/reset + SLICE_X59Y44 FDRE r data_memory/memory_data_reg[268435710][15]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3354,8 +3416,8 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.864 -0.262 instruction_decode/register_file/clk_out1 - SLICE_X62Y39 FDRE r instruction_decode/register_file/registers_reg[12][10]/C + net (fo=18130, routed) 0.864 -0.262 data_memory/clk_out1 + SLICE_X59Y44 FDRE r data_memory/memory_data_reg[268435710][15]/C diff --git a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb index 6282d5b..58f10d7 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb and b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt index 6b2f2cd..e885dfc 100644 --- a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 00:10:49 2024 +| Date : Fri Jul 12 21:06:00 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb | Design : CPU @@ -32,13 +32,13 @@ Table of Contents +-------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------------+-------+-------+------------+-----------+-------+ -| Slice LUTs | 7991 | 0 | 0 | 20800 | 38.42 | -| LUT as Logic | 7991 | 0 | 0 | 20800 | 38.42 | +| Slice LUTs | 8003 | 0 | 0 | 20800 | 38.48 | +| LUT as Logic | 8003 | 0 | 0 | 20800 | 38.48 | | LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | -| Slice Registers | 18132 | 0 | 0 | 41600 | 43.59 | -| Register as Flip Flop | 18132 | 0 | 0 | 41600 | 43.59 | +| Slice Registers | 18130 | 0 | 0 | 41600 | 43.58 | +| Register as Flip Flop | 18130 | 0 | 0 | 41600 | 43.58 | | Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | -| F7 Muxes | 2352 | 0 | 0 | 16300 | 14.43 | +| F7 Muxes | 2426 | 0 | 0 | 16300 | 14.88 | | F8 Muxes | 1088 | 0 | 0 | 8150 | 13.35 | +-------------------------+-------+-------+------------+-----------+-------+ * Warning! LUT value is adjusted to account for LUT combining. @@ -59,7 +59,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 0 | Yes | Set | - | -| 18132 | Yes | Reset | - | +| 18130 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -69,21 +69,21 @@ Table of Contents +--------------------------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +--------------------------------------------+-------+-------+------------+-----------+-------+ -| Slice | 7679 | 0 | 0 | 8150 | 94.22 | -| SLICEL | 5398 | 0 | | | | -| SLICEM | 2281 | 0 | | | | -| LUT as Logic | 7991 | 0 | 0 | 20800 | 38.42 | +| Slice | 7420 | 0 | 0 | 8150 | 91.04 | +| SLICEL | 5250 | 0 | | | | +| SLICEM | 2170 | 0 | | | | +| LUT as Logic | 8003 | 0 | 0 | 20800 | 38.48 | | using O5 output only | 0 | | | | | -| using O6 output only | 7632 | | | | | -| using O5 and O6 | 359 | | | | | +| using O6 output only | 7624 | | | | | +| using O5 and O6 | 379 | | | | | | LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | | LUT as Distributed RAM | 0 | 0 | | | | | LUT as Shift Register | 0 | 0 | | | | -| Slice Registers | 18132 | 0 | 0 | 41600 | 43.59 | -| Register driven from within the Slice | 1317 | | | | | -| Register driven from outside the Slice | 16815 | | | | | -| LUT in front of the register is unused | 14690 | | | | | -| LUT in front of the register is used | 2125 | | | | | +| Slice Registers | 18130 | 0 | 0 | 41600 | 43.58 | +| Register driven from within the Slice | 1232 | | | | | +| Register driven from outside the Slice | 16898 | | | | | +| LUT in front of the register is unused | 14968 | | | | | +| LUT in front of the register is used | 1930 | | | | | | Unique Control Sets | 547 | | 0 | 8150 | 6.71 | +--------------------------------------------+-------+-------+------------+-----------+-------+ * * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. @@ -180,14 +180,14 @@ Table of Contents +-----------+-------+---------------------+ | Ref Name | Used | Functional Category | +-----------+-------+---------------------+ -| FDRE | 18132 | Flop & Latch | -| LUT6 | 6948 | LUT | -| MUXF7 | 2352 | MuxFx | +| FDRE | 18130 | Flop & Latch | +| LUT6 | 6947 | LUT | +| MUXF7 | 2426 | MuxFx | | MUXF8 | 1088 | MuxFx | -| LUT5 | 701 | LUT | -| LUT4 | 309 | LUT | -| LUT3 | 230 | LUT | -| LUT2 | 161 | LUT | +| LUT5 | 720 | LUT | +| LUT4 | 300 | LUT | +| LUT3 | 231 | LUT | +| LUT2 | 183 | LUT | | CARRY4 | 39 | CarryLogic | | OBUF | 13 | IO | | DSP48E1 | 3 | Block Arithmetic | diff --git a/PipelineProcessor.runs/impl_1/clockInfo.txt b/PipelineProcessor.runs/impl_1/clockInfo.txt index 4d7dbd0..0986769 100644 --- a/PipelineProcessor.runs/impl_1/clockInfo.txt +++ b/PipelineProcessor.runs/impl_1/clockInfo.txt @@ -1,6 +1,6 @@ ------------------------------------- | Tool Version : Vivado v.2023.2 -| Date : Fri Jul 12 00:10:23 2024 +| Date : Fri Jul 12 21:05:29 2024 | Host : Viviana | Design : design_1 | Device : xc7a35t-fgg484-1-- diff --git a/PipelineProcessor.runs/impl_1/init_design.pb b/PipelineProcessor.runs/impl_1/init_design.pb index cd9742d..55318cc 100644 Binary files a/PipelineProcessor.runs/impl_1/init_design.pb and b/PipelineProcessor.runs/impl_1/init_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/opt_design.pb b/PipelineProcessor.runs/impl_1/opt_design.pb index fccaa19..c1056ec 100644 Binary files a/PipelineProcessor.runs/impl_1/opt_design.pb and b/PipelineProcessor.runs/impl_1/opt_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/phys_opt_design.pb b/PipelineProcessor.runs/impl_1/phys_opt_design.pb index e9fd9aa..e90d8c3 100644 Binary files a/PipelineProcessor.runs/impl_1/phys_opt_design.pb and b/PipelineProcessor.runs/impl_1/phys_opt_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/place_design.pb b/PipelineProcessor.runs/impl_1/place_design.pb index d8046c0..0379dc1 100644 Binary files a/PipelineProcessor.runs/impl_1/place_design.pb and b/PipelineProcessor.runs/impl_1/place_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/route_design.pb b/PipelineProcessor.runs/impl_1/route_design.pb index 71e586f..e20edec 100644 Binary files a/PipelineProcessor.runs/impl_1/route_design.pb and b/PipelineProcessor.runs/impl_1/route_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/vivado.jou b/PipelineProcessor.runs/impl_1/vivado.jou index 04b6470..4bec96a 100644 --- a/PipelineProcessor.runs/impl_1/vivado.jou +++ b/PipelineProcessor.runs/impl_1/vivado.jou @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Fri Jul 12 00:09:58 2024 -# Process ID: 29956 +# Start of session at: Fri Jul 12 21:05:00 2024 +# Process ID: 22952 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1 # Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi diff --git a/PipelineProcessor.runs/impl_1/vivado.pb b/PipelineProcessor.runs/impl_1/vivado.pb index c8e9922..2352fc3 100644 Binary files a/PipelineProcessor.runs/impl_1/vivado.pb and b/PipelineProcessor.runs/impl_1/vivado.pb differ diff --git a/PipelineProcessor.runs/impl_1/write_bitstream.pb b/PipelineProcessor.runs/impl_1/write_bitstream.pb index b6cc42c..e2d4355 100644 Binary files a/PipelineProcessor.runs/impl_1/write_bitstream.pb and b/PipelineProcessor.runs/impl_1/write_bitstream.pb differ diff --git a/PipelineProcessor.runs/synth_1/CPU.dcp b/PipelineProcessor.runs/synth_1/CPU.dcp index e8da80d..f29ea0c 100644 Binary files a/PipelineProcessor.runs/synth_1/CPU.dcp and b/PipelineProcessor.runs/synth_1/CPU.dcp differ diff --git a/PipelineProcessor.runs/synth_1/CPU.vds b/PipelineProcessor.runs/synth_1/CPU.vds index aed6639..6fdef09 100644 --- a/PipelineProcessor.runs/synth_1/CPU.vds +++ b/PipelineProcessor.runs/synth_1/CPU.vds @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Fri Jul 12 00:08:43 2024 -# Process ID: 16484 +# Start of session at: Fri Jul 12 21:03:30 2024 +# Process ID: 19744 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1 # Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds @@ -12,6 +12,7 @@ # Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB #----------------------------------------------------------- source CPU.tcl -notrace +create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 462.926 ; gain = 182.984 Command: read_checkpoint -auto_incremental -incremental D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp INFO: [Vivado 12-5825] Read reference checkpoint from D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes @@ -24,13 +25,13 @@ INFO: [Designutils 20-5440] No compile time benefit to using incremental synthes INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 16380 +INFO: [Synth 8-7075] Helper process launched with PID 23648 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 1308.098 ; gain = 440.137 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 1306.855 ; gain = 438.977 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'CPU' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/CPU.v:2] -INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-16484-Viviana/realtime/phase_locked_loop_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-16484-Viviana/realtime/phase_locked_loop_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-19744-Viviana/realtime/phase_locked_loop_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-19744-Viviana/realtime/phase_locked_loop_stub.v:6] INFO: [Synth 8-6157] synthesizing module 'InstFetch' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstFetch.v:2] INFO: [Synth 8-6157] synthesizing module 'InstructionMemory' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3] INFO: [Synth 8-6155] done synthesizing module 'InstructionMemory' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3] @@ -65,18 +66,18 @@ WARNING: [Synth 8-7129] Port address[0] in module DataMemory is either unconnect WARNING: [Synth 8-7129] Port address[1] in module InstructionMemory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module InstructionMemory is either unconnected or has no load --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1475.660 ; gain = 607.699 +Finished RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1476.648 ; gain = 608.770 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1475.660 ; gain = 607.699 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1476.648 ; gain = 608.770 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1475.660 ; gain = 607.699 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1476.648 ; gain = 608.770 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.145 . Memory (MB): peak = 1475.660 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.173 . Memory (MB): peak = 1476.648 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints @@ -89,22 +90,22 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi Resolution: To avoid this warning, move constraints listed in [.Xil/CPU_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1581.605 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1584.652 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 1581.605 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1584.652 ; gain = 0.000 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 1581.605 ; gain = 713.645 +Finished Constraint Validation : Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.652 ; gain = 716.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tfgg484-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 1581.605 ; gain = 713.645 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.652 ; gain = 716.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints @@ -113,10 +114,10 @@ Applied set_property IO_BUFFER_TYPE = NONE for hardware_clk. (constraint file d Applied set_property CLOCK_BUFFER_TYPE = NONE for hardware_clk. (constraint file d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc, line 4). Applied set_property KEEP_HIERARCHY = SOFT for pll. (constraint file auto generated constraint). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 1581.605 ; gain = 713.645 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.652 ; gain = 716.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 1581.605 ; gain = 713.645 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:18 . Memory (MB): peak = 1584.652 ; gain = 716.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics @@ -140,7 +141,7 @@ Detailed RTL Component Info : 2 Input 5 Bit Muxes := 3 6 Input 5 Bit Muxes := 1 4 Input 5 Bit Muxes := 1 - 3 Input 2 Bit Muxes := 4 + 3 Input 2 Bit Muxes := 3 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 703 --------------------------------------------------------------------------------- @@ -172,7 +173,7 @@ DSP Report: Generating DSP alu/result0, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator alu/result0 is absorbed into DSP alu/result0. DSP Report: operator alu/result0 is absorbed into DSP alu/result0. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:32 . Memory (MB): peak = 1581.605 ; gain = 713.645 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:40 . Memory (MB): peak = 1584.652 ; gain = 716.773 --------------------------------------------------------------------------------- Sort Area is CPU__GC0 alu/result0_0 : 0 0 : 3101 5879 : Used 1 time 0 Sort Area is CPU__GC0 alu/result0_0 : 0 1 : 2778 5879 : Used 1 time 0 @@ -200,19 +201,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:38 . Memory (MB): peak = 1581.605 ; gain = 713.645 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:47 . Memory (MB): peak = 1584.652 ; gain = 716.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:45 . Memory (MB): peak = 1721.945 ; gain = 853.984 +Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:56 . Memory (MB): peak = 1761.211 ; gain = 893.332 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:50 . Memory (MB): peak = 1728.258 ; gain = 860.297 +Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:01:02 . Memory (MB): peak = 1767.527 ; gain = 899.648 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -230,37 +231,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:53 . Memory (MB): peak = 1728.258 ; gain = 860.297 +Finished IO Insertion : Time (s): cpu = 00:00:12 ; elapsed = 00:01:06 . Memory (MB): peak = 1767.527 ; gain = 899.648 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:54 . Memory (MB): peak = 1728.258 ; gain = 860.297 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:12 ; elapsed = 00:01:06 . Memory (MB): peak = 1767.527 ; gain = 899.648 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:55 . Memory (MB): peak = 1728.258 ; gain = 860.297 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:55 . Memory (MB): peak = 1728.258 ; gain = 860.297 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:55 . Memory (MB): peak = 1728.258 ; gain = 860.297 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:55 . Memory (MB): peak = 1728.258 ; gain = 860.297 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -290,40 +291,40 @@ Report Cell Usage: |1 |phase_locked_loop | 1| |2 |CARRY4 | 39| |3 |DSP48E1 | 3| -|4 |LUT1 | 5| -|5 |LUT2 | 161| -|6 |LUT3 | 230| -|7 |LUT4 | 309| -|8 |LUT5 | 701| -|9 |LUT6 | 6948| -|10 |MUXF7 | 2352| +|4 |LUT1 | 2| +|5 |LUT2 | 183| +|6 |LUT3 | 231| +|7 |LUT4 | 300| +|8 |LUT5 | 720| +|9 |LUT6 | 6947| +|10 |MUXF7 | 2426| |11 |MUXF8 | 1088| -|12 |FDRE | 18120| +|12 |FDRE | 18118| |13 |IBUF | 1| |14 |OBUF | 13| +------+------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:55 . Memory (MB): peak = 1728.258 ; gain = 860.297 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:53 . Memory (MB): peak = 1728.258 ; gain = 754.352 -Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:55 . Memory (MB): peak = 1728.258 ; gain = 860.297 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:01:05 . Memory (MB): peak = 1767.527 ; gain = 791.645 +Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.208 . Memory (MB): peak = 1728.258 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 3482 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.245 . Memory (MB): peak = 1767.527 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 3556 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1728.258 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1767.527 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Synth Design complete | Checksum: 83c65142 +Synth Design complete | Checksum: a3f3fba1 INFO: [Common 17-83] Releasing license: Synthesis 51 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:01:01 . Memory (MB): peak = 1728.258 ; gain = 1251.520 -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1728.258 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:01:15 . Memory (MB): peak = 1767.527 ; gain = 1293.230 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1767.527 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Jul 12 00:09:51 2024... +INFO: [Common 17-206] Exiting Vivado at Fri Jul 12 21:04:53 2024... diff --git a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb index 75c61bb..90c1ccf 100644 Binary files a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb and b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb differ diff --git a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt index 8e846a5..9379864 100644 --- a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt +++ b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 00:09:51 2024 +| Date : Fri Jul 12 21:04:53 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb | Design : CPU @@ -31,13 +31,13 @@ Table of Contents +-------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------------+-------+-------+------------+-----------+-------+ -| Slice LUTs* | 8036 | 0 | 0 | 20800 | 38.63 | -| LUT as Logic | 8036 | 0 | 0 | 20800 | 38.63 | +| Slice LUTs* | 8042 | 0 | 0 | 20800 | 38.66 | +| LUT as Logic | 8042 | 0 | 0 | 20800 | 38.66 | | LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | -| Slice Registers | 18120 | 0 | 0 | 41600 | 43.56 | -| Register as Flip Flop | 18120 | 0 | 0 | 41600 | 43.56 | +| Slice Registers | 18118 | 0 | 0 | 41600 | 43.55 | +| Register as Flip Flop | 18118 | 0 | 0 | 41600 | 43.55 | | Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | -| F7 Muxes | 2352 | 0 | 0 | 16300 | 14.43 | +| F7 Muxes | 2426 | 0 | 0 | 16300 | 14.88 | | F8 Muxes | 1088 | 0 | 0 | 8150 | 13.35 | +-------------------------+-------+-------+------------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -59,7 +59,7 @@ Warning! LUT value is adjusted to account for LUT combining. | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 0 | Yes | Set | - | -| 18120 | Yes | Reset | - | +| 18118 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -152,18 +152,18 @@ Warning! LUT value is adjusted to account for LUT combining. +----------+-------+---------------------+ | Ref Name | Used | Functional Category | +----------+-------+---------------------+ -| FDRE | 18120 | Flop & Latch | -| LUT6 | 6948 | LUT | -| MUXF7 | 2352 | MuxFx | +| FDRE | 18118 | Flop & Latch | +| LUT6 | 6947 | LUT | +| MUXF7 | 2426 | MuxFx | | MUXF8 | 1088 | MuxFx | -| LUT5 | 701 | LUT | -| LUT4 | 309 | LUT | -| LUT3 | 230 | LUT | -| LUT2 | 161 | LUT | +| LUT5 | 720 | LUT | +| LUT4 | 300 | LUT | +| LUT3 | 231 | LUT | +| LUT2 | 183 | LUT | | CARRY4 | 39 | CarryLogic | | OBUF | 13 | IO | -| LUT1 | 5 | LUT | | DSP48E1 | 3 | Block Arithmetic | +| LUT1 | 2 | LUT | | IBUF | 1 | IO | +----------+-------+---------------------+ diff --git a/PipelineProcessor.runs/synth_1/vivado.jou b/PipelineProcessor.runs/synth_1/vivado.jou index bbbe656..d2d90e9 100644 --- a/PipelineProcessor.runs/synth_1/vivado.jou +++ b/PipelineProcessor.runs/synth_1/vivado.jou @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Fri Jul 12 00:08:43 2024 -# Process ID: 16484 +# Start of session at: Fri Jul 12 21:03:30 2024 +# Process ID: 19744 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1 # Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds diff --git a/PipelineProcessor.runs/synth_1/vivado.pb b/PipelineProcessor.runs/synth_1/vivado.pb index 8f3b1b9..6b4e59c 100644 Binary files a/PipelineProcessor.runs/synth_1/vivado.pb and b/PipelineProcessor.runs/synth_1/vivado.pb differ diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem index f6e3925..c17d8c2 100644 Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem and b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem differ diff --git a/PipelineProcessor.srcs/sources_1/new/ControlUnit.v b/PipelineProcessor.srcs/sources_1/new/ControlUnit.v index 5f2a5c1..9be1000 100644 --- a/PipelineProcessor.srcs/sources_1/new/ControlUnit.v +++ b/PipelineProcessor.srcs/sources_1/new/ControlUnit.v @@ -67,10 +67,7 @@ module ControlUnit ( assign register_write_destination_source = (opcode == 6'h23 || opcode == 6'h8 || opcode == 6'h9 || opcode == 6'hc || opcode == 6'hd || opcode == 6'ha || - opcode == 6'hb || opcode == 6'hf || - (opcode == 6'h0 && - (funct == 6'h0 || funct == 6'h2 || - funct == 6'h3))) ? 0 : 1; + opcode == 6'hb || opcode == 6'hf) ? 0 : 1; assign extendop = (opcode == 6'hf) ? 2'b10 : (opcode == 6'hc || opcode == 6'hd) ? 2'b01 : 2'b00; endmodule diff --git a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v index e82d213..010d037 100644 --- a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v +++ b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v @@ -7,10 +7,257 @@ module InstructionMemory ( always @(*) begin case (address[31:2]) - 20'd0: instruction <= 32'h3c010000; - 20'd1: instruction <= 32'h3421fadd; - 20'd2: instruction <= 32'h00018020; - 20'd3: instruction <= 32'h08000003; + 20'd0: instruction <= 32'h3c1d4000; + 20'd1: instruction <= 32'h23bd07ff; + 20'd2: instruction <= 32'h3c104000; + 20'd3: instruction <= 32'h22100020; + 20'd4: instruction <= 32'h2011003f; + 20'd5: instruction <= 32'hae110000; + 20'd6: instruction <= 32'h20110006; + 20'd7: instruction <= 32'hae110004; + 20'd8: instruction <= 32'h2011005b; + 20'd9: instruction <= 32'hae110008; + 20'd10: instruction <= 32'h2011004f; + 20'd11: instruction <= 32'hae11000c; + 20'd12: instruction <= 32'h20110066; + 20'd13: instruction <= 32'hae110010; + 20'd14: instruction <= 32'h2011006d; + 20'd15: instruction <= 32'hae110014; + 20'd16: instruction <= 32'h2011007d; + 20'd17: instruction <= 32'hae110018; + 20'd18: instruction <= 32'h20110007; + 20'd19: instruction <= 32'hae11001c; + 20'd20: instruction <= 32'h2011007f; + 20'd21: instruction <= 32'hae110020; + 20'd22: instruction <= 32'h2011006f; + 20'd23: instruction <= 32'hae110024; + 20'd24: instruction <= 32'h20110077; + 20'd25: instruction <= 32'hae110028; + 20'd26: instruction <= 32'h2011007c; + 20'd27: instruction <= 32'hae11002c; + 20'd28: instruction <= 32'h20110058; + 20'd29: instruction <= 32'hae110030; + 20'd30: instruction <= 32'h2011005e; + 20'd31: instruction <= 32'hae110034; + 20'd32: instruction <= 32'h20110079; + 20'd33: instruction <= 32'hae110038; + 20'd34: instruction <= 32'h20110071; + 20'd35: instruction <= 32'hae11003c; + 20'd36: instruction <= 32'h3c104000; + 20'd37: instruction <= 32'h22100060; + 20'd38: instruction <= 32'h20114b8d; + 20'd39: instruction <= 32'hae110000; + 20'd40: instruction <= 32'h20112307; + 20'd41: instruction <= 32'hae110004; + 20'd42: instruction <= 32'h3c010000; + 20'd43: instruction <= 32'h3421fae0; + 20'd44: instruction <= 32'h00018820; + 20'd45: instruction <= 32'hae110008; + 20'd46: instruction <= 32'h20117815; + 20'd47: instruction <= 32'hae11000c; + 20'd48: instruction <= 32'h3c010000; + 20'd49: instruction <= 32'h3421c105; + 20'd50: instruction <= 32'h00018820; + 20'd51: instruction <= 32'hae110010; + 20'd52: instruction <= 32'h3c010000; + 20'd53: instruction <= 32'h342184f0; + 20'd54: instruction <= 32'h00018820; + 20'd55: instruction <= 32'hae110014; + 20'd56: instruction <= 32'h20110db6; + 20'd57: instruction <= 32'hae110018; + 20'd58: instruction <= 32'h3c010000; + 20'd59: instruction <= 32'h3421f21d; + 20'd60: instruction <= 32'h00018820; + 20'd61: instruction <= 32'hae11001c; + 20'd62: instruction <= 32'h3c010000; + 20'd63: instruction <= 32'h3421e97a; + 20'd64: instruction <= 32'h00018820; + 20'd65: instruction <= 32'hae110020; + 20'd66: instruction <= 32'h3c010000; + 20'd67: instruction <= 32'h3421a3b6; + 20'd68: instruction <= 32'h00018820; + 20'd69: instruction <= 32'hae110024; + 20'd70: instruction <= 32'h3c010000; + 20'd71: instruction <= 32'h34218466; + 20'd72: instruction <= 32'h00018820; + 20'd73: instruction <= 32'hae110028; + 20'd74: instruction <= 32'h20113a25; + 20'd75: instruction <= 32'hae11002c; + 20'd76: instruction <= 32'h201105df; + 20'd77: instruction <= 32'hae110030; + 20'd78: instruction <= 32'h3c010000; + 20'd79: instruction <= 32'h3421d2de; + 20'd80: instruction <= 32'h00018820; + 20'd81: instruction <= 32'hae110034; + 20'd82: instruction <= 32'h3c010000; + 20'd83: instruction <= 32'h3421ba7a; + 20'd84: instruction <= 32'h00018820; + 20'd85: instruction <= 32'hae110038; + 20'd86: instruction <= 32'h20117809; + 20'd87: instruction <= 32'hae11003c; + 20'd88: instruction <= 32'h3c010000; + 20'd89: instruction <= 32'h3421f6a8; + 20'd90: instruction <= 32'h00018820; + 20'd91: instruction <= 32'hae110040; + 20'd92: instruction <= 32'h2011361d; + 20'd93: instruction <= 32'hae110044; + 20'd94: instruction <= 32'h20113adb; + 20'd95: instruction <= 32'hae110048; + 20'd96: instruction <= 32'h3c010000; + 20'd97: instruction <= 32'h3421969a; + 20'd98: instruction <= 32'h00018820; + 20'd99: instruction <= 32'hae11004c; + 20'd100: instruction <= 32'h20040014; + 20'd101: instruction <= 32'h0c0000a6; + 20'd102: instruction <= 32'h3c104000; + 20'd103: instruction <= 32'h22110010; + 20'd104: instruction <= 32'h22100060; + 20'd105: instruction <= 32'h20120000; + 20'd106: instruction <= 32'h20130014; + 20'd107: instruction <= 32'h00124080; + 20'd108: instruction <= 32'h02084020; + 20'd109: instruction <= 32'h8d040000; + 20'd110: instruction <= 32'h22250000; + 20'd111: instruction <= 32'h0c000075; + 20'd112: instruction <= 32'h22520001; + 20'd113: instruction <= 32'h02724022; + 20'd114: instruction <= 32'h1d00fff8; + 20'd115: instruction <= 32'h0c00009f; + 20'd116: instruction <= 32'h08000069; + 20'd117: instruction <= 32'h23bdffe0; + 20'd118: instruction <= 32'hafbf0004; + 20'd119: instruction <= 32'hafb00008; + 20'd120: instruction <= 32'hafb1000c; + 20'd121: instruction <= 32'hafb20010; + 20'd122: instruction <= 32'hafb30014; + 20'd123: instruction <= 32'hafb40018; + 20'd124: instruction <= 32'hafb5001c; + 20'd125: instruction <= 32'hafb60020; + 20'd126: instruction <= 32'h20900000; + 20'd127: instruction <= 32'h20b10000; + 20'd128: instruction <= 32'h3c124000; + 20'd129: instruction <= 32'h22520020; + 20'd130: instruction <= 32'h20130be2; + 20'd131: instruction <= 32'h22140000; + 20'd132: instruction <= 32'h20160100; + 20'd133: instruction <= 32'h20150004; + 20'd134: instruction <= 32'h3288000f; + 20'd135: instruction <= 32'h00084080; + 20'd136: instruction <= 32'h02484020; + 20'd137: instruction <= 32'h8d080000; + 20'd138: instruction <= 32'h01164025; + 20'd139: instruction <= 32'hae280000; + 20'd140: instruction <= 32'h0014a102; + 20'd141: instruction <= 32'h0016b040; + 20'd142: instruction <= 32'h20080400; + 20'd143: instruction <= 32'h2108ffff; + 20'd144: instruction <= 32'h1d00fffe; + 20'd145: instruction <= 32'h22b5ffff; + 20'd146: instruction <= 32'h1ea0fff3; + 20'd147: instruction <= 32'h2273ffff; + 20'd148: instruction <= 32'h1e60ffee; + 20'd149: instruction <= 32'h8fbf0004; + 20'd150: instruction <= 32'h8fb00008; + 20'd151: instruction <= 32'h8fb1000c; + 20'd152: instruction <= 32'h8fb20010; + 20'd153: instruction <= 32'h8fb30014; + 20'd154: instruction <= 32'h8fb40018; + 20'd155: instruction <= 32'h8fb5001c; + 20'd156: instruction <= 32'h8fb60020; + 20'd157: instruction <= 32'h23bd0020; + 20'd158: instruction <= 32'h03e00008; + 20'd159: instruction <= 32'h3c084000; + 20'd160: instruction <= 32'h21080010; + 20'd161: instruction <= 32'had000000; + 20'd162: instruction <= 32'h3c080100; + 20'd163: instruction <= 32'h2108ffff; + 20'd164: instruction <= 32'h1d00fffe; + 20'd165: instruction <= 32'h03e00008; + 20'd166: instruction <= 32'h23bdfff4; + 20'd167: instruction <= 32'hafbf0004; + 20'd168: instruction <= 32'hafb00008; + 20'd169: instruction <= 32'hafb1000c; + 20'd170: instruction <= 32'h20900000; + 20'd171: instruction <= 32'h20110001; + 20'd172: instruction <= 32'h02114022; + 20'd173: instruction <= 32'h19000009; + 20'd174: instruction <= 32'h24040000; + 20'd175: instruction <= 32'h2225ffff; + 20'd176: instruction <= 32'h00113021; + 20'd177: instruction <= 32'h0c0000bc; + 20'd178: instruction <= 32'h00022021; + 20'd179: instruction <= 32'h00112821; + 20'd180: instruction <= 32'h0c0000e1; + 20'd181: instruction <= 32'h22310001; + 20'd182: instruction <= 32'h080000ac; + 20'd183: instruction <= 32'h8fbf0004; + 20'd184: instruction <= 32'h8fb00008; + 20'd185: instruction <= 32'h8fb1000c; + 20'd186: instruction <= 32'h23bd000c; + 20'd187: instruction <= 32'h03e00008; + 20'd188: instruction <= 32'h23bdffec; + 20'd189: instruction <= 32'hafb00004; + 20'd190: instruction <= 32'hafb10008; + 20'd191: instruction <= 32'hafb2000c; + 20'd192: instruction <= 32'hafb30010; + 20'd193: instruction <= 32'hafbf0014; + 20'd194: instruction <= 32'h00854022; + 20'd195: instruction <= 32'h19000002; + 20'd196: instruction <= 32'h00801020; + 20'd197: instruction <= 32'h080000da; + 20'd198: instruction <= 32'h00048021; + 20'd199: instruction <= 32'h00058821; + 20'd200: instruction <= 32'h00069021; + 20'd201: instruction <= 32'h02119820; + 20'd202: instruction <= 32'h00139842; + 20'd203: instruction <= 32'h3c084000; + 20'd204: instruction <= 32'h21080060; + 20'd205: instruction <= 32'h00134880; + 20'd206: instruction <= 32'h01284820; + 20'd207: instruction <= 32'h8d290000; + 20'd208: instruction <= 32'h00125080; + 20'd209: instruction <= 32'h01485020; + 20'd210: instruction <= 32'h8d4a0000; + 20'd211: instruction <= 32'h012a4022; + 20'd212: instruction <= 32'h19000003; + 20'd213: instruction <= 32'h2265ffff; + 20'd214: instruction <= 32'h0c0000bc; + 20'd215: instruction <= 32'h080000da; + 20'd216: instruction <= 32'h22640001; + 20'd217: instruction <= 32'h0c0000bc; + 20'd218: instruction <= 32'h8fb00004; + 20'd219: instruction <= 32'h8fb10008; + 20'd220: instruction <= 32'h8fb2000c; + 20'd221: instruction <= 32'h8fb30010; + 20'd222: instruction <= 32'h8fbf0014; + 20'd223: instruction <= 32'h23bd0014; + 20'd224: instruction <= 32'h03e00008; + 20'd225: instruction <= 32'h23bdfff4; + 20'd226: instruction <= 32'hafb00004; + 20'd227: instruction <= 32'hafb10008; + 20'd228: instruction <= 32'hafbf000c; + 20'd229: instruction <= 32'h3c104000; + 20'd230: instruction <= 32'h22100060; + 20'd231: instruction <= 32'h00054080; + 20'd232: instruction <= 32'h02089020; + 20'd233: instruction <= 32'h8e520000; + 20'd234: instruction <= 32'h20b1ffff; + 20'd235: instruction <= 32'h02244022; + 20'd236: instruction <= 32'h05000006; + 20'd237: instruction <= 32'h00114080; + 20'd238: instruction <= 32'h02084020; + 20'd239: instruction <= 32'h8d090000; + 20'd240: instruction <= 32'had090004; + 20'd241: instruction <= 32'h2231ffff; + 20'd242: instruction <= 32'h080000eb; + 20'd243: instruction <= 32'h00044080; + 20'd244: instruction <= 32'h02084020; + 20'd245: instruction <= 32'had120000; + 20'd246: instruction <= 32'h8fb00004; + 20'd247: instruction <= 32'h8fb10008; + 20'd248: instruction <= 32'h8fbf000c; + 20'd249: instruction <= 32'h23bd000c; + 20'd250: instruction <= 32'h03e00008; default: instruction <= 32'h00000000; endcase end diff --git a/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp b/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp index 80f15c0..a18d6fc 100644 Binary files a/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp and b/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp differ diff --git a/PipelineProcessor.xpr b/PipelineProcessor.xpr index 751de98..6e63286 100644 --- a/PipelineProcessor.xpr +++ b/PipelineProcessor.xpr @@ -60,7 +60,7 @@