diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
index 6a5d976..ae917a3 100644
Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem and b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem differ
diff --git a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
index 2745533..46665bb 100644
--- a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
+++ b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
@@ -7,21 +7,26 @@ module InstructionMemory (
always @(*) begin
case (address[31:2])
- 20'd0: instruction <= 32'h20110001; // addi $s1, $zero, 1
+ 20'd0: instruction <= 32'h20110002; // addi $s1, $zero, 2
20'd1: instruction <= 32'h00000000;
20'd2: instruction <= 32'h00000000;
20'd3: instruction <= 32'h00000000;
20'd4: instruction <= 32'h00000000;
- 20'd5: instruction <= 32'h0c000007; // jal func
- // end:
- 20'd6: instruction <= 32'h08000006; // j end
- // func:
- 20'd7: instruction <= 32'h20120002; // addi $s2, $zero, 2
+ 20'd5: instruction <= 32'h20120050; // addi $s2, $zero, 0x50
+ 20'd6: instruction <= 32'h00000000;
+ 20'd7: instruction <= 32'h00000000;
20'd8: instruction <= 32'h00000000;
20'd9: instruction <= 32'h00000000;
- 20'd10: instruction <= 32'h00000000;
- 20'd11: instruction <= 32'h00000000;
- 20'd12: instruction <= 32'h03e00008; // jr $ra
+ 20'd10: instruction <= 32'h02408009; // jalr $s2, $s0
+ // end:
+ 20'd11: instruction <= 32'h0800000b; // j end
+ // Note the address
+ 20'd20: instruction <= 32'h20130003; // addi $s3, $zero, 3
+ 20'd21: instruction <= 32'h00000000;
+ 20'd22: instruction <= 32'h00000000;
+ 20'd23: instruction <= 32'h00000000;
+ 20'd24: instruction <= 32'h00000000;
+ 20'd25: instruction <= 32'h02000008; // jr $s0
default: instruction <= 32'h00000000;
endcase
end
diff --git a/PipelineProcessor.xpr b/PipelineProcessor.xpr
index eb0c989..3b3f391 100644
--- a/PipelineProcessor.xpr
+++ b/PipelineProcessor.xpr
@@ -60,7 +60,7 @@
-
+