diff --git a/PipelineProcessor.runs/impl_1/CPU.vdi b/PipelineProcessor.runs/impl_1/CPU.vdi index edc8397..25e0b58 100644 --- a/PipelineProcessor.runs/impl_1/CPU.vdi +++ b/PipelineProcessor.runs/impl_1/CPU.vdi @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Fri Jul 12 21:05:00 2024 -# Process ID: 22952 +# Start of session at: Sat Jul 13 14:27:36 2024 +# Process ID: 19592 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1 # Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi @@ -12,14 +12,14 @@ # Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB #----------------------------------------------------------- source CPU.tcl -notrace -create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 464.035 ; gain = 185.215 +create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 462.727 ; gain = 184.750 Command: link_design -top CPU -part xc7a35tfgg484-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7a35tfgg484-1 INFO: [Project 1-454] Reading design checkpoint 'd:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp' for cell 'pll' -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.112 . Memory (MB): peak = 915.762 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 3557 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.175 . Memory (MB): peak = 915.922 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 3504 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.2 INFO: [Project 1-570] Preparing netlist for logic optimization @@ -28,18 +28,18 @@ Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/Pipelin Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54] INFO: [Timing 38-2] Deriving generated clocks [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54] -get_clocks: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1598.367 ; gain = 557.914 +get_clocks: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 1598.910 ; gain = 559.754 Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst' Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc] Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1598.367 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1598.910 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 1598.367 ; gain = 1120.484 +link_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 1598.910 ; gain = 1122.715 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' @@ -50,111 +50,112 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.645 . Memory (MB): peak = 1598.367 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1598.910 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 16cb45a4f +Ending Cache Timing Information Task | Checksum: 144775da6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.434 . Memory (MB): peak = 1612.133 ; gain = 13.766 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.821 . Memory (MB): peak = 1613.023 ; gain = 14.113 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup -Phase 1.1 Core Generation And Design Setup | Checksum: 16cb45a4f +Phase 1.1 Core Generation And Design Setup | Checksum: 144775da6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.844 ; gain = 0.000 Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 16cb45a4f +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 144775da6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Phase 1 Initialization | Checksum: 16cb45a4f +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Phase 1 Initialization | Checksum: 144775da6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1972.844 ; gain = 0.000 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 16cb45a4f +Phase 2.1 Timer Update | Checksum: 144775da6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.355 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.617 . Memory (MB): peak = 1972.844 ; gain = 0.000 Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 16cb45a4f +Phase 2.2 Timing Data Collection | Checksum: 144775da6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.379 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Phase 2 Timer Update And Timing Data Collection | Checksum: 16cb45a4f +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.640 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Phase 2 Timer Update And Timing Data Collection | Checksum: 144775da6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.380 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.642 . Memory (MB): peak = 1972.844 ; gain = 0.000 Phase 3 Retarget +INFO: [Opt 31-1566] Pulled 13 inverters resulting in an inversion of 263 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: 192618621 +Phase 3 Retarget | Checksum: 17395c2ed -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.517 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Retarget | Checksum: 192618621 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.901 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Retarget | Checksum: 17395c2ed +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 14 cells INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: 20b011990 +Phase 4 Constant propagation | Checksum: 1c089ccf4 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.606 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Constant propagation | Checksum: 20b011990 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Constant propagation | Checksum: 1c089ccf4 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep -Phase 5 Sweep | Checksum: 1bc044ae4 +Phase 5 Sweep | Checksum: 12eb909f8 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Sweep | Checksum: 1bc044ae4 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Sweep | Checksum: 12eb909f8 INFO: [Opt 31-389] Phase Sweep created 12 cells and removed 0 cells Phase 6 BUFG optimization -Phase 6 BUFG optimization | Checksum: 1bc044ae4 +Phase 6 BUFG optimization | Checksum: 12eb909f8 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.864 . Memory (MB): peak = 1980.477 ; gain = 0.000 -BUFG optimization | Checksum: 1bc044ae4 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000 +BUFG optimization | Checksum: 12eb909f8 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: 1bc044ae4 +Phase 7 Shift Register Optimization | Checksum: 12eb909f8 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.875 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Shift Register Optimization | Checksum: 1bc044ae4 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Shift Register Optimization | Checksum: 12eb909f8 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: 24e91c234 +Phase 8 Post Processing Netlist | Checksum: 17562fe4e -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.902 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Post Processing Netlist | Checksum: 24e91c234 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Post Processing Netlist | Checksum: 17562fe4e INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 14de2f7bb +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1329e1c39 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Phase 9.2 Verifying Netlist Connectivity | Checksum: 14de2f7bb +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Phase 9.2 Verifying Netlist Connectivity | Checksum: 1329e1c39 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Phase 9 Finalization | Checksum: 14de2f7bb +Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Phase 9 Finalization | Checksum: 1329e1c39 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000 Opt_design Change Summary ========================= @@ -162,7 +163,7 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 1 | 1 | +| Retarget | 0 | 14 | 1 | | Constant propagation | 0 | 0 | 0 | | Sweep | 12 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | @@ -171,31 +172,32 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- -Ending Logic Optimization Task | Checksum: 14de2f7bb +Ending Logic Optimization Task | Checksum: 1329e1c39 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1972.844 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 14de2f7bb +Ending Power Optimization Task | Checksum: 1329e1c39 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1972.844 ; gain = 0.000 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 14de2f7bb +Ending Final Cleanup Task | Checksum: 1329e1c39 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.844 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 14de2f7bb +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 1329e1c39 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1972.844 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation -29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully +opt_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 1972.844 ; gain = 373.934 INFO: [runtcl-4] Executing : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx Command: report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. @@ -203,16 +205,16 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt. report_drc completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1972.844 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1972.844 ; gain = 0.000 Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1972.844 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_opt.dcp' has been generated. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -232,59 +234,59 @@ Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11b2d87cf +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9a573811 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1980.477 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.844 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e3d58ae7 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 161645cda -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 1db20e775 +Phase 1.3 Build Placer Netlist Model | Checksum: 254135206 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 1db20e775 +Phase 1.4 Constrain Clocks/Macros | Checksum: 254135206 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2032.707 ; gain = 52.230 -Phase 1 Placer Initialization | Checksum: 1db20e775 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Phase 1 Placer Initialization | Checksum: 254135206 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 2 Global Placement Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 156b1aef4 +Phase 2.1 Floorplanning | Checksum: 21edfd7da -Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1d86be86e +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 187f6e72f -Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 2.3 Post-Processing in Floorplanning -Phase 2.3 Post-Processing in Floorplanning | Checksum: 1d86be86e +Phase 2.3 Post-Processing in Floorplanning | Checksum: 187f6e72f -Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis -Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1400d07dd +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 2bcb2d97a -Time (s): cpu = 00:00:03 ; elapsed = 00:00:10 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 2.4.2 Physical Synthesis In Placer -INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 78 LUT instances to create LUTNM shape +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 61 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 -INFO: [Physopt 32-1138] End 1 Pass. Optimized 37 nets or LUTs. Breaked 0 LUT, combined 37 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-1138] End 1 Pass. Optimized 29 nets or LUTs. Breaked 0 LUT, combined 29 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell @@ -295,7 +297,7 @@ INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2032.707 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2040.230 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ @@ -304,7 +306,7 @@ Summary of Physical Synthesis Optimizations ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- -| LUT Combining | 0 | 37 | 37 | 0 | 1 | 00:00:00 | +| LUT Combining | 0 | 29 | 29 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | @@ -313,59 +315,59 @@ Summary of Physical Synthesis Optimizations | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 37 | 37 | 0 | 4 | 00:00:00 | +| Total | 0 | 29 | 29 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- -Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1f5974df5 +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1cd490dfe -Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 2032.707 ; gain = 52.230 -Phase 2.4 Global Placement Core | Checksum: 15c812e1b +Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Phase 2.4 Global Placement Core | Checksum: 2593ef06b -Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 2032.707 ; gain = 52.230 -Phase 2 Global Placement | Checksum: 15c812e1b +Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Phase 2 Global Placement | Checksum: 2593ef06b -Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1da65e99f +Phase 3.1 Commit Multi Column Macros | Checksum: 24c2e5196 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:13 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d55c087b +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b29cdebe -Time (s): cpu = 00:00:04 ; elapsed = 00:00:14 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 1214d70ca +Phase 3.3 Area Swap Optimization | Checksum: 1fd1f47c3 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:14 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 174ca9207 +Phase 3.4 Pipeline Register Optimization | Checksum: 1bbf6b047 -Time (s): cpu = 00:00:05 ; elapsed = 00:00:14 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 1eb9f62f7 +Phase 3.5 Small Shape Detail Placement | Checksum: 1f0217d20 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:28 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:26 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 1badb8766 +Phase 3.6 Re-assign LUT pins | Checksum: 149d47d39 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 1ad982255 +Phase 3.7 Pipeline Register Optimization | Checksum: 14f4d2963 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2032.707 ; gain = 52.230 -Phase 3 Detail Placement | Checksum: 1ad982255 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Phase 3 Detail Placement | Checksum: 14f4d2963 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2032.707 ; gain = 52.230 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 2040.230 ; gain = 67.387 Phase 4 Post Placement Optimization and Clean-Up @@ -373,7 +375,7 @@ Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 25abda1d4 +Post Placement Optimization Initialization | Checksum: 1b9a7b723 Phase 4.1.1.1 BUFG Insertion @@ -381,34 +383,34 @@ Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.540 | TNS=0.000 | -Phase 1 Physical Synthesis Initialization | Checksum: 1a16c95e6 +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.040 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 19276cbb6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.702 . Memory (MB): peak = 2079.688 ; gain = 10.484 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.744 . Memory (MB): peak = 2088.574 ; gain = 13.941 INFO: [Place 46-33] Processed net data_memory/reset, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. -Ending Physical Synthesis Task | Checksum: 1a16c95e6 +Ending Physical Synthesis Task | Checksum: 19276cbb6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2081.648 ; gain = 12.445 -Phase 4.1.1.1 BUFG Insertion | Checksum: 25abda1d4 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2090.840 ; gain = 16.207 +Phase 4.1.1.1 BUFG Insertion | Checksum: 1b9a7b723 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 +Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996 Phase 4.1.1.2 Post Placement Timing Optimization -INFO: [Place 30-746] Post Placement Timing Summary WNS=1.540. For the most accurate timing information please run report_timing. -Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 189e73d35 +INFO: [Place 30-746] Post Placement Timing Summary WNS=2.040. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1b853f6e8 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 +Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 -Phase 4.1 Post Commit Optimization | Checksum: 189e73d35 +Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996 +Phase 4.1 Post Commit Optimization | Checksum: 1b853f6e8 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 +Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 189e73d35 +Phase 4.2 Post Placement Cleanup | Checksum: 1b853f6e8 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680 Phase 4.3 Placer Reporting @@ -418,7 +420,7 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| -| North| 2x2| 2x2| +| North| 4x4| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| @@ -427,42 +429,42 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion | West| 1x1| 1x1| |___________|___________________|___________________| -Phase 4.3.1 Print Estimated Congestion | Checksum: 189e73d35 +Phase 4.3.1 Print Estimated Congestion | Checksum: 1b853f6e8 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 -Phase 4.3 Placer Reporting | Checksum: 189e73d35 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680 +Phase 4.3 Placer Reporting | Checksum: 1b853f6e8 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2081.648 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2091.523 ; gain = 0.000 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: d7614f21 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 10fcc6d31 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 -Ending Placer Task | Checksum: bc3137e6 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680 +Ending Placer Task | Checksum: 51a85dd7 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172 -65 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680 +66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:35 . Memory (MB): peak = 2081.648 ; gain = 101.172 +place_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.523 ; gain = 118.680 INFO: [runtcl-4] Executing : report_io -file CPU_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 2081.648 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 2091.523 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 2081.648 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 2091.523 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 2096.543 ; gain = 1.004 -Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.543 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2096.543 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 2106.918 ; gain = 1.973 +Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2106.918 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2106.918 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2096.543 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 2096.543 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2096.543 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.543 ; gain = 1.004 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2106.918 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2106.918 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2106.918 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2106.918 ; gain = 1.973 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_placed.dcp' has been generated. Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -470,23 +472,23 @@ INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc Starting Initial Update Timing Task -Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2143.457 ; gain = 46.914 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2153.953 ; gain = 47.035 INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation -74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +75 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2168.809 ; gain = 7.066 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2169.680 ; gain = 0.871 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2169.680 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2179.293 ; gain = 7.062 +Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2179.293 ; gain = 7.062 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2179.293 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 2169.680 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 2169.680 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2169.680 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2169.680 ; gain = 7.938 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2179.293 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 2179.293 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2179.293 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2179.293 ; gain = 7.062 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -501,30 +503,30 @@ Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design -Checksum: PlaceDB: 835e865f ConstDB: 0 ShapeSum: 38d2b187 RouteDB: 0 -Post Restoration Checksum: NetGraph: 3533f183 | NumContArr: bffdc8ea | Constraints: c2a8fa9d | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 27a83afa7 +Checksum: PlaceDB: 4fa4d64c ConstDB: 0 ShapeSum: 203878b RouteDB: 0 +Post Restoration Checksum: NetGraph: c8a283dc | NumContArr: aad6ec74 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 2f8cb658a -Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 2287.406 ; gain = 85.613 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2289.805 ; gain = 79.008 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 27a83afa7 +Phase 2.1 Fix Topology Constraints | Checksum: 2f8cb658a -Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 2287.414 ; gain = 85.621 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2289.805 ; gain = 79.008 Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 27a83afa7 +Phase 2.2 Pre Route Cleanup | Checksum: 2f8cb658a -Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 2287.414 ; gain = 85.621 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2289.805 ; gain = 79.008 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing -Phase 2.3 Update Timing | Checksum: 17a8d6394 +Phase 2.3 Update Timing | Checksum: 201a59748 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:18 . Memory (MB): peak = 2305.191 ; gain = 103.398 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.776 | TNS=0.000 | WHS=-0.119 | THS=-29.698| +Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 2307.527 ; gain = 96.730 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.230 | TNS=0.000 | WHS=-0.144 | THS=-28.052| Router Utilization Summary @@ -533,86 +535,93 @@ Router Utilization Summary Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. - Number of Failed Nets = 21867 + Number of Failed Nets = 21997 (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 21867 + Number of Unrouted Nets = 21997 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 2 Router Initialization | Checksum: 17e574e9c +Phase 2 Router Initialization | Checksum: 276df3972 -Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.195 ; gain = 145.402 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2345.027 ; gain = 134.230 Phase 3 Initial Routing Phase 3.1 Global Routing -Phase 3.1 Global Routing | Checksum: 17e574e9c +Phase 3.1 Global Routing | Checksum: 276df3972 -Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.195 ; gain = 145.402 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2345.027 ; gain = 134.230 Phase 3.2 Initial Net Routing -Phase 3.2 Initial Net Routing | Checksum: 272722ad6 +Phase 3.2 Initial Net Routing | Checksum: 1646cdf4d -Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 2350.590 ; gain = 148.797 -Phase 3 Initial Routing | Checksum: 272722ad6 +Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 2349.422 ; gain = 138.625 +Phase 3 Initial Routing | Checksum: 1646cdf4d -Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 2350.590 ; gain = 148.797 +Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 2349.422 ; gain = 138.625 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 2990 - Number of Nodes with overlaps = 252 - Number of Nodes with overlaps = 65 - Number of Nodes with overlaps = 17 - Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 3178 + Number of Nodes with overlaps = 255 + Number of Nodes with overlaps = 41 + Number of Nodes with overlaps = 12 + Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.677 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.679 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 288010d2c +Phase 4.1 Global Iteration 0 | Checksum: 3741328e8 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949 -Phase 4 Rip-up And Reroute | Checksum: 288010d2c +Time (s): cpu = 00:00:19 ; elapsed = 00:00:31 . Memory (MB): peak = 2352.559 ; gain = 141.762 +Phase 4 Rip-up And Reroute | Checksum: 3741328e8 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:31 . Memory (MB): peak = 2352.559 ; gain = 141.762 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 288010d2c -Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949 +Phase 5.1.1 Update Timing +Phase 5.1.1 Update Timing | Checksum: 2b9958991 + +Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.679 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.1 Delay CleanUp | Checksum: 2b9958991 + +Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 288010d2c +Phase 5.2 Clock Skew Optimization | Checksum: 2b9958991 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949 -Phase 5 Delay and Skew Optimization | Checksum: 288010d2c +Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762 +Phase 5 Delay and Skew Optimization | Checksum: 2b9958991 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 271761283 +Phase 6.1.1 Update Timing | Checksum: 2903d569b -Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2358.742 ; gain = 156.949 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.677 | TNS=0.000 | WHS=0.055 | THS=0.000 | +Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.679 | TNS=0.000 | WHS=0.070 | THS=0.000 | -Phase 6.1 Hold Fix Iter | Checksum: 271761283 +Phase 6.1 Hold Fix Iter | Checksum: 2ecebe266 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2358.742 ; gain = 156.949 -Phase 6 Post Hold Fix | Checksum: 271761283 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762 +Phase 6 Post Hold Fix | Checksum: 2ecebe266 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2358.742 ; gain = 156.949 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 13.8992 % - Global Horizontal Routing Utilization = 14.3475 % + Global Vertical Routing Utilization = 16.0809 % + Global Horizontal Routing Utilization = 14.8794 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -622,44 +631,44 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 7 Route finalize | Checksum: 271761283 +Phase 7 Route finalize | Checksum: 2ecebe266 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2358.742 ; gain = 156.949 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 271761283 +Phase 8 Verifying routed nets | Checksum: 2ecebe266 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2360.758 ; gain = 158.965 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2354.578 ; gain = 143.781 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 20252a6c4 +Phase 9 Depositing Routes | Checksum: 2aa639e35 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2361.215 ; gain = 159.422 +Time (s): cpu = 00:00:20 ; elapsed = 00:00:34 . Memory (MB): peak = 2354.578 ; gain = 143.781 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=2.677 | TNS=0.000 | WHS=0.055 | THS=0.000 | +INFO: [Route 35-57] Estimated Timing Summary | WNS=2.679 | TNS=0.000 | WHS=0.070 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 20252a6c4 +Phase 10 Post Router Timing | Checksum: 2aa639e35 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:34 . Memory (MB): peak = 2361.215 ; gain = 159.422 +Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.578 ; gain = 143.781 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing -Phase 11 Post-Route Event Processing | Checksum: d1fb966c +Phase 11 Post-Route Event Processing | Checksum: 6f450aed -Time (s): cpu = 00:00:13 ; elapsed = 00:00:35 . Memory (MB): peak = 2361.215 ; gain = 159.422 -Ending Routing Task | Checksum: d1fb966c +Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.578 ; gain = 143.781 +Ending Routing Task | Checksum: 6f450aed -Time (s): cpu = 00:00:14 ; elapsed = 00:00:35 . Memory (MB): peak = 2361.215 ; gain = 159.422 +Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.578 ; gain = 143.781 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation -88 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +90 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:36 . Memory (MB): peak = 2361.215 ; gain = 191.535 +route_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:36 . Memory (MB): peak = 2354.578 ; gain = 175.285 INFO: [runtcl-4] Executing : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx Command: report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. @@ -672,14 +681,14 @@ INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt. report_methodology completed successfully -report_methodology: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2429.797 ; gain = 68.582 +report_methodology: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2435.902 ; gain = 81.324 INFO: [runtcl-4] Executing : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx Command: report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation -98 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +100 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [runtcl-4] Executing : report_route_status -file CPU_route_status.rpt -pb CPU_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file CPU_timing_summary_routed.rpt -pb CPU_timing_summary_routed.pb -rpx CPU_timing_summary_routed.rpx -warn_on_violation @@ -692,16 +701,16 @@ INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU_bus_sk INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 2488.125 ; gain = 4.934 -Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2488.125 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2488.125 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 2496.238 ; gain = 3.922 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2497.543 ; gain = 1.305 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2497.543 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.215 . Memory (MB): peak = 2488.125 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2488.125 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2488.125 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2488.125 ; gain = 4.934 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.221 . Memory (MB): peak = 2497.543 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 2497.543 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2497.543 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2497.543 ; gain = 5.227 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_routed.dcp' has been generated. Command: write_bitstream -force CPU.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -745,5 +754,5 @@ INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT dev INFO: [Common 17-83] Releasing license: Implementation 14 Infos, 13 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2951.012 ; gain = 462.887 -INFO: [Common 17-206] Exiting Vivado at Fri Jul 12 21:07:14 2024... +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2966.875 ; gain = 469.332 +INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 14:30:07 2024... diff --git a/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt index d9a8574..1ff2a07 100644 --- a/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 21:06:59 2024 +| Date : Sat Jul 13 14:29:52 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_bus_skew -warn_on_violation -file CPU_bus_skew_routed.rpt -pb CPU_bus_skew_routed.pb -rpx CPU_bus_skew_routed.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt index 297f2d9..6064672 100644 --- a/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 21:06:59 2024 +| Date : Sat Jul 13 14:29:52 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_clock_utilization -file CPU_clock_utilization_routed.rpt | Design : CPU @@ -50,7 +50,7 @@ Table of Contents +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+ -| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 6 | 18130 | 0 | 20.000 | clk_out1_phase_locked_loop | pll/inst/clkout1_buf/O | pll/inst/clk_out1 | +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 6 | 18132 | 0 | 20.000 | clk_out1_phase_locked_loop | pll/inst/clkout1_buf/O | pll/inst/clk_out1 | | g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 1 | 0 | 20.000 | clkfbout_phase_locked_loop | pll/inst/clkf_buf/O | pll/inst/clkfbout_buf_phase_locked_loop | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered @@ -78,12 +78,12 @@ Table of Contents +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1534 | 1200 | 474 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3394 | 1500 | 972 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | -| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2590 | 1200 | 888 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4413 | 1500 | 1301 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | -| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4412 | 1800 | 855 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 1787 | 950 | 508 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | +| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1517 | 1200 | 460 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3911 | 1500 | 1072 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2799 | 1200 | 937 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3610 | 1500 | 1055 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4277 | 1800 | 774 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 2018 | 950 | 601 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts @@ -107,7 +107,7 @@ All Modules +-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+ -| g0 | BUFG/O | n/a | clk_out1_phase_locked_loop | 20.000 | {0.000 10.000} | 18130 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | BUFG/O | n/a | clk_out1_phase_locked_loop | 20.000 | {0.000 10.000} | 18132 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types @@ -118,9 +118,9 @@ All Modules +----+-------+-------+-----------------------+ | | X0 | X1 | HORIZONTAL PROG DELAY | +----+-------+-------+-----------------------+ -| Y2 | 4412 | 1787 | 0 | -| Y1 | 2590 | 4413 | 0 | -| Y0 | 1534 | 3394 | 0 | +| Y2 | 4277 | 2018 | 0 | +| Y1 | 2799 | 3610 | 0 | +| Y0 | 1517 | 3911 | 0 | +----+-------+-------+-----------------------+ @@ -153,7 +153,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 1534 | 0 | 1534 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 1517 | 0 | 1517 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -166,7 +166,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+ -| g0 | n/a | BUFG/O | None | 3394 | 0 | 3394 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 3911 | 0 | 3911 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | | g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | pll/inst/clkfbout_buf_phase_locked_loop | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered @@ -180,7 +180,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 2590 | 0 | 2590 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 2799 | 0 | 2799 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -193,7 +193,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 4413 | 0 | 4413 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 3610 | 0 | 3610 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -206,7 +206,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 4412 | 0 | 4412 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 4277 | 0 | 4277 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -219,7 +219,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 1787 | 0 | 1787 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 2018 | 0 | 2018 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads diff --git a/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt b/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt index ddb3b28..e3759f5 100644 --- a/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 21:06:00 2024 +| Date : Sat Jul 13 14:28:53 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_control_sets -verbose -file CPU_control_sets_placed.rpt | Design : CPU @@ -27,7 +27,7 @@ Table of Contents | Minimum number of control sets | 547 | | Addition due to synthesis replication | 0 | | Addition due to physical synthesis replication | 0 | -| Unused register locations in slices containing registers | 14 | +| Unused register locations in slices containing registers | 12 | +----------------------------------------------------------+-------+ * Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers ** Run report_qor_suggestions for automated merging and remapping suggestions @@ -60,566 +60,566 @@ Table of Contents +--------------+-----------------------+------------------------+-----------------+--------------+ | No | No | No | 0 | 0 | | No | No | Yes | 0 | 0 | -| No | Yes | No | 710 | 237 | +| No | Yes | No | 712 | 272 | | Yes | No | No | 0 | 0 | | Yes | No | Yes | 0 | 0 | -| Yes | Yes | No | 17420 | 7064 | +| Yes | Yes | No | 17420 | 7020 | +--------------+-----------------------+------------------------+-----------------+--------------+ 4. Detailed Control Set Information ----------------------------------- -+--------------------+------------------------------------------------------------+-----------------------------------+------------------+----------------+--------------+ -| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | -+--------------------+------------------------------------------------------------+-----------------------------------+------------------+----------------+--------------+ -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_4[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[3]_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[1]_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/E[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[23][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[11][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[18][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[19][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[2][31]_i_1_n_0 | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[17][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[21][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[30][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[4][31]_i_1_n_0 | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[28][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[3][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[16][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[12][31]_i_1_n_0 | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | instruction_decode/register_file/p_0_in | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[13][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[22][31]_i_1_n_0 | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[25][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[31][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[5][31]_i_1_n_0 | data_memory/reset | 20 | 32 | 1.60 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[27][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[10][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[14][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[26][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[29][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[7][31]_i_1_n_0 | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[24][31]_i_1_n_0 | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[8][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[9][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_0[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/E[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_1[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_10[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_1[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_0[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_11[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_5[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_13[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_15[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_5[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_5[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_2[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_2[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_4[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_3[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_4[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_2[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__17_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_0[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__26_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_13[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_0[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_6[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__9_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_1[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_7[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_8[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_12[0] | data_memory/reset | 20 | 32 | 1.60 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_2[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_10[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_11[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_14[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_4[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_12[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__14_1[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_5[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_4[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_6[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_3[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__19_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_4[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_4[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__29_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__19_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__31_2[0] | data_memory/reset | 7 | 32 | 4.57 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_1[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_2[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_5[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_5[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_4[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_1[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__23_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_8[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_9[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_1[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_2[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__19_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__19_3[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_2[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_7[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_5[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__23_4[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_4[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | write_back/WB_register_write_reg_1[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_1[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_16[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__23_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_5[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_3[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_4[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__23_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_3[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_6[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__27_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_2[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__31_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep__0_3[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_13[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_25[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_4[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_22[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_5[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_4[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_7[0] | data_memory/reset | 20 | 32 | 1.60 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_8[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_10[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_30[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_10[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_12[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_10[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_11[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_28[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_23[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_7[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_3[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_18[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_13[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_14[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_8[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_17[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_16[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_17[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_5[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_15[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_19[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_11[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_20[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_12[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_1[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_6[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_6[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_18[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_13[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_20[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_27[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_15[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_24[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_26[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_29[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_14[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_21[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_2[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_31[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_11[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_0[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_16[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_9[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_14[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_19[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_24[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_17[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_22[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_4[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_12[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_11[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_13[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_14[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_36[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_8[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_33[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_11[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_12[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_14[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_22[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_25[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_35[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_4[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_29[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_6[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_38[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_10[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_15[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_37[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_5[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_7[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_16[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_32[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_17[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_18[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_8[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_19[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_34[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_20[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_27[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_21[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_20[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_6[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_7[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_24[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_23[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_18[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_19[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_21[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_0[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_23[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_15[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_26[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_28[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_9[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_16[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_13[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_30[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_9[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_31[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__1_10[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_10[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_11[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_33[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_26[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_35[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_29[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_0[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_25[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_24[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_32[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_7[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_11[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_29[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_30[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_15[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_16[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_19[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_20[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_12[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_18[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_26[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_9[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_27[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_24[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_30[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_31[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_21[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_4[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_7[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_9[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_36[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_21[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_22[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_28[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_8[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_27[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_4[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_28[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_17[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_32[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_31[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_13[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_14[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_23[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_34[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_35[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_5[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_36[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_33[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_6[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_25[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_5[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_6[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_22[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_8[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_10[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__1_34[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_23[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_6[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_64[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_18[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_13[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_19[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_14[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_23[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_27[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_30[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_21[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_29[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_33[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_35[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_39[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_40[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_43[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_46[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_25[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_37[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_47[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_20[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_32[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_48[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_49[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_5[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_50[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_51[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_24[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_36[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_54[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_57[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_44[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_22[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_58[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_60[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_63[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_66[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_45[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_61[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_31[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_55[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_28[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_16[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_4[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_7[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_8[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_62[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_42[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_9[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_53[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_12[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_17[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_41[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_56[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_59[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_15[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_65[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_34[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_26[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_38[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_52[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_7[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_4[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_9[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_8[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_6[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_1[0] | data_memory/reset | 20 | 32 | 1.60 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_35[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_12[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_11[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_23[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_24[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_29[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_32[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_36[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_18[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_27[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_4[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_8[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_30[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_34[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_4[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_0[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_14[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_26[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_7[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_7[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_11[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_13[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_9[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_15[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_19[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_0[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_6[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_8[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_10[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_13[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_10[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_10[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_12[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_16[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_17[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_6[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_21[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_9[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_22[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_20[0] | data_memory/reset | 20 | 32 | 1.60 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_25[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_28[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_31[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_0[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_33[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_27[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_22[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_30[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_4[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_40[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_45[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_51[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_18[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_35[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_11[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_20[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_16[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_24[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_26[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_28[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_43[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_47[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_49[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_54[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_56[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_14[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_42[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_58[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_13[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_17[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_55[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_59[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_6[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_60[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_12[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_31[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_61[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_52[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_36[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_62[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_63[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_23[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_32[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_41[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_46[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_8[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_57[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_38[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_25[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_48[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_7[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_15[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_33[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_29[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_34[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_39[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_50[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_53[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_19[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_37[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_21[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_44[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_9[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_3[0] | data_memory/reset | 13 | 44 | 3.38 | -| pll/inst/clk_out1 | | instruction_decode/IFID_PC_plus_4 | 40 | 67 | 1.67 | -| pll/inst/clk_out1 | | instruction_decode/SR[0] | 53 | 160 | 3.02 | -| pll/inst/clk_out1 | | data_memory/reset | 144 | 483 | 3.35 | -+--------------------+------------------------------------------------------------+-----------------------------------+------------------+----------------+--------------+ ++--------------------+------------------------------------------------------------+------------------------------+------------------+----------------+--------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | ++--------------------+------------------------------------------------------------+------------------------------+------------------+----------------+--------------+ +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_10[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_28[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_47[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | execution/alu/E[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[25][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[12][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[3][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[5][31]_i_1_n_0 | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[14][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[10][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/p_0_in | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[9][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[27][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[2][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[11][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[4][31]_i_1_n_0 | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[7][31]_i_1_n_0 | data_memory/reset | 19 | 32 | 1.68 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[26][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[17][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[22][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[24][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[31][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[13][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[16][31]_i_1_n_0 | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[18][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[21][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[28][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[30][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[8][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[19][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[23][31]_i_1_n_0 | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[29][31]_i_1_n_0 | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | write_back/E[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[1]_3[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[3]_1[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_22[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_8[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_11[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_9[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_17[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_18[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_24[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_27[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_13[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_30[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_19[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_14[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_28[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_6[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_7[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_8[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_21[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_25[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_38[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_32[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_3[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_10[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_23[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_4[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_16[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_23[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_1[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_16[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_11[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_17[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_25[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_12[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_26[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_15[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_22[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_15[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_19[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_20[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_21[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_29[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_14[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_3[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_0[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_24[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_7[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_9[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_33[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_20[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_34[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_36[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_13[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_35[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_37[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_4[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_6[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_18[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_5[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_31[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_12[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/E[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_0[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_2[0] | data_memory/reset | 7 | 32 | 4.57 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_19[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_23[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__14_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_22[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_25[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_26[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_27[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_4[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_28[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_4[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_5[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_0[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_0[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_2[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_5[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__26_1[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__9_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_1[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_54[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_13[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_0[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_14[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_15[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_21[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_0[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_4[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_0[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_10[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_24[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_11[0] | data_memory/reset | 7 | 32 | 4.57 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_6[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_16[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_2[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_20[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_2[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_0[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_17[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_0[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_4[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_3[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__17_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_18[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_4[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_2[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_0[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_4[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__30_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_0[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_4[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_6[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_5[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_1[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_5[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_5[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_7[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_4[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_4[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_5[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_0[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_5[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_3[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_4[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_1[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__29_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__30_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__27_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_3[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_1[0] | data_memory/reset | 20 | 32 | 1.60 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_3[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_0[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_8[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_28[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_7[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_23[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_9[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_10[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_0[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_11[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_11[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_12[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_22[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_13[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_14[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_14[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_24[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_30[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_29[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_5[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_18[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_19[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_16[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_17[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_15[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_13[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_2[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_31[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_4[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_27[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_5[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_8[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_6[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_25[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_10[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_12[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_20[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_0[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_26[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_6[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_21[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_24[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_25[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_25[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_4[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_8[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_26[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_17[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_27[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_30[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_28[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_22[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_10[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_12[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_38[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_28[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_15[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_21[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_31[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_5[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_20[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_22[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_34[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_27[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_41[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_6[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_11[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_33[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_18[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_20[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_19[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_29[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_32[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_23[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_16[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_24[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_17[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_10[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_39[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_14[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_7[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_15[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_0[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_16[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_11[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_35[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_26[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_36[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_40[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_9[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_21[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_13[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_9[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_14[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_13[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_37[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_2[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_18[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_23[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_42[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_43[0] | data_memory/reset | 20 | 32 | 1.60 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_29[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_9[0] | data_memory/reset | 7 | 32 | 4.57 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_10[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_8[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_29[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_27[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_3[0] | data_memory/reset | 19 | 32 | 1.68 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_8[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_6[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_1[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_17[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_16[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_30[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_0[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_13[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_23[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_11[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_10[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_7[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_12[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_32[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_18[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_14[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_31[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_30[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_31[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_5[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_15[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_33[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_11[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_20[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_4[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_24[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_25[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_34[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_7[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_35[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_6[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_5[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_28[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_12[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_13[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_32[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_36[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_37[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_38[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_39[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_4[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_22[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_40[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_41[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_51[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_48[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_6[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_7[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_44[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_3[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_2[0] | data_memory/reset | 20 | 32 | 1.60 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_45[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_4[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_49[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_5[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_8[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_8[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_9[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_52[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_46[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_7[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_5[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_9[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_0[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_50[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_47[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_6[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_10[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_11[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_12[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_13[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_0[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_25[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_8[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_30[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_10[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_26[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_11[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_9[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_10[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_13[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_34[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_14[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_15[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_14[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_2[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_22[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_12[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_7[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_25[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_15[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_20[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_32[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_36[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_4[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_21[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_16[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_5[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_11[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_17[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_5[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_17[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_29[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_33[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_23[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_18[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_28[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_19[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_8[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_12[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_16[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_13[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_6[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_6[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_4[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_31[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_9[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_18[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_24[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_35[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_7[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_22[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_20[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_23[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_27[0] | data_memory/reset | 6 | 32 | 5.33 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_24[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_5[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_60[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_42[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_43[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_8[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_37[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_38[0] | data_memory/reset | 19 | 32 | 1.68 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_62[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_29[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_52[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_34[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_46[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_55[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_57[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_40[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_59[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_63[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_51[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_7[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_31[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_45[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_53[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_33[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_48[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_49[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_32[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_3[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_6[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_61[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_4[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_30[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_36[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_58[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_50[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_9[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_44[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_56[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_35[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_27[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_39[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_41[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_3[0] | data_memory/reset | 19 | 44 | 2.32 | +| pll/inst/clk_out1 | | execution/alu/IFID_PC_plus_4 | 30 | 67 | 2.23 | +| pll/inst/clk_out1 | | execution/alu/SR[0] | 61 | 160 | 2.62 | +| pll/inst/clk_out1 | | data_memory/reset | 181 | 485 | 2.68 | ++--------------------+------------------------------------------------------------+------------------------------+------------------+----------------+--------------+ diff --git a/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt b/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt index 94dc7bf..98b3b84 100644 --- a/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 21:05:24 2024 +| Date : Sat Jul 13 14:28:18 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt index abacd86..3b0184c 100644 --- a/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 21:06:47 2024 +| Date : Sat Jul 13 14:29:40 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt b/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt index 4248b09..a8dac69 100644 --- a/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 21:06:00 2024 +| Date : Sat Jul 13 14:28:53 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_io -file CPU_io_placed.rpt | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt index e9e162b..0c74031 100644 --- a/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 21:06:53 2024 +| Date : Sat Jul 13 14:29:46 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_opt.dcp b/PipelineProcessor.runs/impl_1/CPU_opt.dcp index 5a0b467..f0fb8c0 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_opt.dcp and b/PipelineProcessor.runs/impl_1/CPU_opt.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_physopt.dcp b/PipelineProcessor.runs/impl_1/CPU_physopt.dcp index 9fd52fe..6c4e89d 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_physopt.dcp and b/PipelineProcessor.runs/impl_1/CPU_physopt.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_placed.dcp b/PipelineProcessor.runs/impl_1/CPU_placed.dcp index a1ba698..ed25cb2 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_placed.dcp and b/PipelineProcessor.runs/impl_1/CPU_placed.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt index 210b924..65103f3 100644 --- a/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 21:06:57 2024 +| Date : Sat Jul 13 14:29:51 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx | Design : CPU @@ -30,10 +30,10 @@ Table of Contents ---------- +--------------------------+--------------+ -| Total On-Chip Power (W) | 0.187 | +| Total On-Chip Power (W) | 0.189 | | Design Power Budget (W) | Unspecified* | | Power Budget Margin (W) | NA | -| Dynamic (W) | 0.119 | +| Dynamic (W) | 0.120 | | Device Static (W) | 0.069 | | Effective TJA (C/W) | 2.8 | | Max Ambient (C) | 84.5 | @@ -52,19 +52,19 @@ Table of Contents +----------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +----------------+-----------+----------+-----------+-----------------+ -| Clocks | 0.015 | 5 | --- | --- | -| Slice Logic | 0.002 | 30077 | --- | --- | -| LUT as Logic | 0.002 | 8003 | 20800 | 38.48 | +| Clocks | 0.016 | 5 | --- | --- | +| Slice Logic | 0.003 | 30286 | --- | --- | +| LUT as Logic | 0.003 | 8337 | 20800 | 40.08 | | CARRY4 | <0.001 | 39 | 8150 | 0.48 | -| Register | <0.001 | 18130 | 41600 | 43.58 | -| F7/F8 Muxes | <0.001 | 3514 | 32600 | 10.78 | +| Register | <0.001 | 18132 | 41600 | 43.59 | +| F7/F8 Muxes | <0.001 | 3461 | 32600 | 10.62 | | Others | 0.000 | 12 | --- | --- | -| Signals | 0.002 | 21867 | --- | --- | +| Signals | 0.002 | 21997 | --- | --- | | PLL | 0.099 | 1 | 5 | 20.00 | | DSPs | <0.001 | 3 | 90 | 3.33 | | I/O | <0.001 | 15 | 250 | 6.00 | | Static Power | 0.069 | | | | -| Total | 0.187 | | | | +| Total | 0.189 | | | | +----------------+-----------+----------+-----------+-----------------+ @@ -74,7 +74,7 @@ Table of Contents +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ -| Vccint | 1.000 | 0.038 | 0.029 | 0.010 | NA | Unspecified | NA | +| Vccint | 1.000 | 0.040 | 0.030 | 0.010 | NA | Unspecified | NA | | Vccaux | 1.800 | 0.063 | 0.050 | 0.013 | NA | Unspecified | NA | | Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | @@ -145,13 +145,14 @@ Table of Contents +----------------------+-----------+ | Name | Power (W) | +----------------------+-----------+ -| CPU | 0.119 | +| CPU | 0.120 | | data_memory | 0.014 | | instruction_decode | 0.002 | -| instruction_fetch | 0.002 | +| register_file | 0.001 | +| instruction_fetch | 0.001 | | pll | 0.100 | | inst | 0.100 | -| write_back | 0.001 | +| write_back | 0.002 | +----------------------+-----------+ diff --git a/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb b/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb index b3190bf..403d16c 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb and b/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_route_status.pb b/PipelineProcessor.runs/impl_1/CPU_route_status.pb index 3e20761..e8db5e4 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_route_status.pb and b/PipelineProcessor.runs/impl_1/CPU_route_status.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_route_status.rpt b/PipelineProcessor.runs/impl_1/CPU_route_status.rpt index 6d15b26..3f1e04d 100644 --- a/PipelineProcessor.runs/impl_1/CPU_route_status.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_route_status.rpt @@ -1,11 +1,11 @@ Design Route Status : # nets : ------------------------------------------- : ----------- : - # of logical nets.......................... : 30302 : - # of nets not needing routing.......... : 8428 : - # of internally routed nets........ : 8428 : - # of routable nets..................... : 21874 : - # of fully routed nets............. : 21874 : + # of logical nets.......................... : 30511 : + # of nets not needing routing.......... : 8507 : + # of internally routed nets........ : 8507 : + # of routable nets..................... : 22004 : + # of fully routed nets............. : 22004 : # of nets with routing errors.......... : 0 : ------------------------------------------- : ----------- : diff --git a/PipelineProcessor.runs/impl_1/CPU_routed.dcp b/PipelineProcessor.runs/impl_1/CPU_routed.dcp index 48be280..21d8f9f 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_routed.dcp and b/PipelineProcessor.runs/impl_1/CPU_routed.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb index fd83a94..cf643ee 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb and b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt index c6f288f..7bbd449 100644 --- a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 21:06:58 2024 +| Date : Sat Jul 13 14:29:52 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -report_unconstrained -file CPU_timing_summary_routed.rpt -pb CPU_timing_summary_routed.pb -rpx CPU_timing_summary_routed.rpx -warn_on_violation | Design : CPU @@ -142,7 +142,7 @@ Table of Contents WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 2.677 0.000 0 35777 0.055 0.000 0 35777 3.000 0.000 0 18136 + 2.679 0.000 0 35779 0.070 0.000 0 35779 3.000 0.000 0 18138 All user specified timing constraints are met. @@ -168,7 +168,7 @@ hardware_clk {0.000 5.000} 10.000 100.000 Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- hardware_clk 3.000 0.000 0 1 - clk_out1_phase_locked_loop 2.677 0.000 0 35777 0.055 0.000 0 35777 9.500 0.000 0 18132 + clk_out1_phase_locked_loop 2.679 0.000 0 35779 0.070 0.000 0 35779 9.500 0.000 0 18134 clkfbout_phase_locked_loop 17.845 0.000 0 3 @@ -248,27 +248,27 @@ High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 5.000 From Clock: clk_out1_phase_locked_loop To Clock: clk_out1_phase_locked_loop -Setup : 0 Failing Endpoints, Worst Slack 2.677ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.055ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 2.679ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.070ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 9.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 2.677ns (required time - arrival time) - Source: execution/EX_rt_address_reg[2]/C +Slack (MET) : 2.679ns (required time - arrival time) + Source: write_back/WB_memory_read_data_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[30]_rep/D + Destination: memory_access/MEM_ALU_result_reg[24]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.869ns (logic 8.394ns (49.760%) route 8.475ns (50.240%)) - Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) - Clock Path Skew: -0.127ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.034ns = ( 17.966 - 20.000 ) - Source Clock Delay (SCD): -2.412ns + Data Path Delay: 17.177ns (logic 7.918ns (46.097%) route 9.259ns (53.903%)) + Logic Levels: 12 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) + Source Clock Delay (SCD): -2.420ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -287,46 +287,41 @@ Slack (MET) : 2.677ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 - SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C + net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 + SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q - net (fo=4, routed) 1.044 -0.850 execution/Q[2] - SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O - net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 - SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O - net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O - net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] - SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O - net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] - DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) - 4.053 7.660 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 - DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.180 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 - SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O - net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 - SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X11Y35 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.018 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.018 execution/alu/result0_inferred__11/i__carry__1_n_0 - SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[2]) - 0.239 11.257 r execution/alu/result0_inferred__11/i__carry__2/O[2] - net (fo=1, routed) 0.449 11.706 execution/alu/result0_inferred__11/i__carry__2_n_5 - SLICE_X8Y36 LUT6 (Prop_lut6_I5_O) 0.302 12.008 r execution/alu/MEM_ALU_result[30]_i_6/O - net (fo=1, routed) 0.727 12.735 execution/alu/MEM_ALU_result[30]_i_6_n_0 - SLICE_X12Y36 LUT6 (Prop_lut6_I5_O) 0.124 12.859 r execution/alu/MEM_ALU_result[30]_i_3/O - net (fo=1, routed) 0.000 12.859 execution/alu/MEM_ALU_result[30]_i_3_n_0 - SLICE_X12Y36 MUXF7 (Prop_muxf7_I1_O) 0.214 13.073 r execution/alu/MEM_ALU_result_reg[30]_i_1/O - net (fo=3, routed) 1.385 14.457 memory_access/prev_ALU_result[30] - SLICE_X13Y59 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/D + SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q + net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] + SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O + net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] + SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.905 3.857 execution/result0__0_3 + SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O + net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] + DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.665 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 + DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 10.185 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 + SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 + SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X12Y18 CARRY4 (Prop_carry4_CI_O[0]) + 0.219 12.085 r execution/alu/result0_inferred__11/i__carry__1/O[0] + net (fo=1, routed) 0.803 12.888 execution/alu/result0_inferred__11/i__carry__1_n_7 + SLICE_X8Y21 LUT4 (Prop_lut4_I3_O) 0.295 13.183 r execution/alu/MEM_ALU_result[24]_i_13/O + net (fo=1, routed) 0.646 13.829 execution/alu/MEM_ALU_result[24]_i_13_n_0 + SLICE_X5Y21 LUT6 (Prop_lut6_I5_O) 0.124 13.953 r execution/alu/MEM_ALU_result[24]_i_4/O + net (fo=1, routed) 0.680 14.633 execution/alu/MEM_ALU_result[24]_i_4_n_0 + SLICE_X8Y21 LUT6 (Prop_lut6_I3_O) 0.124 14.757 r execution/alu/MEM_ALU_result[24]_i_1/O + net (fo=1, routed) 0.000 14.757 memory_access/prev_ALU_result[24] + SLICE_X8Y21 FDRE r memory_access/MEM_ALU_result_reg[24]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -339,30 +334,30 @@ Slack (MET) : 2.677ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.438 17.966 memory_access/clk_out1 - SLICE_X13Y59 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/C - clock pessimism -0.505 17.461 + net (fo=18132, routed) 1.438 17.967 memory_access/clk_out1 + SLICE_X8Y21 FDRE r memory_access/MEM_ALU_result_reg[24]/C + clock pessimism -0.505 17.462 clock uncertainty -0.108 17.354 - SLICE_X13Y59 FDRE (Setup_fdre_C_D) -0.220 17.134 memory_access/MEM_ALU_result_reg[30]_rep + SLICE_X8Y21 FDRE (Setup_fdre_C_D) 0.081 17.435 memory_access/MEM_ALU_result_reg[24] ------------------------------------------------------------------- - required time 17.134 - arrival time -14.457 + required time 17.435 + arrival time -14.757 ------------------------------------------------------------------- - slack 2.677 + slack 2.679 -Slack (MET) : 2.829ns (required time - arrival time) - Source: execution/EX_rt_address_reg[2]/C +Slack (MET) : 3.013ns (required time - arrival time) + Source: write_back/WB_memory_read_data_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[30]/D + Destination: memory_access/MEM_ALU_result_reg[23]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.733ns (logic 8.394ns (50.165%) route 8.339ns (49.835%)) - Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) - Clock Path Skew: -0.127ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.034ns = ( 17.966 - 20.000 ) - Source Clock Delay (SCD): -2.412ns + Data Path Delay: 16.858ns (logic 7.909ns (46.917%) route 8.949ns (53.083%)) + Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) + Clock Path Skew: -0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.966ns = ( 18.034 - 20.000 ) + Source Clock Delay (SCD): -2.420ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -381,46 +376,38 @@ Slack (MET) : 2.829ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 - SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C + net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 + SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q - net (fo=4, routed) 1.044 -0.850 execution/Q[2] - SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O - net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 - SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O - net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O - net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] - SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O - net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] - DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) - 4.053 7.660 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 - DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.180 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 - SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O - net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 - SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X11Y35 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.018 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.018 execution/alu/result0_inferred__11/i__carry__1_n_0 - SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[2]) - 0.239 11.257 r execution/alu/result0_inferred__11/i__carry__2/O[2] - net (fo=1, routed) 0.449 11.706 execution/alu/result0_inferred__11/i__carry__2_n_5 - SLICE_X8Y36 LUT6 (Prop_lut6_I5_O) 0.302 12.008 r execution/alu/MEM_ALU_result[30]_i_6/O - net (fo=1, routed) 0.727 12.735 execution/alu/MEM_ALU_result[30]_i_6_n_0 - SLICE_X12Y36 LUT6 (Prop_lut6_I5_O) 0.124 12.859 r execution/alu/MEM_ALU_result[30]_i_3/O - net (fo=1, routed) 0.000 12.859 execution/alu/MEM_ALU_result[30]_i_3_n_0 - SLICE_X12Y36 MUXF7 (Prop_muxf7_I1_O) 0.214 13.073 r execution/alu/MEM_ALU_result_reg[30]_i_1/O - net (fo=3, routed) 1.248 14.321 memory_access/prev_ALU_result[30] - SLICE_X12Y60 FDRE r memory_access/MEM_ALU_result_reg[30]/D + SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q + net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] + SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O + net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] + SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.905 3.857 execution/result0__0_3 + SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O + net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] + DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.665 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 + DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 10.185 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 + SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 + SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X12Y17 CARRY4 (Prop_carry4_CI_O[3]) + 0.315 12.064 r execution/alu/result0_inferred__11/i__carry__0/O[3] + net (fo=1, routed) 0.818 12.882 execution/alu/result0_inferred__11/i__carry__0_n_4 + SLICE_X7Y17 LUT4 (Prop_lut4_I3_O) 0.307 13.189 r execution/alu/MEM_ALU_result[23]_i_11/O + net (fo=1, routed) 0.701 13.891 execution/alu/MEM_ALU_result[23]_i_11_n_0 + SLICE_X3Y21 LUT6 (Prop_lut6_I5_O) 0.124 14.015 r execution/alu/MEM_ALU_result[23]_i_4/O + net (fo=1, routed) 0.299 14.313 execution/alu/MEM_ALU_result[23]_i_4_n_0 + SLICE_X7Y21 LUT6 (Prop_lut6_I3_O) 0.124 14.437 r execution/alu/MEM_ALU_result[23]_i_1/O + net (fo=1, routed) 0.000 14.437 memory_access/prev_ALU_result[23] + SLICE_X7Y21 FDRE r memory_access/MEM_ALU_result_reg[23]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -433,30 +420,30 @@ Slack (MET) : 2.829ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.438 17.966 memory_access/clk_out1 - SLICE_X12Y60 FDRE r memory_access/MEM_ALU_result_reg[30]/C - clock pessimism -0.505 17.461 - clock uncertainty -0.108 17.354 - SLICE_X12Y60 FDRE (Setup_fdre_C_D) -0.204 17.150 memory_access/MEM_ALU_result_reg[30] + net (fo=18132, routed) 1.505 18.034 memory_access/clk_out1 + SLICE_X7Y21 FDRE r memory_access/MEM_ALU_result_reg[23]/C + clock pessimism -0.505 17.529 + clock uncertainty -0.108 17.421 + SLICE_X7Y21 FDRE (Setup_fdre_C_D) 0.029 17.450 memory_access/MEM_ALU_result_reg[23] ------------------------------------------------------------------- - required time 17.150 - arrival time -14.321 + required time 17.450 + arrival time -14.437 ------------------------------------------------------------------- - slack 2.829 + slack 3.013 -Slack (MET) : 3.117ns (required time - arrival time) - Source: execution/EX_rt_address_reg[2]/C +Slack (MET) : 3.041ns (required time - arrival time) + Source: write_back/WB_memory_read_data_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[30]_rep__0/D + Destination: memory_access/MEM_ALU_result_reg[28]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.446ns (logic 8.394ns (51.039%) route 8.052ns (48.961%)) - Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) - Clock Path Skew: -0.125ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.032ns = ( 17.968 - 20.000 ) - Source Clock Delay (SCD): -2.412ns + Data Path Delay: 16.830ns (logic 8.035ns (47.741%) route 8.795ns (52.259%)) + Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=2) + Clock Path Skew: -0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.965ns = ( 18.035 - 20.000 ) + Source Clock Delay (SCD): -2.420ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -475,46 +462,44 @@ Slack (MET) : 3.117ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 - SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C + net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 + SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q - net (fo=4, routed) 1.044 -0.850 execution/Q[2] - SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O - net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 - SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O - net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O - net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] - SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O - net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] - DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) - 4.053 7.660 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 - DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.180 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 - SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O - net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 - SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X11Y35 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.018 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.018 execution/alu/result0_inferred__11/i__carry__1_n_0 - SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[2]) - 0.239 11.257 r execution/alu/result0_inferred__11/i__carry__2/O[2] - net (fo=1, routed) 0.449 11.706 execution/alu/result0_inferred__11/i__carry__2_n_5 - SLICE_X8Y36 LUT6 (Prop_lut6_I5_O) 0.302 12.008 r execution/alu/MEM_ALU_result[30]_i_6/O - net (fo=1, routed) 0.727 12.735 execution/alu/MEM_ALU_result[30]_i_6_n_0 - SLICE_X12Y36 LUT6 (Prop_lut6_I5_O) 0.124 12.859 r execution/alu/MEM_ALU_result[30]_i_3/O - net (fo=1, routed) 0.000 12.859 execution/alu/MEM_ALU_result[30]_i_3_n_0 - SLICE_X12Y36 MUXF7 (Prop_muxf7_I1_O) 0.214 13.073 r execution/alu/MEM_ALU_result_reg[30]_i_1/O - net (fo=3, routed) 0.962 14.034 memory_access/prev_ALU_result[30] - SLICE_X12Y55 FDRE r memory_access/MEM_ALU_result_reg[30]_rep__0/D + SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q + net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] + SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O + net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] + SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.905 3.857 execution/result0__0_3 + SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O + net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] + DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.665 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 + DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 10.185 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 + SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 + SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X12Y18 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.983 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.983 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X12Y19 CARRY4 (Prop_carry4_CI_O[0]) + 0.219 12.202 r execution/alu/result0_inferred__11/i__carry__2/O[0] + net (fo=1, routed) 0.835 13.037 execution/alu/result0_inferred__11/i__carry__2_n_7 + SLICE_X6Y19 LUT4 (Prop_lut4_I3_O) 0.295 13.332 r execution/alu/MEM_ALU_result[28]_i_12/O + net (fo=1, routed) 0.427 13.759 execution/alu/MEM_ALU_result[28]_i_12_n_0 + SLICE_X5Y20 LUT5 (Prop_lut5_I4_O) 0.124 13.883 r execution/alu/MEM_ALU_result[28]_i_4/O + net (fo=1, routed) 0.403 14.286 execution/alu/MEM_ALU_result[28]_i_4_n_0 + SLICE_X5Y20 LUT6 (Prop_lut6_I3_O) 0.124 14.410 r execution/alu/MEM_ALU_result[28]_i_1/O + net (fo=1, routed) 0.000 14.410 memory_access/prev_ALU_result[28] + SLICE_X5Y20 FDRE r memory_access/MEM_ALU_result_reg[28]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -527,31 +512,31 @@ Slack (MET) : 3.117ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.440 17.968 memory_access/clk_out1 - SLICE_X12Y55 FDRE r memory_access/MEM_ALU_result_reg[30]_rep__0/C - clock pessimism -0.505 17.463 - clock uncertainty -0.108 17.356 - SLICE_X12Y55 FDRE (Setup_fdre_C_D) -0.204 17.152 memory_access/MEM_ALU_result_reg[30]_rep__0 + net (fo=18132, routed) 1.506 18.035 memory_access/clk_out1 + SLICE_X5Y20 FDRE r memory_access/MEM_ALU_result_reg[28]/C + clock pessimism -0.505 17.530 + clock uncertainty -0.108 17.422 + SLICE_X5Y20 FDRE (Setup_fdre_C_D) 0.029 17.451 memory_access/MEM_ALU_result_reg[28] ------------------------------------------------------------------- - required time 17.152 - arrival time -14.034 + required time 17.451 + arrival time -14.410 ------------------------------------------------------------------- - slack 3.117 + slack 3.041 -Slack (MET) : 4.099ns (required time - arrival time) - Source: execution/EX_rt_address_reg[2]/C +Slack (MET) : 3.055ns (required time - arrival time) + Source: write_back/WB_memory_read_data_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[29]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 15.744ns (logic 8.521ns (54.123%) route 7.223ns (45.877%)) - Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) - Clock Path Skew: -0.113ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.028ns = ( 17.972 - 20.000 ) - Source Clock Delay (SCD): -2.412ns - Clock Pessimism Removal (CPR): -0.497ns + Data Path Delay: 16.817ns (logic 8.150ns (48.463%) route 8.667ns (51.537%)) + Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=2) + Clock Path Skew: -0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.965ns = ( 18.035 - 20.000 ) + Source Clock Delay (SCD): -2.420ns + Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -569,46 +554,44 @@ Slack (MET) : 4.099ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 - SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C + net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 + SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q - net (fo=4, routed) 1.044 -0.850 execution/Q[2] - SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O - net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 - SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O - net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O - net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] - SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O - net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] - DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) - 4.053 7.660 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 - DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.180 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 - SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O - net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 - SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X11Y35 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.018 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.018 execution/alu/result0_inferred__11/i__carry__1_n_0 - SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 11.352 r execution/alu/result0_inferred__11/i__carry__2/O[1] - net (fo=1, routed) 0.595 11.947 execution/alu/result0_inferred__11/i__carry__2_n_6 - SLICE_X8Y35 LUT6 (Prop_lut6_I5_O) 0.303 12.250 r execution/alu/MEM_ALU_result[29]_i_6/O - net (fo=1, routed) 0.713 12.963 execution/alu/MEM_ALU_result[29]_i_6_n_0 - SLICE_X13Y33 LUT6 (Prop_lut6_I5_O) 0.124 13.087 r execution/alu/MEM_ALU_result[29]_i_3/O - net (fo=1, routed) 0.000 13.087 execution/alu/MEM_ALU_result[29]_i_3_n_0 - SLICE_X13Y33 MUXF7 (Prop_muxf7_I1_O) 0.245 13.332 r execution/alu/MEM_ALU_result_reg[29]_i_1/O - net (fo=1, routed) 0.000 13.332 memory_access/prev_ALU_result[29] - SLICE_X13Y33 FDRE r memory_access/MEM_ALU_result_reg[29]/D + SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q + net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] + SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O + net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] + SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.905 3.857 execution/result0__0_3 + SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O + net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] + DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.665 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 + DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 10.185 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 + SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 + SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X12Y18 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.983 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.983 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X12Y19 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 12.306 r execution/alu/result0_inferred__11/i__carry__2/O[1] + net (fo=1, routed) 0.600 12.905 execution/alu/result0_inferred__11/i__carry__2_n_6 + SLICE_X6Y19 LUT4 (Prop_lut4_I3_O) 0.306 13.211 r execution/alu/MEM_ALU_result[29]_i_10/O + net (fo=1, routed) 0.453 13.664 execution/alu/MEM_ALU_result[29]_i_10_n_0 + SLICE_X6Y21 LUT5 (Prop_lut5_I4_O) 0.124 13.788 r execution/alu/MEM_ALU_result[29]_i_4/O + net (fo=1, routed) 0.484 14.273 execution/alu/MEM_ALU_result[29]_i_4_n_0 + SLICE_X7Y20 LUT6 (Prop_lut6_I3_O) 0.124 14.397 r execution/alu/MEM_ALU_result[29]_i_1/O + net (fo=1, routed) 0.000 14.397 memory_access/prev_ALU_result[29] + SLICE_X7Y20 FDRE r memory_access/MEM_ALU_result_reg[29]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -621,31 +604,31 @@ Slack (MET) : 4.099ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.443 17.972 memory_access/clk_out1 - SLICE_X13Y33 FDRE r memory_access/MEM_ALU_result_reg[29]/C - clock pessimism -0.497 17.475 - clock uncertainty -0.108 17.367 - SLICE_X13Y33 FDRE (Setup_fdre_C_D) 0.064 17.431 memory_access/MEM_ALU_result_reg[29] + net (fo=18132, routed) 1.506 18.035 memory_access/clk_out1 + SLICE_X7Y20 FDRE r memory_access/MEM_ALU_result_reg[29]/C + clock pessimism -0.505 17.530 + clock uncertainty -0.108 17.422 + SLICE_X7Y20 FDRE (Setup_fdre_C_D) 0.029 17.451 memory_access/MEM_ALU_result_reg[29] ------------------------------------------------------------------- - required time 17.431 - arrival time -13.332 + required time 17.451 + arrival time -14.397 ------------------------------------------------------------------- - slack 4.099 + slack 3.055 -Slack (MET) : 4.315ns (required time - arrival time) - Source: execution/EX_rt_address_reg[2]/C +Slack (MET) : 3.160ns (required time - arrival time) + Source: write_back/WB_memory_read_data_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[27]/D + Destination: memory_access/MEM_ALU_result_reg[30]_rep/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 15.578ns (logic 8.391ns (53.863%) route 7.187ns (46.137%)) - Logic Levels: 13 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) - Clock Path Skew: -0.112ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.027ns = ( 17.973 - 20.000 ) - Source Clock Delay (SCD): -2.412ns - Clock Pessimism Removal (CPR): -0.497ns + Data Path Delay: 16.600ns (logic 7.937ns (47.813%) route 8.663ns (52.187%)) + Logic Levels: 12 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=2) + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.032ns = ( 17.968 - 20.000 ) + Source Clock Delay (SCD): -2.420ns + Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -663,43 +646,42 @@ Slack (MET) : 4.315ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 - SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C + net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 + SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q - net (fo=4, routed) 1.044 -0.850 execution/Q[2] - SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O - net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 - SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O - net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O - net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] - SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O - net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] - DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) - 4.053 7.660 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 - DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.180 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 - SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O - net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 - SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X11Y35 CARRY4 (Prop_carry4_CI_O[3]) - 0.313 11.217 r execution/alu/result0_inferred__11/i__carry__1/O[3] - net (fo=1, routed) 0.673 11.890 execution/alu/result0_inferred__11/i__carry__1_n_4 - SLICE_X8Y35 LUT6 (Prop_lut6_I5_O) 0.306 12.196 r execution/alu/MEM_ALU_result[27]_i_6/O - net (fo=1, routed) 0.599 12.795 execution/alu/MEM_ALU_result[27]_i_6_n_0 - SLICE_X14Y34 LUT6 (Prop_lut6_I5_O) 0.124 12.919 r execution/alu/MEM_ALU_result[27]_i_3/O - net (fo=1, routed) 0.000 12.919 execution/alu/MEM_ALU_result[27]_i_3_n_0 - SLICE_X14Y34 MUXF7 (Prop_muxf7_I1_O) 0.247 13.166 r execution/alu/MEM_ALU_result_reg[27]_i_1/O - net (fo=1, routed) 0.000 13.166 memory_access/prev_ALU_result[27] - SLICE_X14Y34 FDRE r memory_access/MEM_ALU_result_reg[27]/D + SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q + net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] + SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O + net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] + SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.905 3.857 execution/result0__0_3 + SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O + net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] + DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.665 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 + DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 10.185 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 + SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 + SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X12Y18 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.983 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.983 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X12Y19 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 12.222 r execution/alu/result0_inferred__11/i__carry__2/O[2] + net (fo=1, routed) 0.671 12.892 execution/alu/result0_inferred__11/i__carry__2_n_5 + SLICE_X10Y21 LUT4 (Prop_lut4_I3_O) 0.301 13.193 r execution/alu/MEM_ALU_result[30]_i_3/O + net (fo=2, routed) 0.294 13.487 execution/alu/MEM_ALU_result[30]_i_3_n_0 + SLICE_X10Y21 LUT6 (Prop_lut6_I2_O) 0.124 13.611 r execution/alu/MEM_ALU_result[30]_rep_i_1/O + net (fo=1, routed) 0.568 14.180 memory_access/MEM_ALU_result_reg[30]_rep_29 + SLICE_X10Y21 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -712,31 +694,31 @@ Slack (MET) : 4.315ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.444 17.973 memory_access/clk_out1 - SLICE_X14Y34 FDRE r memory_access/MEM_ALU_result_reg[27]/C - clock pessimism -0.497 17.476 - clock uncertainty -0.108 17.368 - SLICE_X14Y34 FDRE (Setup_fdre_C_D) 0.113 17.481 memory_access/MEM_ALU_result_reg[27] + net (fo=18132, routed) 1.439 17.968 memory_access/clk_out1 + SLICE_X10Y21 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/C + clock pessimism -0.505 17.463 + clock uncertainty -0.108 17.355 + SLICE_X10Y21 FDRE (Setup_fdre_C_D) -0.016 17.339 memory_access/MEM_ALU_result_reg[30]_rep ------------------------------------------------------------------- - required time 17.481 - arrival time -13.166 + required time 17.339 + arrival time -14.180 ------------------------------------------------------------------- - slack 4.315 + slack 3.160 -Slack (MET) : 4.357ns (required time - arrival time) - Source: execution/EX_rt_address_reg[2]/C +Slack (MET) : 3.264ns (required time - arrival time) + Source: write_back/WB_memory_read_data_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[25]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 15.537ns (logic 8.376ns (53.910%) route 7.161ns (46.090%)) - Logic Levels: 13 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) - Clock Path Skew: -0.111ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.026ns = ( 17.974 - 20.000 ) - Source Clock Delay (SCD): -2.412ns - Clock Pessimism Removal (CPR): -0.497ns + Data Path Delay: 16.608ns (logic 8.033ns (48.367%) route 8.575ns (51.633%)) + Logic Levels: 12 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) + Clock Path Skew: -0.051ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.966ns = ( 18.034 - 20.000 ) + Source Clock Delay (SCD): -2.420ns + Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -754,43 +736,41 @@ Slack (MET) : 4.357ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 - SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C + net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 + SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q - net (fo=4, routed) 1.044 -0.850 execution/Q[2] - SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O - net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 - SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O - net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O - net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] - SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O - net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] - DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) - 4.053 7.660 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 - DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.180 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 - SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O - net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 - SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X11Y35 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 11.238 r execution/alu/result0_inferred__11/i__carry__1/O[1] - net (fo=1, routed) 0.665 11.903 execution/alu/result0_inferred__11/i__carry__1_n_6 - SLICE_X9Y35 LUT6 (Prop_lut6_I5_O) 0.303 12.206 r execution/alu/MEM_ALU_result[25]_i_6/O - net (fo=1, routed) 0.581 12.787 execution/alu/MEM_ALU_result[25]_i_6_n_0 - SLICE_X12Y35 LUT6 (Prop_lut6_I5_O) 0.124 12.911 r execution/alu/MEM_ALU_result[25]_i_3/O - net (fo=1, routed) 0.000 12.911 execution/alu/MEM_ALU_result[25]_i_3_n_0 - SLICE_X12Y35 MUXF7 (Prop_muxf7_I1_O) 0.214 13.125 r execution/alu/MEM_ALU_result_reg[25]_i_1/O - net (fo=1, routed) 0.000 13.125 memory_access/prev_ALU_result[25] - SLICE_X12Y35 FDRE r memory_access/MEM_ALU_result_reg[25]/D + SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q + net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] + SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O + net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] + SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.905 3.857 execution/result0__0_3 + SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O + net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] + DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.665 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 + DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 10.185 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 + SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 + SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X12Y18 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 12.189 r execution/alu/result0_inferred__11/i__carry__1/O[1] + net (fo=1, routed) 0.725 12.914 execution/alu/result0_inferred__11/i__carry__1_n_6 + SLICE_X7Y20 LUT4 (Prop_lut4_I3_O) 0.306 13.220 r execution/alu/MEM_ALU_result[25]_i_11/O + net (fo=1, routed) 0.436 13.656 execution/alu/MEM_ALU_result[25]_i_11_n_0 + SLICE_X4Y21 LUT6 (Prop_lut6_I5_O) 0.124 13.780 r execution/alu/MEM_ALU_result[25]_i_4/O + net (fo=1, routed) 0.284 14.064 execution/alu/MEM_ALU_result[25]_i_4_n_0 + SLICE_X7Y21 LUT6 (Prop_lut6_I3_O) 0.124 14.188 r execution/alu/MEM_ALU_result[25]_i_1/O + net (fo=1, routed) 0.000 14.188 memory_access/prev_ALU_result[25] + SLICE_X7Y21 FDRE r memory_access/MEM_ALU_result_reg[25]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -803,210 +783,31 @@ Slack (MET) : 4.357ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.445 17.974 memory_access/clk_out1 - SLICE_X12Y35 FDRE r memory_access/MEM_ALU_result_reg[25]/C - clock pessimism -0.497 17.477 - clock uncertainty -0.108 17.369 - SLICE_X12Y35 FDRE (Setup_fdre_C_D) 0.113 17.482 memory_access/MEM_ALU_result_reg[25] + net (fo=18132, routed) 1.505 18.034 memory_access/clk_out1 + SLICE_X7Y21 FDRE r memory_access/MEM_ALU_result_reg[25]/C + clock pessimism -0.505 17.529 + clock uncertainty -0.108 17.421 + SLICE_X7Y21 FDRE (Setup_fdre_C_D) 0.031 17.452 memory_access/MEM_ALU_result_reg[25] ------------------------------------------------------------------- - required time 17.482 - arrival time -13.125 + required time 17.452 + arrival time -14.188 ------------------------------------------------------------------- - slack 4.357 + slack 3.264 -Slack (MET) : 4.410ns (required time - arrival time) - Source: execution/EX_rt_address_reg[2]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[19]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 15.497ns (logic 8.024ns (51.779%) route 7.473ns (48.221%)) - Logic Levels: 11 (CARRY4=1 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) - Clock Path Skew: -0.050ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.965ns = ( 18.035 - 20.000 ) - Source Clock Delay (SCD): -2.412ns - Clock Pessimism Removal (CPR): -0.497ns - Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 - SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q - net (fo=4, routed) 1.044 -0.850 execution/Q[2] - SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O - net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 - SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O - net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O - net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] - SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O - net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] - DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) - 4.053 7.660 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 - DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.180 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 - SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O - net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 - SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_O[3]) - 0.640 10.880 r execution/alu/result0_inferred__11/i__carry/O[3] - net (fo=1, routed) 0.973 11.853 execution/alu/result0_inferred__11/i__carry_n_4 - SLICE_X4Y34 LUT6 (Prop_lut6_I5_O) 0.306 12.159 r execution/alu/MEM_ALU_result[19]_i_6/O - net (fo=1, routed) 0.585 12.744 execution/alu/MEM_ALU_result[19]_i_6_n_0 - SLICE_X7Y30 LUT6 (Prop_lut6_I5_O) 0.124 12.868 r execution/alu/MEM_ALU_result[19]_i_3/O - net (fo=1, routed) 0.000 12.868 execution/alu/MEM_ALU_result[19]_i_3_n_0 - SLICE_X7Y30 MUXF7 (Prop_muxf7_I1_O) 0.217 13.085 r execution/alu/MEM_ALU_result_reg[19]_i_1/O - net (fo=1, routed) 0.000 13.085 memory_access/prev_ALU_result[19] - SLICE_X7Y30 FDRE r memory_access/MEM_ALU_result_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 20.000 20.000 r - R4 0.000 20.000 r hardware_clk (IN) - net (fo=0) 0.000 20.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.506 18.035 memory_access/clk_out1 - SLICE_X7Y30 FDRE r memory_access/MEM_ALU_result_reg[19]/C - clock pessimism -0.497 17.538 - clock uncertainty -0.108 17.430 - SLICE_X7Y30 FDRE (Setup_fdre_C_D) 0.064 17.494 memory_access/MEM_ALU_result_reg[19] - ------------------------------------------------------------------- - required time 17.494 - arrival time -13.085 - ------------------------------------------------------------------- - slack 4.410 - -Slack (MET) : 4.445ns (required time - arrival time) - Source: execution/EX_rt_address_reg[2]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[31]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 15.401ns (logic 8.475ns (55.030%) route 6.926ns (44.970%)) - Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) - Clock Path Skew: -0.111ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.026ns = ( 17.974 - 20.000 ) - Source Clock Delay (SCD): -2.412ns - Clock Pessimism Removal (CPR): -0.497ns - Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 - SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q - net (fo=4, routed) 1.044 -0.850 execution/Q[2] - SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O - net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 - SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O - net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O - net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] - SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O - net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] - DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) - 4.053 7.660 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 - DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.180 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 - SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O - net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 - SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X11Y34 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 10.904 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 10.904 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X11Y35 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.018 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.018 execution/alu/result0_inferred__11/i__carry__1_n_0 - SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[3]) - 0.313 11.331 r execution/alu/result0_inferred__11/i__carry__2/O[3] - net (fo=1, routed) 0.608 11.939 execution/alu/result0_inferred__11/i__carry__2_n_4 - SLICE_X15Y36 LUT6 (Prop_lut6_I5_O) 0.306 12.245 r execution/alu/MEM_ALU_result[31]_i_8/O - net (fo=1, routed) 0.403 12.648 execution/alu/MEM_ALU_result[31]_i_8_n_0 - SLICE_X15Y36 LUT6 (Prop_lut6_I5_O) 0.124 12.772 r execution/alu/MEM_ALU_result[31]_i_4/O - net (fo=1, routed) 0.000 12.772 execution/alu/MEM_ALU_result[31]_i_4_n_0 - SLICE_X15Y36 MUXF7 (Prop_muxf7_I1_O) 0.217 12.989 r execution/alu/MEM_ALU_result_reg[31]_i_1/O - net (fo=1, routed) 0.000 12.989 memory_access/prev_ALU_result[31] - SLICE_X15Y36 FDRE r memory_access/MEM_ALU_result_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 20.000 20.000 r - R4 0.000 20.000 r hardware_clk (IN) - net (fo=0) 0.000 20.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.445 17.974 memory_access/clk_out1 - SLICE_X15Y36 FDRE r memory_access/MEM_ALU_result_reg[31]/C - clock pessimism -0.497 17.477 - clock uncertainty -0.108 17.369 - SLICE_X15Y36 FDRE (Setup_fdre_C_D) 0.064 17.433 memory_access/MEM_ALU_result_reg[31] - ------------------------------------------------------------------- - required time 17.433 - arrival time -12.989 - ------------------------------------------------------------------- - slack 4.445 - -Slack (MET) : 4.467ns (required time - arrival time) - Source: execution/EX_rt_address_reg[2]/C +Slack (MET) : 3.380ns (required time - arrival time) + Source: write_back/WB_memory_read_data_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[22]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 15.375ns (logic 8.197ns (53.313%) route 7.178ns (46.687%)) - Logic Levels: 12 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) - Clock Path Skew: -0.114ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.029ns = ( 17.971 - 20.000 ) - Source Clock Delay (SCD): -2.412ns - Clock Pessimism Removal (CPR): -0.497ns + Data Path Delay: 16.542ns (logic 7.827ns (47.315%) route 8.715ns (52.685%)) + Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) + Clock Path Skew: -0.048ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.963ns = ( 18.037 - 20.000 ) + Source Clock Delay (SCD): -2.420ns + Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -1024,40 +825,38 @@ Slack (MET) : 4.467ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 - SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C + net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 + SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q - net (fo=4, routed) 1.044 -0.850 execution/Q[2] - SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O - net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 - SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O - net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O - net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] - SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O - net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] - DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) - 4.053 7.660 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 - DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.180 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 - SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O - net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 - SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X11Y34 CARRY4 (Prop_carry4_CI_O[2]) - 0.239 11.029 r execution/alu/result0_inferred__11/i__carry__0/O[2] - net (fo=1, routed) 0.555 11.584 execution/alu/result0_inferred__11/i__carry__0_n_5 - SLICE_X9Y35 LUT6 (Prop_lut6_I5_O) 0.302 11.886 r execution/alu/MEM_ALU_result[22]_i_6/O - net (fo=1, routed) 0.708 12.594 execution/alu/MEM_ALU_result[22]_i_6_n_0 - SLICE_X13Y32 LUT6 (Prop_lut6_I5_O) 0.124 12.718 r execution/alu/MEM_ALU_result[22]_i_3/O - net (fo=1, routed) 0.000 12.718 execution/alu/MEM_ALU_result[22]_i_3_n_0 - SLICE_X13Y32 MUXF7 (Prop_muxf7_I1_O) 0.245 12.963 r execution/alu/MEM_ALU_result_reg[22]_i_1/O - net (fo=1, routed) 0.000 12.963 memory_access/prev_ALU_result[22] - SLICE_X13Y32 FDRE r memory_access/MEM_ALU_result_reg[22]/D + SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q + net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] + SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O + net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] + SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.905 3.857 execution/result0__0_3 + SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O + net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] + DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.665 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 + DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 10.185 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 + SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 + SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X12Y17 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 11.988 r execution/alu/result0_inferred__11/i__carry__0/O[2] + net (fo=1, routed) 0.579 12.567 execution/alu/result0_inferred__11/i__carry__0_n_5 + SLICE_X7Y17 LUT4 (Prop_lut4_I3_O) 0.301 12.868 r execution/alu/MEM_ALU_result[22]_i_12/O + net (fo=1, routed) 0.565 13.433 execution/alu/MEM_ALU_result[22]_i_12_n_0 + SLICE_X1Y18 LUT6 (Prop_lut6_I5_O) 0.124 13.557 r execution/alu/MEM_ALU_result[22]_i_4/O + net (fo=1, routed) 0.441 13.998 execution/alu/MEM_ALU_result[22]_i_4_n_0 + SLICE_X2Y20 LUT6 (Prop_lut6_I3_O) 0.124 14.122 r execution/alu/MEM_ALU_result[22]_i_1/O + net (fo=1, routed) 0.000 14.122 memory_access/prev_ALU_result[22] + SLICE_X2Y20 FDRE r memory_access/MEM_ALU_result_reg[22]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1070,31 +869,31 @@ Slack (MET) : 4.467ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.442 17.971 memory_access/clk_out1 - SLICE_X13Y32 FDRE r memory_access/MEM_ALU_result_reg[22]/C - clock pessimism -0.497 17.474 - clock uncertainty -0.108 17.366 - SLICE_X13Y32 FDRE (Setup_fdre_C_D) 0.064 17.430 memory_access/MEM_ALU_result_reg[22] + net (fo=18132, routed) 1.508 18.037 memory_access/clk_out1 + SLICE_X2Y20 FDRE r memory_access/MEM_ALU_result_reg[22]/C + clock pessimism -0.505 17.532 + clock uncertainty -0.108 17.424 + SLICE_X2Y20 FDRE (Setup_fdre_C_D) 0.077 17.501 memory_access/MEM_ALU_result_reg[22] ------------------------------------------------------------------- - required time 17.430 - arrival time -12.963 + required time 17.501 + arrival time -14.122 ------------------------------------------------------------------- - slack 4.467 + slack 3.380 -Slack (MET) : 4.471ns (required time - arrival time) - Source: execution/EX_rt_address_reg[2]/C +Slack (MET) : 3.438ns (required time - arrival time) + Source: write_back/WB_memory_read_data_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[21]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 15.371ns (logic 8.265ns (53.769%) route 7.106ns (46.231%)) - Logic Levels: 12 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT5=1 LUT6=4 MUXF7=1) - Clock Path Skew: -0.114ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.029ns = ( 17.971 - 20.000 ) - Source Clock Delay (SCD): -2.412ns - Clock Pessimism Removal (CPR): -0.497ns + Data Path Delay: 16.488ns (logic 7.916ns (48.011%) route 8.572ns (51.989%)) + Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) + Clock Path Skew: -0.048ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.963ns = ( 18.037 - 20.000 ) + Source Clock Delay (SCD): -2.420ns + Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -1112,40 +911,38 @@ Slack (MET) : 4.471ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.564 -2.412 execution/clk_out1 - SLICE_X38Y7 FDRE r execution/EX_rt_address_reg[2]/C + net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 + SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y7 FDRE (Prop_fdre_C_Q) 0.518 -1.894 r execution/EX_rt_address_reg[2]/Q - net (fo=4, routed) 1.044 -0.850 execution/Q[2] - SLICE_X38Y10 LUT5 (Prop_lut5_I0_O) 0.124 -0.726 r execution/MEM_memory_write_data[31]_i_6/O - net (fo=2, routed) 0.576 -0.150 memory_access/IDB_source2__3 - SLICE_X37Y10 LUT6 (Prop_lut6_I5_O) 0.124 -0.026 r memory_access/MEM_memory_write_data[31]_i_2/O - net (fo=32, routed) 1.275 1.250 memory_access/MEM_memory_write_data[31]_i_2_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I1_O) 0.124 1.374 r memory_access/MEM_memory_write_data[9]_i_1/O - net (fo=9, routed) 1.307 2.680 execution/EX_memory_write_data[9] - SLICE_X15Y26 LUT3 (Prop_lut3_I1_O) 0.152 2.832 r execution/result0_i_23/O - net (fo=20, routed) 0.775 3.607 execution/alu/ALU_in2[9] - DSP48_X0Y11 DSP48E1 (Prop_dsp48e1_B[9]_PCOUT[47]) - 4.053 7.660 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 7.662 execution/alu/result0__0_n_106 - DSP48_X0Y12 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.180 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.936 10.116 execution/alu/result0__1_n_105 - SLICE_X11Y33 LUT2 (Prop_lut2_I0_O) 0.124 10.240 r execution/alu/i__carry_i_3__2/O - net (fo=1, routed) 0.000 10.240 execution/alu/i__carry_i_3__2_n_0 - SLICE_X11Y33 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 10.790 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 10.790 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X11Y34 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 11.124 r execution/alu/result0_inferred__11/i__carry__0/O[1] - net (fo=1, routed) 0.589 11.714 execution/alu/result0_inferred__11/i__carry__0_n_6 - SLICE_X8Y34 LUT6 (Prop_lut6_I5_O) 0.303 12.017 r execution/alu/MEM_ALU_result[21]_i_6/O - net (fo=1, routed) 0.602 12.618 execution/alu/MEM_ALU_result[21]_i_6_n_0 - SLICE_X13Y32 LUT6 (Prop_lut6_I5_O) 0.124 12.742 r execution/alu/MEM_ALU_result[21]_i_3/O - net (fo=1, routed) 0.000 12.742 execution/alu/MEM_ALU_result[21]_i_3_n_0 - SLICE_X13Y32 MUXF7 (Prop_muxf7_I1_O) 0.217 12.959 r execution/alu/MEM_ALU_result_reg[21]_i_1/O - net (fo=1, routed) 0.000 12.959 memory_access/prev_ALU_result[21] - SLICE_X13Y32 FDRE r memory_access/MEM_ALU_result_reg[21]/D + SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q + net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] + SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O + net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] + SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.905 3.857 execution/result0__0_3 + SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O + net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] + DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.665 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 + DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 10.185 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 + SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 + SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X12Y17 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 12.072 r execution/alu/result0_inferred__11/i__carry__0/O[1] + net (fo=1, routed) 0.697 12.769 execution/alu/result0_inferred__11/i__carry__0_n_6 + SLICE_X5Y17 LUT4 (Prop_lut4_I1_O) 0.306 13.075 r execution/alu/MEM_ALU_result[21]_i_12/O + net (fo=1, routed) 0.449 13.524 execution/alu/MEM_ALU_result[21]_i_12_n_0 + SLICE_X1Y19 LUT6 (Prop_lut6_I5_O) 0.124 13.648 r execution/alu/MEM_ALU_result[21]_i_4/O + net (fo=1, routed) 0.295 13.943 execution/alu/MEM_ALU_result[21]_i_4_n_0 + SLICE_X2Y19 LUT6 (Prop_lut6_I3_O) 0.124 14.067 r execution/alu/MEM_ALU_result[21]_i_1/O + net (fo=1, routed) 0.000 14.067 memory_access/prev_ALU_result[21] + SLICE_X2Y19 FDRE r memory_access/MEM_ALU_result_reg[21]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1158,16 +955,166 @@ Slack (MET) : 4.471ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.442 17.971 memory_access/clk_out1 - SLICE_X13Y32 FDRE r memory_access/MEM_ALU_result_reg[21]/C - clock pessimism -0.497 17.474 - clock uncertainty -0.108 17.366 - SLICE_X13Y32 FDRE (Setup_fdre_C_D) 0.064 17.430 memory_access/MEM_ALU_result_reg[21] + net (fo=18132, routed) 1.508 18.037 memory_access/clk_out1 + SLICE_X2Y19 FDRE r memory_access/MEM_ALU_result_reg[21]/C + clock pessimism -0.505 17.532 + clock uncertainty -0.108 17.424 + SLICE_X2Y19 FDRE (Setup_fdre_C_D) 0.081 17.505 memory_access/MEM_ALU_result_reg[21] ------------------------------------------------------------------- - required time 17.430 - arrival time -12.959 + required time 17.505 + arrival time -14.067 ------------------------------------------------------------------- - slack 4.471 + slack 3.438 + +Slack (MET) : 3.466ns (required time - arrival time) + Source: write_back/WB_memory_read_data_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: memory_access/MEM_ALU_result_reg[3]_rep__18/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 16.324ns (logic 5.041ns (30.880%) route 11.283ns (69.120%)) + Logic Levels: 7 (DSP48E1=1 LUT3=2 LUT6=4) + Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.034ns = ( 17.966 - 20.000 ) + Source Clock Delay (SCD): -2.420ns + Clock Pessimism Removal (CPR): -0.427ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 + SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q + net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] + SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O + net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] + SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.905 3.857 execution/result0__0_3 + SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O + net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] + DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_P[3]) + 3.841 8.470 r execution/alu/result0__0/P[3] + net (fo=1, routed) 0.752 9.223 execution/alu/result0__0_n_102 + SLICE_X10Y16 LUT6 (Prop_lut6_I1_O) 0.124 9.347 r execution/alu/MEM_ALU_result[3]_i_10/O + net (fo=1, routed) 0.452 9.799 execution/alu/MEM_ALU_result[3]_i_10_n_0 + SLICE_X9Y18 LUT6 (Prop_lut6_I5_O) 0.124 9.923 r execution/alu/MEM_ALU_result[3]_i_4/O + net (fo=34, routed) 3.289 13.212 execution/alu/MEM_ALU_result[3]_i_4_n_0 + SLICE_X43Y99 LUT6 (Prop_lut6_I3_O) 0.124 13.336 r execution/alu/MEM_ALU_result[3]_rep_i_1__18/O + net (fo=1, routed) 0.568 13.904 memory_access/MEM_ALU_result_reg[3]_rep__18_6 + SLICE_X43Y99 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__18/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 20.000 20.000 r + R4 0.000 20.000 r hardware_clk (IN) + net (fo=0) 0.000 20.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.438 17.966 memory_access/clk_out1 + SLICE_X43Y99 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__18/C + clock pessimism -0.427 17.540 + clock uncertainty -0.108 17.432 + SLICE_X43Y99 FDRE (Setup_fdre_C_D) -0.062 17.370 memory_access/MEM_ALU_result_reg[3]_rep__18 + ------------------------------------------------------------------- + required time 17.370 + arrival time -13.904 + ------------------------------------------------------------------- + slack 3.466 + +Slack (MET) : 3.484ns (required time - arrival time) + Source: write_back/WB_memory_read_data_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: memory_access/MEM_ALU_result_reg[3]_rep__25/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 16.404ns (logic 5.041ns (30.729%) route 11.363ns (69.271%)) + Logic Levels: 7 (DSP48E1=1 LUT3=2 LUT6=4) + Clock Path Skew: 0.063ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.859ns = ( 18.141 - 20.000 ) + Source Clock Delay (SCD): -2.420ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 + SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q + net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] + SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O + net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] + SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.905 3.857 execution/result0__0_3 + SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O + net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] + DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_P[3]) + 3.841 8.470 r execution/alu/result0__0/P[3] + net (fo=1, routed) 0.752 9.223 execution/alu/result0__0_n_102 + SLICE_X10Y16 LUT6 (Prop_lut6_I1_O) 0.124 9.347 r execution/alu/MEM_ALU_result[3]_i_10/O + net (fo=1, routed) 0.452 9.799 execution/alu/MEM_ALU_result[3]_i_10_n_0 + SLICE_X9Y18 LUT6 (Prop_lut6_I5_O) 0.124 9.923 r execution/alu/MEM_ALU_result[3]_i_4/O + net (fo=34, routed) 3.324 13.247 execution/alu/MEM_ALU_result[3]_i_4_n_0 + SLICE_X48Y104 LUT6 (Prop_lut6_I3_O) 0.124 13.371 r execution/alu/MEM_ALU_result[3]_rep_i_1__25/O + net (fo=1, routed) 0.613 13.984 memory_access/MEM_ALU_result_reg[3]_rep__25_2 + SLICE_X48Y104 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__25/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 20.000 20.000 r + R4 0.000 20.000 r hardware_clk (IN) + net (fo=0) 0.000 20.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.612 18.141 memory_access/clk_out1 + SLICE_X48Y104 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__25/C + clock pessimism -0.498 17.643 + clock uncertainty -0.108 17.535 + SLICE_X48Y104 FDRE (Setup_fdre_C_D) -0.067 17.468 memory_access/MEM_ALU_result_reg[3]_rep__25 + ------------------------------------------------------------------- + required time 17.468 + arrival time -13.984 + ------------------------------------------------------------------- + slack 3.484 @@ -1175,514 +1122,19 @@ Slack (MET) : 4.471ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.055ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[15]/C +Slack (MET) : 0.070ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[20]_rep__5/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435959][15]/D + Destination: data_memory/memory_data_reg[268435472][20]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.388ns (logic 0.141ns (36.319%) route 0.247ns (63.681%)) - Logic Levels: 0 - Clock Path Skew: 0.263ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.215ns - Source Clock Delay (SCD): -0.448ns - Clock Pessimism Removal (CPR): -0.030ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.639 -0.448 memory_access/clk_out1 - SLICE_X35Y112 FDRE r memory_access/MEM_memory_write_data_reg[15]/C - ------------------------------------------------------------------- ------------------- - SLICE_X35Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.307 r memory_access/MEM_memory_write_data_reg[15]/Q - net (fo=64, routed) 0.247 -0.059 data_memory/memory_data_reg[268435905][31]_0[15] - SLICE_X39Y114 FDRE r data_memory/memory_data_reg[268435959][15]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.911 -0.215 data_memory/clk_out1 - SLICE_X39Y114 FDRE r data_memory/memory_data_reg[268435959][15]/C - clock pessimism 0.030 -0.185 - SLICE_X39Y114 FDRE (Hold_fdre_C_D) 0.070 -0.115 data_memory/memory_data_reg[268435959][15] - ------------------------------------------------------------------- - required time 0.115 - arrival time -0.059 - ------------------------------------------------------------------- - slack 0.055 - -Slack (MET) : 0.063ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[15]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435932][15]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.398ns (logic 0.141ns (35.387%) route 0.257ns (64.613%)) - Logic Levels: 0 - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.212ns - Source Clock Delay (SCD): -0.448ns - Clock Pessimism Removal (CPR): -0.030ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.639 -0.448 memory_access/clk_out1 - SLICE_X35Y112 FDRE r memory_access/MEM_memory_write_data_reg[15]/C - ------------------------------------------------------------------- ------------------- - SLICE_X35Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.307 r memory_access/MEM_memory_write_data_reg[15]/Q - net (fo=64, routed) 0.257 -0.049 data_memory/memory_data_reg[268435905][31]_0[15] - SLICE_X39Y110 FDRE r data_memory/memory_data_reg[268435932][15]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.914 -0.212 data_memory/clk_out1 - SLICE_X39Y110 FDRE r data_memory/memory_data_reg[268435932][15]/C - clock pessimism 0.030 -0.182 - SLICE_X39Y110 FDRE (Hold_fdre_C_D) 0.070 -0.112 data_memory/memory_data_reg[268435932][15] - ------------------------------------------------------------------- - required time 0.112 - arrival time -0.049 - ------------------------------------------------------------------- - slack 0.063 - -Slack (MET) : 0.066ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[21]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435959][21]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.395ns (logic 0.141ns (35.729%) route 0.254ns (64.271%)) - Logic Levels: 0 - Clock Path Skew: 0.263ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.215ns - Source Clock Delay (SCD): -0.448ns - Clock Pessimism Removal (CPR): -0.030ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.639 -0.448 memory_access/clk_out1 - SLICE_X35Y112 FDRE r memory_access/MEM_memory_write_data_reg[21]/C - ------------------------------------------------------------------- ------------------- - SLICE_X35Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.307 r memory_access/MEM_memory_write_data_reg[21]/Q - net (fo=64, routed) 0.254 -0.053 data_memory/memory_data_reg[268435905][31]_0[21] - SLICE_X39Y114 FDRE r data_memory/memory_data_reg[268435959][21]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.911 -0.215 data_memory/clk_out1 - SLICE_X39Y114 FDRE r data_memory/memory_data_reg[268435959][21]/C - clock pessimism 0.030 -0.185 - SLICE_X39Y114 FDRE (Hold_fdre_C_D) 0.066 -0.119 data_memory/memory_data_reg[268435959][21] - ------------------------------------------------------------------- - required time 0.119 - arrival time -0.053 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.069ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[22]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435937][22]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.401ns (logic 0.141ns (35.127%) route 0.260ns (64.873%)) - Logic Levels: 0 - Clock Path Skew: 0.263ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.215ns - Source Clock Delay (SCD): -0.448ns - Clock Pessimism Removal (CPR): -0.030ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.639 -0.448 memory_access/clk_out1 - SLICE_X35Y112 FDRE r memory_access/MEM_memory_write_data_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X35Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.307 r memory_access/MEM_memory_write_data_reg[22]/Q - net (fo=64, routed) 0.260 -0.046 data_memory/memory_data_reg[268435905][31]_0[22] - SLICE_X36Y114 FDRE r data_memory/memory_data_reg[268435937][22]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.911 -0.215 data_memory/clk_out1 - SLICE_X36Y114 FDRE r data_memory/memory_data_reg[268435937][22]/C - clock pessimism 0.030 -0.185 - SLICE_X36Y114 FDRE (Hold_fdre_C_D) 0.070 -0.115 data_memory/memory_data_reg[268435937][22] - ------------------------------------------------------------------- - required time 0.115 - arrival time -0.046 - ------------------------------------------------------------------- - slack 0.069 - -Slack (MET) : 0.072ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[24]_rep__1/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435769][24]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.407ns (logic 0.141ns (34.609%) route 0.266ns (65.391%)) - Logic Levels: 0 - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.222ns - Source Clock Delay (SCD): -0.458ns - Clock Pessimism Removal (CPR): -0.030ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.629 -0.458 memory_access/clk_out1 - SLICE_X37Y125 FDRE r memory_access/MEM_memory_write_data_reg[24]_rep__1/C - ------------------------------------------------------------------- ------------------- - SLICE_X37Y125 FDRE (Prop_fdre_C_Q) 0.141 -0.317 r memory_access/MEM_memory_write_data_reg[24]_rep__1/Q - net (fo=64, routed) 0.266 -0.050 data_memory/memory_data_reg[268435713][31]_0[24] - SLICE_X32Y128 FDRE r data_memory/memory_data_reg[268435769][24]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.904 -0.222 data_memory/clk_out1 - SLICE_X32Y128 FDRE r data_memory/memory_data_reg[268435769][24]/C - clock pessimism 0.030 -0.192 - SLICE_X32Y128 FDRE (Hold_fdre_C_D) 0.070 -0.122 data_memory/memory_data_reg[268435769][24] - ------------------------------------------------------------------- - required time 0.122 - arrival time -0.050 - ------------------------------------------------------------------- - slack 0.072 - -Slack (MET) : 0.076ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[21]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435923][21]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.403ns (logic 0.141ns (34.960%) route 0.262ns (65.040%)) - Logic Levels: 0 - Clock Path Skew: 0.262ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.216ns - Source Clock Delay (SCD): -0.448ns - Clock Pessimism Removal (CPR): -0.030ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.639 -0.448 memory_access/clk_out1 - SLICE_X35Y112 FDRE r memory_access/MEM_memory_write_data_reg[21]/C - ------------------------------------------------------------------- ------------------- - SLICE_X35Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.307 r memory_access/MEM_memory_write_data_reg[21]/Q - net (fo=64, routed) 0.262 -0.044 data_memory/memory_data_reg[268435905][31]_0[21] - SLICE_X36Y115 FDRE r data_memory/memory_data_reg[268435923][21]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.910 -0.216 data_memory/clk_out1 - SLICE_X36Y115 FDRE r data_memory/memory_data_reg[268435923][21]/C - clock pessimism 0.030 -0.186 - SLICE_X36Y115 FDRE (Hold_fdre_C_D) 0.066 -0.120 data_memory/memory_data_reg[268435923][21] - ------------------------------------------------------------------- - required time 0.120 - arrival time -0.044 - ------------------------------------------------------------------- - slack 0.076 - -Slack (MET) : 0.078ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[16]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435941][16]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.403ns (logic 0.141ns (35.011%) route 0.262ns (64.989%)) - Logic Levels: 0 - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.212ns - Source Clock Delay (SCD): -0.448ns - Clock Pessimism Removal (CPR): -0.030ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.639 -0.448 memory_access/clk_out1 - SLICE_X35Y112 FDRE r memory_access/MEM_memory_write_data_reg[16]/C - ------------------------------------------------------------------- ------------------- - SLICE_X35Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.307 r memory_access/MEM_memory_write_data_reg[16]/Q - net (fo=64, routed) 0.262 -0.045 data_memory/memory_data_reg[268435905][31]_0[16] - SLICE_X38Y111 FDRE r data_memory/memory_data_reg[268435941][16]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.914 -0.212 data_memory/clk_out1 - SLICE_X38Y111 FDRE r data_memory/memory_data_reg[268435941][16]/C - clock pessimism 0.030 -0.182 - SLICE_X38Y111 FDRE (Hold_fdre_C_D) 0.059 -0.123 data_memory/memory_data_reg[268435941][16] - ------------------------------------------------------------------- - required time 0.123 - arrival time -0.045 - ------------------------------------------------------------------- - slack 0.078 - -Slack (MET) : 0.080ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[21]_rep/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435900][21]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.415ns (logic 0.141ns (33.997%) route 0.274ns (66.003%)) - Logic Levels: 0 - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.223ns - Source Clock Delay (SCD): -0.458ns - Clock Pessimism Removal (CPR): -0.030ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.629 -0.458 memory_access/clk_out1 - SLICE_X37Y125 FDRE r memory_access/MEM_memory_write_data_reg[21]_rep/C - ------------------------------------------------------------------- ------------------- - SLICE_X37Y125 FDRE (Prop_fdre_C_Q) 0.141 -0.317 r memory_access/MEM_memory_write_data_reg[21]_rep/Q - net (fo=64, routed) 0.274 -0.043 data_memory/memory_data_reg[268435841][31]_0[21] - SLICE_X35Y127 FDRE r data_memory/memory_data_reg[268435900][21]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.903 -0.223 data_memory/clk_out1 - SLICE_X35Y127 FDRE r data_memory/memory_data_reg[268435900][21]/C - clock pessimism 0.030 -0.193 - SLICE_X35Y127 FDRE (Hold_fdre_C_D) 0.070 -0.123 data_memory/memory_data_reg[268435900][21] - ------------------------------------------------------------------- - required time 0.123 - arrival time -0.043 - ------------------------------------------------------------------- - slack 0.080 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[18]_rep__0/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435832][18]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.420ns (logic 0.141ns (33.608%) route 0.279ns (66.392%)) + Data Path Delay: 0.411ns (logic 0.141ns (34.345%) route 0.270ns (65.655%)) Logic Levels: 0 Clock Path Skew: 0.269ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.219ns - Source Clock Delay (SCD): -0.458ns - Clock Pessimism Removal (CPR): -0.030ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.629 -0.458 memory_access/clk_out1 - SLICE_X37Y125 FDRE r memory_access/MEM_memory_write_data_reg[18]_rep__0/C - ------------------------------------------------------------------- ------------------- - SLICE_X37Y125 FDRE (Prop_fdre_C_Q) 0.141 -0.317 r memory_access/MEM_memory_write_data_reg[18]_rep__0/Q - net (fo=64, routed) 0.279 -0.038 data_memory/memory_data_reg[268435777][31]_0[18] - SLICE_X35Y131 FDRE r data_memory/memory_data_reg[268435832][18]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.907 -0.219 data_memory/clk_out1 - SLICE_X35Y131 FDRE r data_memory/memory_data_reg[268435832][18]/C - clock pessimism 0.030 -0.189 - SLICE_X35Y131 FDRE (Hold_fdre_C_D) 0.066 -0.123 data_memory/memory_data_reg[268435832][18] - ------------------------------------------------------------------- - required time 0.123 - arrival time -0.038 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.089ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[15]_rep__3/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435605][15]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.355ns (logic 0.128ns (36.020%) route 0.227ns (63.980%)) - Logic Levels: 0 - Clock Path Skew: 0.274ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.288ns - Source Clock Delay (SCD): -0.523ns + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.524ns Clock Pessimism Removal (CPR): -0.039ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1697,12 +1149,12 @@ Slack (MET) : 0.089ns (arrival time - required time) -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.564 -0.523 memory_access/clk_out1 - SLICE_X51Y54 FDRE r memory_access/MEM_memory_write_data_reg[15]_rep__3/C + net (fo=18132, routed) 0.563 -0.524 memory_access/clk_out1 + SLICE_X41Y46 FDRE r memory_access/MEM_memory_write_data_reg[20]_rep__5/C ------------------------------------------------------------------- ------------------- - SLICE_X51Y54 FDRE (Prop_fdre_C_Q) 0.128 -0.395 r memory_access/MEM_memory_write_data_reg[15]_rep__3/Q - net (fo=64, routed) 0.227 -0.168 data_memory/memory_data_reg[268435585][31]_0[15] - SLICE_X55Y49 FDRE r data_memory/memory_data_reg[268435605][15]/D + SLICE_X41Y46 FDRE (Prop_fdre_C_Q) 0.141 -0.383 r memory_access/MEM_memory_write_data_reg[20]_rep__5/Q + net (fo=64, routed) 0.270 -0.114 data_memory/memory_data_reg[268435457][31]_0[20] + SLICE_X43Y51 FDRE r data_memory/memory_data_reg[268435472][20]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1715,15 +1167,512 @@ Slack (MET) : 0.089ns (arrival time - required time) -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.838 -0.288 data_memory/clk_out1 - SLICE_X55Y49 FDRE r data_memory/memory_data_reg[268435605][15]/C - clock pessimism 0.039 -0.249 - SLICE_X55Y49 FDRE (Hold_fdre_C_D) -0.008 -0.257 data_memory/memory_data_reg[268435605][15] + net (fo=18132, routed) 0.832 -0.294 data_memory/clk_out1 + SLICE_X43Y51 FDRE r data_memory/memory_data_reg[268435472][20]/C + clock pessimism 0.039 -0.255 + SLICE_X43Y51 FDRE (Hold_fdre_C_D) 0.072 -0.183 data_memory/memory_data_reg[268435472][20] ------------------------------------------------------------------- - required time 0.257 - arrival time -0.168 + required time 0.183 + arrival time -0.114 ------------------------------------------------------------------- - slack 0.089 + slack 0.070 + +Slack (MET) : 0.079ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[25]/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435951][25]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.313ns (logic 0.141ns (45.059%) route 0.172ns (54.941%)) + Logic Levels: 0 + Clock Path Skew: 0.182ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.291ns + Source Clock Delay (SCD): -0.440ns + Clock Pessimism Removal (CPR): -0.034ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.647 -0.440 memory_access/clk_out1 + SLICE_X15Y100 FDRE r memory_access/MEM_memory_write_data_reg[25]/C + ------------------------------------------------------------------- ------------------- + SLICE_X15Y100 FDRE (Prop_fdre_C_Q) 0.141 -0.299 r memory_access/MEM_memory_write_data_reg[25]/Q + net (fo=64, routed) 0.172 -0.127 data_memory/memory_data_reg[268435905][31]_0[25] + SLICE_X14Y98 FDRE r data_memory/memory_data_reg[268435951][25]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.834 -0.291 data_memory/clk_out1 + SLICE_X14Y98 FDRE r data_memory/memory_data_reg[268435951][25]/C + clock pessimism 0.034 -0.257 + SLICE_X14Y98 FDRE (Hold_fdre_C_D) 0.052 -0.205 data_memory/memory_data_reg[268435951][25] + ------------------------------------------------------------------- + required time 0.205 + arrival time -0.127 + ------------------------------------------------------------------- + slack 0.079 + +Slack (MET) : 0.080ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[0]_rep__4/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435548][0]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.164ns (39.691%) route 0.249ns (60.309%)) + Logic Levels: 0 + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.299ns + Source Clock Delay (SCD): -0.528ns + Clock Pessimism Removal (CPR): -0.034ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.559 -0.528 memory_access/clk_out1 + SLICE_X38Y36 FDRE r memory_access/MEM_memory_write_data_reg[0]_rep__4/C + ------------------------------------------------------------------- ------------------- + SLICE_X38Y36 FDRE (Prop_fdre_C_Q) 0.164 -0.364 r memory_access/MEM_memory_write_data_reg[0]_rep__4/Q + net (fo=64, routed) 0.249 -0.115 data_memory/memory_data_reg[268435521][31]_0[0] + SLICE_X35Y37 FDRE r data_memory/memory_data_reg[268435548][0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.827 -0.299 data_memory/clk_out1 + SLICE_X35Y37 FDRE r data_memory/memory_data_reg[268435548][0]/C + clock pessimism 0.034 -0.265 + SLICE_X35Y37 FDRE (Hold_fdre_C_D) 0.070 -0.195 data_memory/memory_data_reg[268435548][0] + ------------------------------------------------------------------- + required time 0.195 + arrival time -0.115 + ------------------------------------------------------------------- + slack 0.080 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[31]_rep__4/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435541][31]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.414ns (logic 0.164ns (39.608%) route 0.250ns (60.392%)) + Logic Levels: 0 + Clock Path Skew: 0.262ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.300ns + Source Clock Delay (SCD): -0.528ns + Clock Pessimism Removal (CPR): -0.034ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.559 -0.528 memory_access/clk_out1 + SLICE_X38Y36 FDRE r memory_access/MEM_memory_write_data_reg[31]_rep__4/C + ------------------------------------------------------------------- ------------------- + SLICE_X38Y36 FDRE (Prop_fdre_C_Q) 0.164 -0.364 r memory_access/MEM_memory_write_data_reg[31]_rep__4/Q + net (fo=64, routed) 0.250 -0.114 data_memory/memory_data_reg[268435521][31]_0[31] + SLICE_X35Y36 FDRE r data_memory/memory_data_reg[268435541][31]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.826 -0.300 data_memory/clk_out1 + SLICE_X35Y36 FDRE r data_memory/memory_data_reg[268435541][31]/C + clock pessimism 0.034 -0.266 + SLICE_X35Y36 FDRE (Hold_fdre_C_D) 0.066 -0.200 data_memory/memory_data_reg[268435541][31] + ------------------------------------------------------------------- + required time 0.200 + arrival time -0.114 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.092ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[31]_rep__4/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435548][31]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.425ns (logic 0.164ns (38.560%) route 0.261ns (61.440%)) + Logic Levels: 0 + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.299ns + Source Clock Delay (SCD): -0.528ns + Clock Pessimism Removal (CPR): -0.034ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.559 -0.528 memory_access/clk_out1 + SLICE_X38Y36 FDRE r memory_access/MEM_memory_write_data_reg[31]_rep__4/C + ------------------------------------------------------------------- ------------------- + SLICE_X38Y36 FDRE (Prop_fdre_C_Q) 0.164 -0.364 r memory_access/MEM_memory_write_data_reg[31]_rep__4/Q + net (fo=64, routed) 0.261 -0.103 data_memory/memory_data_reg[268435521][31]_0[31] + SLICE_X35Y37 FDRE r data_memory/memory_data_reg[268435548][31]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.827 -0.299 data_memory/clk_out1 + SLICE_X35Y37 FDRE r data_memory/memory_data_reg[268435548][31]/C + clock pessimism 0.034 -0.265 + SLICE_X35Y37 FDRE (Hold_fdre_C_D) 0.070 -0.195 data_memory/memory_data_reg[268435548][31] + ------------------------------------------------------------------- + required time 0.195 + arrival time -0.103 + ------------------------------------------------------------------- + slack 0.092 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: instruction_decode/IFID_PC_plus_4_reg[21]/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: instruction_decode/register_file/registers_reg[10][21]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.447ns (logic 0.186ns (41.615%) route 0.261ns (58.385%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.262ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.301ns + Source Clock Delay (SCD): -0.529ns + Clock Pessimism Removal (CPR): -0.034ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.558 -0.529 instruction_decode/clk_out1 + SLICE_X28Y16 FDRE r instruction_decode/IFID_PC_plus_4_reg[21]/C + ------------------------------------------------------------------- ------------------- + SLICE_X28Y16 FDRE (Prop_fdre_C_Q) 0.141 -0.388 r instruction_decode/IFID_PC_plus_4_reg[21]/Q + net (fo=39, routed) 0.261 -0.127 write_back/registers_reg[3][31][21] + SLICE_X39Y16 LUT6 (Prop_lut6_I3_O) 0.045 -0.082 r write_back/registers[10][21]_i_1/O + net (fo=1, routed) 0.000 -0.082 instruction_decode/register_file/registers_reg[10][31]_0[21] + SLICE_X39Y16 FDRE r instruction_decode/register_file/registers_reg[10][21]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.825 -0.301 instruction_decode/register_file/clk_out1 + SLICE_X39Y16 FDRE r instruction_decode/register_file/registers_reg[10][21]/C + clock pessimism 0.034 -0.267 + SLICE_X39Y16 FDRE (Hold_fdre_C_D) 0.092 -0.175 instruction_decode/register_file/registers_reg[10][21] + ------------------------------------------------------------------- + required time 0.175 + arrival time -0.082 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[6]_rep__0/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435776][6]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.379ns (logic 0.128ns (33.753%) route 0.251ns (66.247%)) + Logic Levels: 0 + Clock Path Skew: 0.269ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.524ns + Clock Pessimism Removal (CPR): -0.039ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.563 -0.524 memory_access/clk_out1 + SLICE_X31Y44 FDRE r memory_access/MEM_memory_write_data_reg[6]_rep__0/C + ------------------------------------------------------------------- ------------------- + SLICE_X31Y44 FDRE (Prop_fdre_C_Q) 0.128 -0.396 r memory_access/MEM_memory_write_data_reg[6]_rep__0/Q + net (fo=64, routed) 0.251 -0.145 data_memory/memory_data_reg[268435777][31]_0[6] + SLICE_X28Y51 FDRE r data_memory/memory_data_reg[268435776][6]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.832 -0.294 data_memory/clk_out1 + SLICE_X28Y51 FDRE r data_memory/memory_data_reg[268435776][6]/C + clock pessimism 0.039 -0.255 + SLICE_X28Y51 FDRE (Hold_fdre_C_D) 0.017 -0.238 data_memory/memory_data_reg[268435776][6] + ------------------------------------------------------------------- + required time 0.238 + arrival time -0.145 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.094ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[7]_rep__2/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435711][7]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.373ns (logic 0.128ns (34.278%) route 0.245ns (65.722%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.222ns + Source Clock Delay (SCD): -0.453ns + Clock Pessimism Removal (CPR): -0.030ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.634 -0.453 memory_access/clk_out1 + SLICE_X32Y129 FDRE r memory_access/MEM_memory_write_data_reg[7]_rep__2/C + ------------------------------------------------------------------- ------------------- + SLICE_X32Y129 FDRE (Prop_fdre_C_Q) 0.128 -0.325 r memory_access/MEM_memory_write_data_reg[7]_rep__2/Q + net (fo=64, routed) 0.245 -0.079 data_memory/memory_data_reg[268435649][31]_0[7] + SLICE_X37Y128 FDRE r data_memory/memory_data_reg[268435711][7]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.904 -0.222 data_memory/clk_out1 + SLICE_X37Y128 FDRE r data_memory/memory_data_reg[268435711][7]/C + clock pessimism 0.030 -0.192 + SLICE_X37Y128 FDRE (Hold_fdre_C_D) 0.019 -0.173 data_memory/memory_data_reg[268435711][7] + ------------------------------------------------------------------- + required time 0.173 + arrival time -0.079 + ------------------------------------------------------------------- + slack 0.094 + +Slack (MET) : 0.097ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[7]_rep__2/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435708][7]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.376ns (logic 0.128ns (34.010%) route 0.248ns (65.990%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.222ns + Source Clock Delay (SCD): -0.453ns + Clock Pessimism Removal (CPR): -0.030ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.634 -0.453 memory_access/clk_out1 + SLICE_X32Y129 FDRE r memory_access/MEM_memory_write_data_reg[7]_rep__2/C + ------------------------------------------------------------------- ------------------- + SLICE_X32Y129 FDRE (Prop_fdre_C_Q) 0.128 -0.325 r memory_access/MEM_memory_write_data_reg[7]_rep__2/Q + net (fo=64, routed) 0.248 -0.076 data_memory/memory_data_reg[268435649][31]_0[7] + SLICE_X36Y128 FDRE r data_memory/memory_data_reg[268435708][7]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.904 -0.222 data_memory/clk_out1 + SLICE_X36Y128 FDRE r data_memory/memory_data_reg[268435708][7]/C + clock pessimism 0.030 -0.192 + SLICE_X36Y128 FDRE (Hold_fdre_C_D) 0.019 -0.173 data_memory/memory_data_reg[268435708][7] + ------------------------------------------------------------------- + required time 0.173 + arrival time -0.076 + ------------------------------------------------------------------- + slack 0.097 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[5]_rep__1/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435761][5]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.433ns (logic 0.141ns (32.546%) route 0.292ns (67.454%)) + Logic Levels: 0 + Clock Path Skew: 0.255ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.312ns + Source Clock Delay (SCD): -0.533ns + Clock Pessimism Removal (CPR): -0.034ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.554 -0.533 memory_access/clk_out1 + SLICE_X36Y81 FDRE r memory_access/MEM_memory_write_data_reg[5]_rep__1/C + ------------------------------------------------------------------- ------------------- + SLICE_X36Y81 FDRE (Prop_fdre_C_Q) 0.141 -0.392 r memory_access/MEM_memory_write_data_reg[5]_rep__1/Q + net (fo=64, routed) 0.292 -0.100 data_memory/memory_data_reg[268435713][31]_0[5] + SLICE_X32Y75 FDRE r data_memory/memory_data_reg[268435761][5]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.813 -0.312 data_memory/clk_out1 + SLICE_X32Y75 FDRE r data_memory/memory_data_reg[268435761][5]/C + clock pessimism 0.034 -0.278 + SLICE_X32Y75 FDRE (Hold_fdre_C_D) 0.070 -0.208 data_memory/memory_data_reg[268435761][5] + ------------------------------------------------------------------- + required time 0.208 + arrival time -0.100 + ------------------------------------------------------------------- + slack 0.108 @@ -1739,35 +1688,35 @@ Sources: { pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y0 pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 20.000 18.751 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKOUT0 -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X58Y77 data_memory/memory_data_reg[268435456][0]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X37Y56 data_memory/memory_data_reg[268435456][10]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X10Y58 data_memory/memory_data_reg[268435456][11]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X57Y56 data_memory/memory_data_reg[268435456][12]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X37Y56 data_memory/memory_data_reg[268435456][13]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X37Y75 data_memory/memory_data_reg[268435456][14]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X58Y77 data_memory/memory_data_reg[268435456][15]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X44Y77 data_memory/memory_data_reg[268435456][16]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X32Y31 data_memory/memory_data_reg[268435456][14]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X32Y31 data_memory/memory_data_reg[268435456][15]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X48Y54 data_memory/memory_data_reg[268435456][16]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 20.000 140.000 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKOUT0 -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X58Y77 data_memory/memory_data_reg[268435456][0]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X58Y77 data_memory/memory_data_reg[268435456][0]/C -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][10]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][10]/C -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X10Y58 data_memory/memory_data_reg[268435456][11]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X10Y58 data_memory/memory_data_reg[268435456][11]/C -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X57Y56 data_memory/memory_data_reg[268435456][12]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X57Y56 data_memory/memory_data_reg[268435456][12]/C -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][13]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][13]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X58Y77 data_memory/memory_data_reg[268435456][0]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X58Y77 data_memory/memory_data_reg[268435456][0]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][10]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][10]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X10Y58 data_memory/memory_data_reg[268435456][11]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X10Y58 data_memory/memory_data_reg[268435456][11]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X57Y56 data_memory/memory_data_reg[268435456][12]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X57Y56 data_memory/memory_data_reg[268435456][12]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][13]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X37Y56 data_memory/memory_data_reg[268435456][13]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C @@ -1810,13 +1759,13 @@ Min Delay 12 Endpoints Max Delay Paths -------------------------------------------------------------------------------------- Slack: inf - Source: data_memory/memory_data_reg[268435460][8]_lopt_replica/C + Source: data_memory/memory_data_reg[268435460][0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[8] + Destination: bcd_control[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 7.652ns (logic 4.162ns (54.388%) route 3.490ns (45.612%)) + Data Path Delay: 6.786ns (logic 3.997ns (58.900%) route 2.789ns (41.100%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -1835,14 +1784,14 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.553 -2.423 data_memory/clk_out1 - SLICE_X36Y56 FDRE r data_memory/memory_data_reg[268435460][8]_lopt_replica/C + net (fo=18132, routed) 1.566 -2.410 data_memory/clk_out1 + SLICE_X45Y42 FDRE r data_memory/memory_data_reg[268435460][0]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X36Y56 FDRE (Prop_fdre_C_Q) 0.419 -2.004 r data_memory/memory_data_reg[268435460][8]_lopt_replica/Q - net (fo=1, routed) 3.490 1.486 lopt_10 - Y3 OBUF (Prop_obuf_I_O) 3.743 5.228 r bcd_control_OBUF[8]_inst/O - net (fo=0) 0.000 5.228 bcd_control[8] - Y3 r bcd_control[8] (OUT) + SLICE_X45Y42 FDRE (Prop_fdre_C_Q) 0.456 -1.954 r data_memory/memory_data_reg[268435460][0]_lopt_replica/Q + net (fo=1, routed) 2.789 0.835 lopt + N2 OBUF (Prop_obuf_I_O) 3.541 4.376 r bcd_control_OBUF[0]_inst/O + net (fo=0) 0.000 4.376 bcd_control[0] + N2 r bcd_control[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -1852,7 +1801,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 7.408ns (logic 4.054ns (54.728%) route 3.354ns (45.272%)) + Data Path Delay: 6.606ns (logic 3.992ns (60.431%) route 2.614ns (39.569%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -1871,24 +1820,24 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.550 -2.426 data_memory/clk_out1 - SLICE_X10Y65 FDRE r data_memory/memory_data_reg[268435460][11]_lopt_replica/C + net (fo=18132, routed) 1.637 -2.339 data_memory/clk_out1 + SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][11]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X10Y65 FDRE (Prop_fdre_C_Q) 0.518 -1.908 r data_memory/memory_data_reg[268435460][11]_lopt_replica/Q - net (fo=1, routed) 3.354 1.445 lopt_2 - M2 OBUF (Prop_obuf_I_O) 3.536 4.982 r bcd_control_OBUF[11]_inst/O - net (fo=0) 0.000 4.982 bcd_control[11] + SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.456 -1.883 r data_memory/memory_data_reg[268435460][11]_lopt_replica/Q + net (fo=1, routed) 2.614 0.731 lopt_2 + M2 OBUF (Prop_obuf_I_O) 3.536 4.267 r bcd_control_OBUF[11]_inst/O + net (fo=0) 0.000 4.267 bcd_control[11] M2 r bcd_control[11] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: data_memory/memory_data_reg[268435460][2]_lopt_replica/C + Source: data_memory/memory_data_reg[268435460][8]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[2] + Destination: bcd_control[8] (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 7.111ns (logic 3.983ns (56.015%) route 3.128ns (43.985%)) + Data Path Delay: 6.536ns (logic 4.160ns (63.646%) route 2.376ns (36.354%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -1907,230 +1856,14 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.626 -2.350 data_memory/clk_out1 - SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][2]_lopt_replica/C + net (fo=18132, routed) 1.551 -2.425 data_memory/clk_out1 + SLICE_X51Y24 FDRE r data_memory/memory_data_reg[268435460][8]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.456 -1.894 r data_memory/memory_data_reg[268435460][2]_lopt_replica/Q - net (fo=1, routed) 3.128 1.233 lopt_4 - V5 OBUF (Prop_obuf_I_O) 3.527 4.760 r bcd_control_OBUF[2]_inst/O - net (fo=0) 0.000 4.760 bcd_control[2] - V5 r bcd_control[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][3]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[3] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 7.072ns (logic 4.150ns (58.677%) route 2.922ns (41.323%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.626 -2.350 data_memory/clk_out1 - SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.419 -1.931 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q - net (fo=1, routed) 2.922 0.991 lopt_5 - U5 OBUF (Prop_obuf_I_O) 3.731 4.722 r bcd_control_OBUF[3]_inst/O - net (fo=0) 0.000 4.722 bcd_control[3] - U5 r bcd_control[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][4]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[4] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 6.913ns (logic 4.147ns (59.987%) route 2.766ns (40.013%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.626 -2.350 data_memory/clk_out1 - SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.419 -1.931 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q - net (fo=1, routed) 2.766 0.835 lopt_6 - T5 OBUF (Prop_obuf_I_O) 3.728 4.563 r bcd_control_OBUF[4]_inst/O - net (fo=0) 0.000 4.563 bcd_control[4] - T5 r bcd_control[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][6]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[6] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 6.854ns (logic 4.148ns (60.513%) route 2.706ns (39.487%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.626 -2.350 data_memory/clk_out1 - SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.419 -1.931 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q - net (fo=1, routed) 2.706 0.775 lopt_8 - W4 OBUF (Prop_obuf_I_O) 3.729 4.504 r bcd_control_OBUF[6]_inst/O - net (fo=0) 0.000 4.504 bcd_control[6] - W4 r bcd_control[6] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][7]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[7] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 6.714ns (logic 4.006ns (59.673%) route 2.708ns (40.327%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.559 -2.417 data_memory/clk_out1 - SLICE_X55Y56 FDRE r data_memory/memory_data_reg[268435460][7]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X55Y56 FDRE (Prop_fdre_C_Q) 0.456 -1.961 r data_memory/memory_data_reg[268435460][7]_lopt_replica/Q - net (fo=1, routed) 2.708 0.746 lopt_9 - V3 OBUF (Prop_obuf_I_O) 3.550 4.297 r bcd_control_OBUF[7]_inst/O - net (fo=0) 0.000 4.297 bcd_control[7] - V3 r bcd_control[7] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][0]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[0] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 6.587ns (logic 4.059ns (61.625%) route 2.528ns (38.375%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.542 -2.434 data_memory/clk_out1 - SLICE_X56Y72 FDRE r data_memory/memory_data_reg[268435460][0]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X56Y72 FDRE (Prop_fdre_C_Q) 0.518 -1.916 r data_memory/memory_data_reg[268435460][0]_lopt_replica/Q - net (fo=1, routed) 2.528 0.611 lopt - N2 OBUF (Prop_obuf_I_O) 3.541 4.152 r bcd_control_OBUF[0]_inst/O - net (fo=0) 0.000 4.152 bcd_control[0] - N2 r bcd_control[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][5]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[5] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 6.129ns (logic 4.014ns (65.490%) route 2.115ns (34.510%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.559 -2.417 data_memory/clk_out1 - SLICE_X55Y56 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X55Y56 FDRE (Prop_fdre_C_Q) 0.456 -1.961 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q - net (fo=1, routed) 2.115 0.154 lopt_7 - P1 OBUF (Prop_obuf_I_O) 3.558 3.712 r bcd_control_OBUF[5]_inst/O - net (fo=0) 0.000 3.712 bcd_control[5] - P1 r bcd_control[5] (OUT) + SLICE_X51Y24 FDRE (Prop_fdre_C_Q) 0.419 -2.006 r data_memory/memory_data_reg[268435460][8]_lopt_replica/Q + net (fo=1, routed) 2.376 0.370 lopt_10 + Y3 OBUF (Prop_obuf_I_O) 3.741 4.111 r bcd_control_OBUF[8]_inst/O + net (fo=0) 0.000 4.111 bcd_control[8] + Y3 r bcd_control[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -2140,7 +1873,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 5.813ns (logic 4.016ns (69.089%) route 1.797ns (30.911%)) + Data Path Delay: 6.422ns (logic 4.016ns (62.541%) route 2.406ns (37.459%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2159,16 +1892,232 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.624 -2.352 data_memory/clk_out1 - SLICE_X62Y59 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C + net (fo=18132, routed) 1.637 -2.339 data_memory/clk_out1 + SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X62Y59 FDRE (Prop_fdre_C_Q) 0.456 -1.896 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q - net (fo=1, routed) 1.797 -0.099 lopt_11 - R1 OBUF (Prop_obuf_I_O) 3.560 3.461 r bcd_control_OBUF[9]_inst/O - net (fo=0) 0.000 3.461 bcd_control[9] + SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.456 -1.883 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q + net (fo=1, routed) 2.406 0.523 lopt_11 + R1 OBUF (Prop_obuf_I_O) 3.560 4.083 r bcd_control_OBUF[9]_inst/O + net (fo=0) 0.000 4.083 bcd_control[9] R1 r bcd_control[9] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: data_memory/memory_data_reg[268435460][5]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[5] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 6.274ns (logic 4.014ns (63.978%) route 2.260ns (36.022%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.637 -2.339 data_memory/clk_out1 + SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.456 -1.883 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q + net (fo=1, routed) 2.260 0.377 lopt_7 + P1 OBUF (Prop_obuf_I_O) 3.558 3.935 r bcd_control_OBUF[5]_inst/O + net (fo=0) 0.000 3.935 bcd_control[5] + P1 r bcd_control[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][3]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[3] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 6.329ns (logic 4.012ns (63.387%) route 2.317ns (36.613%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.551 -2.425 data_memory/clk_out1 + SLICE_X51Y24 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y24 FDRE (Prop_fdre_C_Q) 0.456 -1.969 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q + net (fo=1, routed) 2.317 0.348 lopt_5 + U5 OBUF (Prop_obuf_I_O) 3.556 3.904 r bcd_control_OBUF[3]_inst/O + net (fo=0) 0.000 3.904 bcd_control[3] + U5 r bcd_control[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][1]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[1] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 6.098ns (logic 3.991ns (65.436%) route 2.108ns (34.564%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.637 -2.339 data_memory/clk_out1 + SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][1]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.456 -1.883 r data_memory/memory_data_reg[268435460][1]_lopt_replica/Q + net (fo=1, routed) 2.108 0.225 lopt_3 + P5 OBUF (Prop_obuf_I_O) 3.535 3.759 r bcd_control_OBUF[1]_inst/O + net (fo=0) 0.000 3.759 bcd_control[1] + P5 r bcd_control[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][6]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[6] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 6.088ns (logic 4.010ns (65.856%) route 2.079ns (34.144%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.635 -2.341 data_memory/clk_out1 + SLICE_X65Y38 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y38 FDRE (Prop_fdre_C_Q) 0.456 -1.885 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q + net (fo=1, routed) 2.079 0.194 lopt_8 + W4 OBUF (Prop_obuf_I_O) 3.554 3.747 r bcd_control_OBUF[6]_inst/O + net (fo=0) 0.000 3.747 bcd_control[6] + W4 r bcd_control[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][10]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[10] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 6.059ns (logic 4.000ns (66.015%) route 2.059ns (33.985%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.638 -2.338 data_memory/clk_out1 + SLICE_X65Y46 FDRE r data_memory/memory_data_reg[268435460][10]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y46 FDRE (Prop_fdre_C_Q) 0.456 -1.882 r data_memory/memory_data_reg[268435460][10]_lopt_replica/Q + net (fo=1, routed) 2.059 0.177 lopt_1 + P2 OBUF (Prop_obuf_I_O) 3.544 3.721 r bcd_control_OBUF[10]_inst/O + net (fo=0) 0.000 3.721 bcd_control[10] + P2 r bcd_control[10] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][4]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[4] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 5.732ns (logic 4.011ns (69.973%) route 1.721ns (30.027%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.630 -2.346 data_memory/clk_out1 + SLICE_X65Y16 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y16 FDRE (Prop_fdre_C_Q) 0.456 -1.890 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q + net (fo=1, routed) 1.721 -0.169 lopt_6 + T5 OBUF (Prop_obuf_I_O) 3.555 3.386 r bcd_control_OBUF[4]_inst/O + net (fo=0) 0.000 3.386 bcd_control[4] + T5 r bcd_control[4] (OUT) + ------------------------------------------------------------------- ------------------- + @@ -2176,13 +2125,13 @@ Slack: inf Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf - Source: data_memory/memory_data_reg[268435460][10]_lopt_replica/C + Source: data_memory/memory_data_reg[268435460][2]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[10] + Destination: bcd_control[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 1.716ns (logic 1.386ns (80.750%) route 0.330ns (19.250%)) + Data Path Delay: 1.697ns (logic 1.369ns (80.669%) route 0.328ns (19.331%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2201,158 +2150,14 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.593 -0.494 data_memory/clk_out1 - SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][10]_lopt_replica/C + net (fo=18132, routed) 0.590 -0.497 data_memory/clk_out1 + SLICE_X65Y16 FDRE r data_memory/memory_data_reg[268435460][2]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][10]_lopt_replica/Q - net (fo=1, routed) 0.330 -0.023 lopt_1 - P2 OBUF (Prop_obuf_I_O) 1.245 1.222 r bcd_control_OBUF[10]_inst/O - net (fo=0) 0.000 1.222 bcd_control[10] - P2 r bcd_control[10] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][1]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[1] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.726ns (logic 1.376ns (79.733%) route 0.350ns (20.267%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.593 -0.494 data_memory/clk_out1 - SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][1]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][1]_lopt_replica/Q - net (fo=1, routed) 0.350 -0.003 lopt_3 - P5 OBUF (Prop_obuf_I_O) 1.235 1.232 r bcd_control_OBUF[1]_inst/O - net (fo=0) 0.000 1.232 bcd_control[1] - P5 r bcd_control[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][9]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[9] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.783ns (logic 1.402ns (78.632%) route 0.381ns (21.368%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.592 -0.495 data_memory/clk_out1 - SLICE_X62Y59 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X62Y59 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q - net (fo=1, routed) 0.381 0.027 lopt_11 - R1 OBUF (Prop_obuf_I_O) 1.261 1.288 r bcd_control_OBUF[9]_inst/O - net (fo=0) 0.000 1.288 bcd_control[9] - R1 r bcd_control[9] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][5]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[5] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.961ns (logic 1.400ns (71.380%) route 0.561ns (28.620%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.564 -0.523 data_memory/clk_out1 - SLICE_X55Y56 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X55Y56 FDRE (Prop_fdre_C_Q) 0.141 -0.382 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q - net (fo=1, routed) 0.561 0.179 lopt_7 - P1 OBUF (Prop_obuf_I_O) 1.259 1.438 r bcd_control_OBUF[5]_inst/O - net (fo=0) 0.000 1.438 bcd_control[5] - P1 r bcd_control[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][0]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[0] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.124ns (logic 1.406ns (66.173%) route 0.719ns (33.827%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.556 -0.531 data_memory/clk_out1 - SLICE_X56Y72 FDRE r data_memory/memory_data_reg[268435460][0]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X56Y72 FDRE (Prop_fdre_C_Q) 0.164 -0.367 r data_memory/memory_data_reg[268435460][0]_lopt_replica/Q - net (fo=1, routed) 0.719 0.351 lopt - N2 OBUF (Prop_obuf_I_O) 1.242 1.593 r bcd_control_OBUF[0]_inst/O - net (fo=0) 0.000 1.593 bcd_control[0] - N2 r bcd_control[0] (OUT) + SLICE_X65Y16 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r data_memory/memory_data_reg[268435460][2]_lopt_replica/Q + net (fo=1, routed) 0.328 -0.028 lopt_4 + V5 OBUF (Prop_obuf_I_O) 1.228 1.200 r bcd_control_OBUF[2]_inst/O + net (fo=0) 0.000 1.200 bcd_control[2] + V5 r bcd_control[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -2362,7 +2167,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.218ns (logic 1.392ns (62.774%) route 0.826ns (37.226%)) + Data Path Delay: 1.727ns (logic 1.392ns (80.615%) route 0.335ns (19.385%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2381,52 +2186,16 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.564 -0.523 data_memory/clk_out1 - SLICE_X55Y56 FDRE r data_memory/memory_data_reg[268435460][7]_lopt_replica/C + net (fo=18132, routed) 0.593 -0.494 data_memory/clk_out1 + SLICE_X65Y38 FDRE r data_memory/memory_data_reg[268435460][7]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X55Y56 FDRE (Prop_fdre_C_Q) 0.141 -0.382 r data_memory/memory_data_reg[268435460][7]_lopt_replica/Q - net (fo=1, routed) 0.826 0.443 lopt_9 - V3 OBUF (Prop_obuf_I_O) 1.251 1.695 r bcd_control_OBUF[7]_inst/O - net (fo=0) 0.000 1.695 bcd_control[7] + SLICE_X65Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][7]_lopt_replica/Q + net (fo=1, routed) 0.335 -0.018 lopt_9 + V3 OBUF (Prop_obuf_I_O) 1.251 1.233 r bcd_control_OBUF[7]_inst/O + net (fo=0) 0.000 1.233 bcd_control[7] V3 r bcd_control[7] (OUT) ------------------------------------------------------------------- ------------------- -Slack: inf - Source: data_memory/memory_data_reg[268435460][6]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[6] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.197ns (logic 1.435ns (65.337%) route 0.761ns (34.663%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.593 -0.494 data_memory/clk_out1 - SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.128 -0.366 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q - net (fo=1, routed) 0.761 0.395 lopt_8 - W4 OBUF (Prop_obuf_I_O) 1.307 1.702 r bcd_control_OBUF[6]_inst/O - net (fo=0) 0.000 1.702 bcd_control[6] - W4 r bcd_control[6] (OUT) - ------------------------------------------------------------------- ------------------- - Slack: inf Source: data_memory/memory_data_reg[268435460][4]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -2434,7 +2203,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.250ns (logic 1.437ns (63.854%) route 0.813ns (36.146%)) + Data Path Delay: 1.760ns (logic 1.397ns (79.361%) route 0.363ns (20.639%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2453,16 +2222,160 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.593 -0.494 data_memory/clk_out1 - SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C + net (fo=18132, routed) 0.590 -0.497 data_memory/clk_out1 + SLICE_X65Y16 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.128 -0.366 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q - net (fo=1, routed) 0.813 0.447 lopt_6 - T5 OBUF (Prop_obuf_I_O) 1.309 1.756 r bcd_control_OBUF[4]_inst/O - net (fo=0) 0.000 1.756 bcd_control[4] + SLICE_X65Y16 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q + net (fo=1, routed) 0.363 0.007 lopt_6 + T5 OBUF (Prop_obuf_I_O) 1.256 1.263 r bcd_control_OBUF[4]_inst/O + net (fo=0) 0.000 1.263 bcd_control[4] T5 r bcd_control[4] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: data_memory/memory_data_reg[268435460][10]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[10] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.885ns (logic 1.386ns (73.515%) route 0.499ns (26.485%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.595 -0.492 data_memory/clk_out1 + SLICE_X65Y46 FDRE r data_memory/memory_data_reg[268435460][10]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y46 FDRE (Prop_fdre_C_Q) 0.141 -0.351 r data_memory/memory_data_reg[268435460][10]_lopt_replica/Q + net (fo=1, routed) 0.499 0.148 lopt_1 + P2 OBUF (Prop_obuf_I_O) 1.245 1.393 r bcd_control_OBUF[10]_inst/O + net (fo=0) 0.000 1.393 bcd_control[10] + P2 r bcd_control[10] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][6]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[6] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.887ns (logic 1.395ns (73.937%) route 0.492ns (26.063%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.593 -0.494 data_memory/clk_out1 + SLICE_X65Y38 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q + net (fo=1, routed) 0.492 0.139 lopt_8 + W4 OBUF (Prop_obuf_I_O) 1.254 1.393 r bcd_control_OBUF[6]_inst/O + net (fo=0) 0.000 1.393 bcd_control[6] + W4 r bcd_control[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][1]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.902ns (logic 1.376ns (72.357%) route 0.526ns (27.643%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.594 -0.493 data_memory/clk_out1 + SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][1]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][1]_lopt_replica/Q + net (fo=1, routed) 0.526 0.174 lopt_3 + P5 OBUF (Prop_obuf_I_O) 1.235 1.409 r bcd_control_OBUF[1]_inst/O + net (fo=0) 0.000 1.409 bcd_control[1] + P5 r bcd_control[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][5]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[5] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.987ns (logic 1.400ns (70.452%) route 0.587ns (29.548%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.594 -0.493 data_memory/clk_out1 + SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q + net (fo=1, routed) 0.587 0.235 lopt_7 + P1 OBUF (Prop_obuf_I_O) 1.259 1.493 r bcd_control_OBUF[5]_inst/O + net (fo=0) 0.000 1.493 bcd_control[5] + P1 r bcd_control[5] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: data_memory/memory_data_reg[268435460][3]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -2470,7 +2383,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.307ns (logic 1.438ns (62.353%) route 0.868ns (37.647%)) + Data Path Delay: 2.034ns (logic 1.397ns (68.715%) route 0.636ns (31.285%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2489,24 +2402,24 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.593 -0.494 data_memory/clk_out1 - SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C + net (fo=18132, routed) 0.553 -0.534 data_memory/clk_out1 + SLICE_X51Y24 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.128 -0.366 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q - net (fo=1, routed) 0.868 0.502 lopt_5 - U5 OBUF (Prop_obuf_I_O) 1.310 1.813 r bcd_control_OBUF[3]_inst/O - net (fo=0) 0.000 1.813 bcd_control[3] + SLICE_X51Y24 FDRE (Prop_fdre_C_Q) 0.141 -0.393 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q + net (fo=1, routed) 0.636 0.243 lopt_5 + U5 OBUF (Prop_obuf_I_O) 1.256 1.499 r bcd_control_OBUF[3]_inst/O + net (fo=0) 0.000 1.499 bcd_control[3] U5 r bcd_control[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: data_memory/memory_data_reg[268435460][2]_lopt_replica/C + Source: data_memory/memory_data_reg[268435460][9]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[2] + Destination: bcd_control[9] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.341ns (logic 1.369ns (58.462%) route 0.973ns (41.538%)) + Data Path Delay: 2.044ns (logic 1.402ns (68.602%) route 0.642ns (31.398%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2525,14 +2438,50 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.593 -0.494 data_memory/clk_out1 - SLICE_X62Y56 FDRE r data_memory/memory_data_reg[268435460][2]_lopt_replica/C + net (fo=18132, routed) 0.594 -0.493 data_memory/clk_out1 + SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X62Y56 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][2]_lopt_replica/Q - net (fo=1, routed) 0.973 0.619 lopt_4 - V5 OBUF (Prop_obuf_I_O) 1.228 1.847 r bcd_control_OBUF[2]_inst/O - net (fo=0) 0.000 1.847 bcd_control[2] - V5 r bcd_control[2] (OUT) + SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q + net (fo=1, routed) 0.642 0.289 lopt_11 + R1 OBUF (Prop_obuf_I_O) 1.261 1.551 r bcd_control_OBUF[9]_inst/O + net (fo=0) 0.000 1.551 bcd_control[9] + R1 r bcd_control[9] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][11]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[11] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.108ns (logic 1.378ns (65.371%) route 0.730ns (34.629%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.594 -0.493 data_memory/clk_out1 + SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][11]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][11]_lopt_replica/Q + net (fo=1, routed) 0.730 0.378 lopt_2 + M2 OBUF (Prop_obuf_I_O) 1.237 1.615 r bcd_control_OBUF[11]_inst/O + net (fo=0) 0.000 1.615 bcd_control[11] + M2 r bcd_control[11] (OUT) ------------------------------------------------------------------- ------------------- @@ -2626,8 +2575,8 @@ Path Group: (none) From Clock: To Clock: clk_out1_phase_locked_loop -Max Delay 18130 Endpoints -Min Delay 18130 Endpoints +Max Delay 18132 Endpoints +Min Delay 18132 Endpoints -------------------------------------------------------------------------------------- @@ -2636,11 +2585,137 @@ Max Delay Paths Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435729][19]/R + Destination: data_memory/memory_data_reg[268435704][15]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.258ns (logic 1.650ns (10.148%) route 14.608ns (89.852%)) + Data Path Delay: 16.011ns (logic 1.650ns (10.304%) route 14.362ns (89.696%)) + Logic Levels: 2 (IBUF=1 LUT2=1) + Clock Path Skew: -1.858ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.858ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + B22 0.000 0.000 r hardware_reset (IN) + net (fo=0) 0.000 0.000 hardware_reset + B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O + net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.503 16.011 data_memory/reset + SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][15]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1 + SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][15]/C + +Slack: inf + Source: hardware_reset + (input port) + Destination: data_memory/memory_data_reg[268435704][20]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 16.011ns (logic 1.650ns (10.304%) route 14.362ns (89.696%)) + Logic Levels: 2 (IBUF=1 LUT2=1) + Clock Path Skew: -1.858ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.858ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + B22 0.000 0.000 r hardware_reset (IN) + net (fo=0) 0.000 0.000 hardware_reset + B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O + net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.503 16.011 data_memory/reset + SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][20]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1 + SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][20]/C + +Slack: inf + Source: hardware_reset + (input port) + Destination: data_memory/memory_data_reg[268435704][26]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 16.011ns (logic 1.650ns (10.304%) route 14.362ns (89.696%)) + Logic Levels: 2 (IBUF=1 LUT2=1) + Clock Path Skew: -1.858ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.858ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + B22 0.000 0.000 r hardware_reset (IN) + net (fo=0) 0.000 0.000 hardware_reset + B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O + net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.503 16.011 data_memory/reset + SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][26]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1 + SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][26]/C + +Slack: inf + Source: hardware_reset + (input port) + Destination: data_memory/memory_data_reg[268435653][20]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 16.011ns (logic 1.650ns (10.304%) route 14.361ns (89.696%)) Logic Levels: 2 (IBUF=1 LUT2=1) Clock Path Skew: -1.857ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.857ns @@ -2656,10 +2731,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 9.760 16.258 data_memory/reset - SLICE_X22Y148 FDRE r data_memory/memory_data_reg[268435729][19]/R + net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.503 16.011 data_memory/reset + SLICE_X16Y144 FDRE r data_memory/memory_data_reg[268435653][20]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2672,20 +2747,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.614 -1.857 data_memory/clk_out1 - SLICE_X22Y148 FDRE r data_memory/memory_data_reg[268435729][19]/C + net (fo=18132, routed) 1.614 -1.857 data_memory/clk_out1 + SLICE_X16Y144 FDRE r data_memory/memory_data_reg[268435653][20]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435828][27]/R + Destination: data_memory/memory_data_reg[268435680][23]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.253ns (logic 1.650ns (10.150%) route 14.603ns (89.850%)) + Data Path Delay: 16.010ns (logic 1.650ns (10.304%) route 14.360ns (89.696%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.857ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.857ns + Clock Path Skew: -1.859ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.859ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2698,10 +2773,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 9.756 16.253 data_memory/reset - SLICE_X23Y148 FDRE r data_memory/memory_data_reg[268435828][27]/R + net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.502 16.010 data_memory/reset + SLICE_X11Y138 FDRE r data_memory/memory_data_reg[268435680][23]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2714,20 +2789,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.614 -1.857 data_memory/clk_out1 - SLICE_X23Y148 FDRE r data_memory/memory_data_reg[268435828][27]/C + net (fo=18132, routed) 1.612 -1.859 data_memory/clk_out1 + SLICE_X11Y138 FDRE r data_memory/memory_data_reg[268435680][23]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435752][20]/R + Destination: data_memory/memory_data_reg[268435680][25]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.253ns (logic 1.650ns (10.151%) route 14.603ns (89.849%)) + Data Path Delay: 16.010ns (logic 1.650ns (10.304%) route 14.360ns (89.696%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.857ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.857ns + Clock Path Skew: -1.859ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.859ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2740,10 +2815,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 9.755 16.253 data_memory/reset - SLICE_X18Y146 FDRE r data_memory/memory_data_reg[268435752][20]/R + net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.502 16.010 data_memory/reset + SLICE_X11Y138 FDRE r data_memory/memory_data_reg[268435680][25]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2756,20 +2831,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.614 -1.857 data_memory/clk_out1 - SLICE_X18Y146 FDRE r data_memory/memory_data_reg[268435752][20]/C + net (fo=18132, routed) 1.612 -1.859 data_memory/clk_out1 + SLICE_X11Y138 FDRE r data_memory/memory_data_reg[268435680][25]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435752][27]/R + Destination: data_memory/memory_data_reg[268435685][23]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.253ns (logic 1.650ns (10.151%) route 14.603ns (89.849%)) + Data Path Delay: 16.010ns (logic 1.650ns (10.304%) route 14.360ns (89.696%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.857ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.857ns + Clock Path Skew: -1.859ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.859ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2782,10 +2857,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 9.755 16.253 data_memory/reset - SLICE_X18Y146 FDRE r data_memory/memory_data_reg[268435752][27]/R + net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.502 16.010 data_memory/reset + SLICE_X10Y138 FDRE r data_memory/memory_data_reg[268435685][23]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2798,20 +2873,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.614 -1.857 data_memory/clk_out1 - SLICE_X18Y146 FDRE r data_memory/memory_data_reg[268435752][27]/C + net (fo=18132, routed) 1.612 -1.859 data_memory/clk_out1 + SLICE_X10Y138 FDRE r data_memory/memory_data_reg[268435685][23]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435746][20]/R + Destination: data_memory/memory_data_reg[268435685][25]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.248ns (logic 1.650ns (10.153%) route 14.598ns (89.847%)) + Data Path Delay: 16.010ns (logic 1.650ns (10.304%) route 14.360ns (89.696%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.857ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.857ns + Clock Path Skew: -1.859ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.859ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2824,10 +2899,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 9.751 16.248 data_memory/reset - SLICE_X19Y146 FDRE r data_memory/memory_data_reg[268435746][20]/R + net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.502 16.010 data_memory/reset + SLICE_X10Y138 FDRE r data_memory/memory_data_reg[268435685][25]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2840,20 +2915,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.614 -1.857 data_memory/clk_out1 - SLICE_X19Y146 FDRE r data_memory/memory_data_reg[268435746][20]/C + net (fo=18132, routed) 1.612 -1.859 data_memory/clk_out1 + SLICE_X10Y138 FDRE r data_memory/memory_data_reg[268435685][25]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435728][15]/R + Destination: data_memory/memory_data_reg[268435705][15]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.218ns (logic 1.650ns (10.172%) route 14.568ns (89.828%)) + Data Path Delay: 16.007ns (logic 1.650ns (10.306%) route 14.357ns (89.694%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.856ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.856ns + Clock Path Skew: -1.858ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.858ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2866,10 +2941,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 9.721 16.218 data_memory/reset - SLICE_X11Y145 FDRE r data_memory/memory_data_reg[268435728][15]/R + net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.499 16.007 data_memory/reset + SLICE_X23Y143 FDRE r data_memory/memory_data_reg[268435705][15]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2882,20 +2957,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.615 -1.856 data_memory/clk_out1 - SLICE_X11Y145 FDRE r data_memory/memory_data_reg[268435728][15]/C + net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1 + SLICE_X23Y143 FDRE r data_memory/memory_data_reg[268435705][15]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435728][27]/R + Destination: data_memory/memory_data_reg[268435705][20]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.218ns (logic 1.650ns (10.172%) route 14.568ns (89.828%)) + Data Path Delay: 16.007ns (logic 1.650ns (10.306%) route 14.357ns (89.694%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.856ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.856ns + Clock Path Skew: -1.858ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.858ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2908,10 +2983,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 9.721 16.218 data_memory/reset - SLICE_X11Y145 FDRE r data_memory/memory_data_reg[268435728][27]/R + net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.499 16.007 data_memory/reset + SLICE_X23Y143 FDRE r data_memory/memory_data_reg[268435705][20]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2924,134 +2999,8 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.615 -1.856 data_memory/clk_out1 - SLICE_X11Y145 FDRE r data_memory/memory_data_reg[268435728][27]/C - -Slack: inf - Source: hardware_reset - (input port) - Destination: data_memory/memory_data_reg[268435728][29]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.218ns (logic 1.650ns (10.172%) route 14.568ns (89.828%)) - Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.856ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.856ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - B22 0.000 0.000 r hardware_reset (IN) - net (fo=0) 0.000 0.000 hardware_reset - B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 9.721 16.218 data_memory/reset - SLICE_X11Y145 FDRE r data_memory/memory_data_reg[268435728][29]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.615 -1.856 data_memory/clk_out1 - SLICE_X11Y145 FDRE r data_memory/memory_data_reg[268435728][29]/C - -Slack: inf - Source: hardware_reset - (input port) - Destination: data_memory/memory_data_reg[268435733][27]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.218ns (logic 1.650ns (10.172%) route 14.568ns (89.828%)) - Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.856ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.856ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - B22 0.000 0.000 r hardware_reset (IN) - net (fo=0) 0.000 0.000 hardware_reset - B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 9.721 16.218 data_memory/reset - SLICE_X10Y145 FDRE r data_memory/memory_data_reg[268435733][27]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.615 -1.856 data_memory/clk_out1 - SLICE_X10Y145 FDRE r data_memory/memory_data_reg[268435733][27]/C - -Slack: inf - Source: hardware_reset - (input port) - Destination: data_memory/memory_data_reg[268435757][29]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.075ns (logic 1.650ns (10.262%) route 14.426ns (89.738%)) - Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.788ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.788ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - B22 0.000 0.000 r hardware_reset (IN) - net (fo=0) 0.000 0.000 hardware_reset - B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.847 6.373 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.497 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 9.578 16.075 data_memory/reset - SLICE_X0Y146 FDRE r data_memory/memory_data_reg[268435757][29]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 1.683 -1.788 data_memory/clk_out1 - SLICE_X0Y146 FDRE r data_memory/memory_data_reg[268435757][29]/C + net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1 + SLICE_X23Y143 FDRE r data_memory/memory_data_reg[268435705][20]/C @@ -3062,11 +3011,11 @@ Min Delay Paths Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435654][14]/R + Destination: data_memory/memory_data_reg[268435474][6]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.964ns (logic 0.045ns (4.670%) route 0.919ns (95.330%)) + Data Path Delay: 0.947ns (logic 0.045ns (4.750%) route 0.902ns (95.250%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3076,10 +3025,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.394 0.394 data_memory/locked - SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.525 0.964 data_memory/reset - SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435654][14]/R + net (fo=2, routed) 0.377 0.377 data_memory/locked + SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.525 0.947 data_memory/reset + SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435474][6]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3092,17 +3041,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435654][14]/C + net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435474][6]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435654][26]/R + Destination: data_memory/memory_data_reg[268435475][6]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.964ns (logic 0.045ns (4.670%) route 0.919ns (95.330%)) + Data Path Delay: 0.947ns (logic 0.045ns (4.750%) route 0.902ns (95.250%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3112,10 +3061,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.394 0.394 data_memory/locked - SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.525 0.964 data_memory/reset - SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435654][26]/R + net (fo=2, routed) 0.377 0.377 data_memory/locked + SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.525 0.947 data_memory/reset + SLICE_X64Y49 FDRE r data_memory/memory_data_reg[268435475][6]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3128,17 +3077,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435654][26]/C + net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X64Y49 FDRE r data_memory/memory_data_reg[268435475][6]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435654][2]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435485][6]/S + (rising edge-triggered cell FDSE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.964ns (logic 0.045ns (4.670%) route 0.919ns (95.330%)) + Data Path Delay: 0.980ns (logic 0.045ns (4.590%) route 0.935ns (95.410%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3148,10 +3097,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.394 0.394 data_memory/locked - SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.525 0.964 data_memory/reset - SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435654][2]/R + net (fo=2, routed) 0.377 0.377 data_memory/locked + SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.558 0.980 data_memory/reset + SLICE_X63Y49 FDSE r data_memory/memory_data_reg[268435485][6]/S ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3164,17 +3113,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X65Y48 FDRE r data_memory/memory_data_reg[268435654][2]/C + net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X63Y49 FDSE r data_memory/memory_data_reg[268435485][6]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435661][14]/R + Destination: data_memory/memory_data_reg[268435524][21]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.964ns (logic 0.045ns (4.670%) route 0.919ns (95.330%)) + Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3184,10 +3133,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.394 0.394 data_memory/locked - SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.525 0.964 data_memory/reset - SLICE_X64Y48 FDRE r data_memory/memory_data_reg[268435661][14]/R + net (fo=2, routed) 0.377 0.377 data_memory/locked + SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.562 0.985 data_memory/reset + SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][21]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3200,17 +3149,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X64Y48 FDRE r data_memory/memory_data_reg[268435661][14]/C + net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][21]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435652][14]/R + Destination: data_memory/memory_data_reg[268435524][23]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.024ns (logic 0.045ns (4.392%) route 0.979ns (95.608%)) + Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3220,10 +3169,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.394 0.394 data_memory/locked - SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.586 1.024 data_memory/reset - SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435652][14]/R + net (fo=2, routed) 0.377 0.377 data_memory/locked + SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.562 0.985 data_memory/reset + SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][23]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3236,17 +3185,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435652][14]/C + net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][23]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435652][26]/R + Destination: data_memory/memory_data_reg[268435524][28]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.024ns (logic 0.045ns (4.392%) route 0.979ns (95.608%)) + Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3256,10 +3205,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.394 0.394 data_memory/locked - SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.586 1.024 data_memory/reset - SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435652][26]/R + net (fo=2, routed) 0.377 0.377 data_memory/locked + SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.562 0.985 data_memory/reset + SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][28]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3272,17 +3221,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435652][26]/C + net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][28]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435652][2]/R + Destination: data_memory/memory_data_reg[268435524][29]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.024ns (logic 0.045ns (4.392%) route 0.979ns (95.608%)) + Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3292,10 +3241,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.394 0.394 data_memory/locked - SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.586 1.024 data_memory/reset - SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435652][2]/R + net (fo=2, routed) 0.377 0.377 data_memory/locked + SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.562 0.985 data_memory/reset + SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][29]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3308,17 +3257,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435652][2]/C + net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][29]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435656][26]/R + Destination: data_memory/memory_data_reg[268435524][6]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.024ns (logic 0.045ns (4.392%) route 0.979ns (95.608%)) + Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3328,10 +3277,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.394 0.394 data_memory/locked - SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.586 1.024 data_memory/reset - SLICE_X64Y49 FDRE r data_memory/memory_data_reg[268435656][26]/R + net (fo=2, routed) 0.377 0.377 data_memory/locked + SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.562 0.985 data_memory/reset + SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][6]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3344,17 +3293,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X64Y49 FDRE r data_memory/memory_data_reg[268435656][26]/C + net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 + SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][6]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435652][19]/R + Destination: data_memory/memory_data_reg[268435478][6]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.042ns (logic 0.045ns (4.319%) route 0.997ns (95.681%)) + Data Path Delay: 1.011ns (logic 0.045ns (4.451%) route 0.966ns (95.549%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3364,10 +3313,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.394 0.394 data_memory/locked - SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.603 1.042 data_memory/reset - SLICE_X64Y55 FDRE r data_memory/memory_data_reg[268435652][19]/R + net (fo=2, routed) 0.377 0.377 data_memory/locked + SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.589 1.011 data_memory/reset + SLICE_X65Y51 FDRE r data_memory/memory_data_reg[268435478][6]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3380,17 +3329,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.863 -0.262 data_memory/clk_out1 - SLICE_X64Y55 FDRE r data_memory/memory_data_reg[268435652][19]/C + net (fo=18132, routed) 0.864 -0.261 data_memory/clk_out1 + SLICE_X65Y51 FDRE r data_memory/memory_data_reg[268435478][6]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435710][15]/R + Destination: data_memory/memory_data_reg[268435480][6]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.049ns (logic 0.045ns (4.288%) route 1.004ns (95.712%)) + Data Path Delay: 1.011ns (logic 0.045ns (4.451%) route 0.966ns (95.549%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3400,10 +3349,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.394 0.394 data_memory/locked - SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17905, routed) 0.611 1.049 data_memory/reset - SLICE_X59Y44 FDRE r data_memory/memory_data_reg[268435710][15]/R + net (fo=2, routed) 0.377 0.377 data_memory/locked + SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.589 1.011 data_memory/reset + SLICE_X64Y51 FDRE r data_memory/memory_data_reg[268435480][6]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3416,8 +3365,8 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18130, routed) 0.864 -0.262 data_memory/clk_out1 - SLICE_X59Y44 FDRE r data_memory/memory_data_reg[268435710][15]/C + net (fo=18132, routed) 0.864 -0.261 data_memory/clk_out1 + SLICE_X64Y51 FDRE r data_memory/memory_data_reg[268435480][6]/C diff --git a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb index 58f10d7..64ad7a4 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb and b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt index e885dfc..7680db3 100644 --- a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 21:06:00 2024 +| Date : Sat Jul 13 14:28:53 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb | Design : CPU @@ -32,13 +32,13 @@ Table of Contents +-------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------------+-------+-------+------------+-----------+-------+ -| Slice LUTs | 8003 | 0 | 0 | 20800 | 38.48 | -| LUT as Logic | 8003 | 0 | 0 | 20800 | 38.48 | +| Slice LUTs | 8337 | 0 | 0 | 20800 | 40.08 | +| LUT as Logic | 8337 | 0 | 0 | 20800 | 40.08 | | LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | -| Slice Registers | 18130 | 0 | 0 | 41600 | 43.58 | -| Register as Flip Flop | 18130 | 0 | 0 | 41600 | 43.58 | +| Slice Registers | 18132 | 0 | 0 | 41600 | 43.59 | +| Register as Flip Flop | 18132 | 0 | 0 | 41600 | 43.59 | | Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | -| F7 Muxes | 2426 | 0 | 0 | 16300 | 14.88 | +| F7 Muxes | 2373 | 0 | 0 | 16300 | 14.56 | | F8 Muxes | 1088 | 0 | 0 | 8150 | 13.35 | +-------------------------+-------+-------+------------+-----------+-------+ * Warning! LUT value is adjusted to account for LUT combining. @@ -58,8 +58,8 @@ Table of Contents | 0 | Yes | - | - | | 0 | Yes | - | Set | | 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 18130 | Yes | Reset | - | +| 368 | Yes | Set | - | +| 17764 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -69,21 +69,21 @@ Table of Contents +--------------------------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +--------------------------------------------+-------+-------+------------+-----------+-------+ -| Slice | 7420 | 0 | 0 | 8150 | 91.04 | -| SLICEL | 5250 | 0 | | | | -| SLICEM | 2170 | 0 | | | | -| LUT as Logic | 8003 | 0 | 0 | 20800 | 38.48 | +| Slice | 7477 | 0 | 0 | 8150 | 91.74 | +| SLICEL | 5277 | 0 | | | | +| SLICEM | 2200 | 0 | | | | +| LUT as Logic | 8337 | 0 | 0 | 20800 | 40.08 | | using O5 output only | 0 | | | | | -| using O6 output only | 7624 | | | | | -| using O5 and O6 | 379 | | | | | +| using O6 output only | 8032 | | | | | +| using O5 and O6 | 305 | | | | | | LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | | LUT as Distributed RAM | 0 | 0 | | | | | LUT as Shift Register | 0 | 0 | | | | -| Slice Registers | 18130 | 0 | 0 | 41600 | 43.58 | -| Register driven from within the Slice | 1232 | | | | | -| Register driven from outside the Slice | 16898 | | | | | -| LUT in front of the register is unused | 14968 | | | | | -| LUT in front of the register is used | 1930 | | | | | +| Slice Registers | 18132 | 0 | 0 | 41600 | 43.59 | +| Register driven from within the Slice | 1478 | | | | | +| Register driven from outside the Slice | 16654 | | | | | +| LUT in front of the register is unused | 14681 | | | | | +| LUT in front of the register is used | 1973 | | | | | | Unique Control Sets | 547 | | 0 | 8150 | 6.71 | +--------------------------------------------+-------+-------+------------+-----------+-------+ * * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. @@ -180,14 +180,15 @@ Table of Contents +-----------+-------+---------------------+ | Ref Name | Used | Functional Category | +-----------+-------+---------------------+ -| FDRE | 18130 | Flop & Latch | -| LUT6 | 6947 | LUT | -| MUXF7 | 2426 | MuxFx | +| FDRE | 17764 | Flop & Latch | +| LUT6 | 7147 | LUT | +| MUXF7 | 2373 | MuxFx | | MUXF8 | 1088 | MuxFx | -| LUT5 | 720 | LUT | -| LUT4 | 300 | LUT | -| LUT3 | 231 | LUT | -| LUT2 | 183 | LUT | +| LUT5 | 831 | LUT | +| FDSE | 368 | Flop & Latch | +| LUT4 | 279 | LUT | +| LUT3 | 229 | LUT | +| LUT2 | 155 | LUT | | CARRY4 | 39 | CarryLogic | | OBUF | 13 | IO | | DSP48E1 | 3 | Block Arithmetic | diff --git a/PipelineProcessor.runs/impl_1/clockInfo.txt b/PipelineProcessor.runs/impl_1/clockInfo.txt index 0986769..9b4b1e8 100644 --- a/PipelineProcessor.runs/impl_1/clockInfo.txt +++ b/PipelineProcessor.runs/impl_1/clockInfo.txt @@ -1,6 +1,6 @@ ------------------------------------- | Tool Version : Vivado v.2023.2 -| Date : Fri Jul 12 21:05:29 2024 +| Date : Sat Jul 13 14:28:25 2024 | Host : Viviana | Design : design_1 | Device : xc7a35t-fgg484-1-- diff --git a/PipelineProcessor.runs/impl_1/init_design.pb b/PipelineProcessor.runs/impl_1/init_design.pb index 55318cc..3ed00e2 100644 Binary files a/PipelineProcessor.runs/impl_1/init_design.pb and b/PipelineProcessor.runs/impl_1/init_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/opt_design.pb b/PipelineProcessor.runs/impl_1/opt_design.pb index c1056ec..64b06e0 100644 Binary files a/PipelineProcessor.runs/impl_1/opt_design.pb and b/PipelineProcessor.runs/impl_1/opt_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/phys_opt_design.pb b/PipelineProcessor.runs/impl_1/phys_opt_design.pb index e90d8c3..9393ab6 100644 Binary files a/PipelineProcessor.runs/impl_1/phys_opt_design.pb and b/PipelineProcessor.runs/impl_1/phys_opt_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/place_design.pb b/PipelineProcessor.runs/impl_1/place_design.pb index 0379dc1..fd3e7a2 100644 Binary files a/PipelineProcessor.runs/impl_1/place_design.pb and b/PipelineProcessor.runs/impl_1/place_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/route_design.pb b/PipelineProcessor.runs/impl_1/route_design.pb index e20edec..89b309a 100644 Binary files a/PipelineProcessor.runs/impl_1/route_design.pb and b/PipelineProcessor.runs/impl_1/route_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/vivado.jou b/PipelineProcessor.runs/impl_1/vivado.jou index 4bec96a..0d49340 100644 --- a/PipelineProcessor.runs/impl_1/vivado.jou +++ b/PipelineProcessor.runs/impl_1/vivado.jou @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Fri Jul 12 21:05:00 2024 -# Process ID: 22952 +# Start of session at: Sat Jul 13 14:27:36 2024 +# Process ID: 19592 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1 # Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi diff --git a/PipelineProcessor.runs/impl_1/vivado.pb b/PipelineProcessor.runs/impl_1/vivado.pb index 2352fc3..376a80f 100644 Binary files a/PipelineProcessor.runs/impl_1/vivado.pb and b/PipelineProcessor.runs/impl_1/vivado.pb differ diff --git a/PipelineProcessor.runs/impl_1/write_bitstream.pb b/PipelineProcessor.runs/impl_1/write_bitstream.pb index e2d4355..e4d2da7 100644 Binary files a/PipelineProcessor.runs/impl_1/write_bitstream.pb and b/PipelineProcessor.runs/impl_1/write_bitstream.pb differ diff --git a/PipelineProcessor.runs/synth_1/CPU.dcp b/PipelineProcessor.runs/synth_1/CPU.dcp index f29ea0c..2400e10 100644 Binary files a/PipelineProcessor.runs/synth_1/CPU.dcp and b/PipelineProcessor.runs/synth_1/CPU.dcp differ diff --git a/PipelineProcessor.runs/synth_1/CPU.vds b/PipelineProcessor.runs/synth_1/CPU.vds index 6fdef09..ddec603 100644 --- a/PipelineProcessor.runs/synth_1/CPU.vds +++ b/PipelineProcessor.runs/synth_1/CPU.vds @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Fri Jul 12 21:03:30 2024 -# Process ID: 19744 +# Start of session at: Sat Jul 13 14:22:20 2024 +# Process ID: 3472 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1 # Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds @@ -12,7 +12,7 @@ # Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB #----------------------------------------------------------- source CPU.tcl -notrace -create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 462.926 ; gain = 182.984 +create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:22 . Memory (MB): peak = 463.508 ; gain = 184.387 Command: read_checkpoint -auto_incremental -incremental D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp INFO: [Vivado 12-5825] Read reference checkpoint from D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes @@ -25,13 +25,13 @@ INFO: [Designutils 20-5440] No compile time benefit to using incremental synthes INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 23648 +INFO: [Synth 8-7075] Helper process launched with PID 30200 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 1306.855 ; gain = 438.977 +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:18 . Memory (MB): peak = 1308.621 ; gain = 440.629 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'CPU' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/CPU.v:2] -INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-19744-Viviana/realtime/phase_locked_loop_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-19744-Viviana/realtime/phase_locked_loop_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-3472-Viviana/realtime/phase_locked_loop_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-3472-Viviana/realtime/phase_locked_loop_stub.v:6] INFO: [Synth 8-6157] synthesizing module 'InstFetch' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstFetch.v:2] INFO: [Synth 8-6157] synthesizing module 'InstructionMemory' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3] INFO: [Synth 8-6155] done synthesizing module 'InstructionMemory' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3] @@ -66,18 +66,18 @@ WARNING: [Synth 8-7129] Port address[0] in module DataMemory is either unconnect WARNING: [Synth 8-7129] Port address[1] in module InstructionMemory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module InstructionMemory is either unconnected or has no load --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1476.648 ; gain = 608.770 +Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1478.609 ; gain = 610.617 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1476.648 ; gain = 608.770 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:30 . Memory (MB): peak = 1478.609 ; gain = 610.617 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1476.648 ; gain = 608.770 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:30 . Memory (MB): peak = 1478.609 ; gain = 610.617 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.173 . Memory (MB): peak = 1476.648 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.793 . Memory (MB): peak = 1478.609 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints @@ -90,22 +90,22 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi Resolution: To avoid this warning, move constraints listed in [.Xil/CPU_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1584.652 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1578.020 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1584.652 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.243 . Memory (MB): peak = 1578.020 ; gain = 0.000 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.652 ; gain = 716.773 +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:01:07 . Memory (MB): peak = 1578.020 ; gain = 710.027 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tfgg484-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.652 ; gain = 716.773 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:01:07 . Memory (MB): peak = 1578.020 ; gain = 710.027 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints @@ -114,10 +114,10 @@ Applied set_property IO_BUFFER_TYPE = NONE for hardware_clk. (constraint file d Applied set_property CLOCK_BUFFER_TYPE = NONE for hardware_clk. (constraint file d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc, line 4). Applied set_property KEEP_HIERARCHY = SOFT for pll. (constraint file auto generated constraint). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.652 ; gain = 716.773 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:01:07 . Memory (MB): peak = 1578.020 ; gain = 710.027 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:18 . Memory (MB): peak = 1584.652 ; gain = 716.773 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:01:29 . Memory (MB): peak = 1578.020 ; gain = 710.027 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics @@ -173,7 +173,7 @@ DSP Report: Generating DSP alu/result0, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator alu/result0 is absorbed into DSP alu/result0. DSP Report: operator alu/result0 is absorbed into DSP alu/result0. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:40 . Memory (MB): peak = 1584.652 ; gain = 716.773 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:03:07 . Memory (MB): peak = 1578.020 ; gain = 710.027 --------------------------------------------------------------------------------- Sort Area is CPU__GC0 alu/result0_0 : 0 0 : 3101 5879 : Used 1 time 0 Sort Area is CPU__GC0 alu/result0_0 : 0 1 : 2778 5879 : Used 1 time 0 @@ -183,6 +183,14 @@ Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elaps Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- +ROM: Preliminary Mapping Report ++------------------+-------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------------+-------------+---------------+----------------+ +|InstructionMemory | instruction | 256x32 | LUT | ++------------------+-------------+---------------+----------------+ + + DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | @@ -201,19 +209,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:47 . Memory (MB): peak = 1584.652 ; gain = 716.773 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:39 ; elapsed = 00:03:21 . Memory (MB): peak = 1578.020 ; gain = 710.027 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:56 . Memory (MB): peak = 1761.211 ; gain = 893.332 +Finished Timing Optimization : Time (s): cpu = 00:00:44 ; elapsed = 00:03:49 . Memory (MB): peak = 1712.805 ; gain = 844.812 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:01:02 . Memory (MB): peak = 1767.527 ; gain = 899.648 +Finished Technology Mapping : Time (s): cpu = 00:00:45 ; elapsed = 00:04:00 . Memory (MB): peak = 1719.152 ; gain = 851.160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -231,37 +239,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:12 ; elapsed = 00:01:06 . Memory (MB): peak = 1767.527 ; gain = 899.648 +Finished IO Insertion : Time (s): cpu = 00:00:46 ; elapsed = 00:04:09 . Memory (MB): peak = 1719.152 ; gain = 851.160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:12 ; elapsed = 00:01:06 . Memory (MB): peak = 1767.527 ; gain = 899.648 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:46 ; elapsed = 00:04:09 . Memory (MB): peak = 1719.152 ; gain = 851.160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:46 ; elapsed = 00:04:12 . Memory (MB): peak = 1719.152 ; gain = 851.160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:46 ; elapsed = 00:04:12 . Memory (MB): peak = 1719.152 ; gain = 851.160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:46 ; elapsed = 00:04:12 . Memory (MB): peak = 1719.152 ; gain = 851.160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:46 ; elapsed = 00:04:13 . Memory (MB): peak = 1719.152 ; gain = 851.160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -291,40 +299,41 @@ Report Cell Usage: |1 |phase_locked_loop | 1| |2 |CARRY4 | 39| |3 |DSP48E1 | 3| -|4 |LUT1 | 2| -|5 |LUT2 | 183| -|6 |LUT3 | 231| -|7 |LUT4 | 300| -|8 |LUT5 | 720| -|9 |LUT6 | 6947| -|10 |MUXF7 | 2426| +|4 |LUT1 | 15| +|5 |LUT2 | 155| +|6 |LUT3 | 229| +|7 |LUT4 | 279| +|8 |LUT5 | 831| +|9 |LUT6 | 7147| +|10 |MUXF7 | 2373| |11 |MUXF8 | 1088| -|12 |FDRE | 18118| -|13 |IBUF | 1| -|14 |OBUF | 13| +|12 |FDRE | 17752| +|13 |FDSE | 368| +|14 |IBUF | 1| +|15 |OBUF | 13| +------+------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:46 ; elapsed = 00:04:13 . Memory (MB): peak = 1719.152 ; gain = 851.160 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:01:05 . Memory (MB): peak = 1767.527 ; gain = 791.645 -Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:03:58 . Memory (MB): peak = 1719.152 ; gain = 751.750 +Synthesis Optimization Complete : Time (s): cpu = 00:00:46 ; elapsed = 00:04:13 . Memory (MB): peak = 1719.152 ; gain = 851.160 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.245 . Memory (MB): peak = 1767.527 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 3556 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1724.391 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 3503 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1767.527 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1729.113 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Synth Design complete | Checksum: a3f3fba1 +Synth Design complete | Checksum: 93dc575b INFO: [Common 17-83] Releasing license: Synthesis 51 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:01:15 . Memory (MB): peak = 1767.527 ; gain = 1293.230 -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1767.527 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:51 ; elapsed = 00:04:35 . Memory (MB): peak = 1729.113 ; gain = 1252.605 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1729.113 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri Jul 12 21:04:53 2024... +INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 14:27:28 2024... diff --git a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb index 90c1ccf..6537ad0 100644 Binary files a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb and b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb differ diff --git a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt index 9379864..861a62c 100644 --- a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt +++ b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Fri Jul 12 21:04:53 2024 +| Date : Sat Jul 13 14:27:28 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb | Design : CPU @@ -31,13 +31,13 @@ Table of Contents +-------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------------+-------+-------+------------+-----------+-------+ -| Slice LUTs* | 8042 | 0 | 0 | 20800 | 38.66 | -| LUT as Logic | 8042 | 0 | 0 | 20800 | 38.66 | +| Slice LUTs* | 8380 | 0 | 0 | 20800 | 40.29 | +| LUT as Logic | 8380 | 0 | 0 | 20800 | 40.29 | | LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | -| Slice Registers | 18118 | 0 | 0 | 41600 | 43.55 | -| Register as Flip Flop | 18118 | 0 | 0 | 41600 | 43.55 | +| Slice Registers | 18120 | 0 | 0 | 41600 | 43.56 | +| Register as Flip Flop | 18120 | 0 | 0 | 41600 | 43.56 | | Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | -| F7 Muxes | 2426 | 0 | 0 | 16300 | 14.88 | +| F7 Muxes | 2373 | 0 | 0 | 16300 | 14.56 | | F8 Muxes | 1088 | 0 | 0 | 8150 | 13.35 | +-------------------------+-------+-------+------------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -58,8 +58,8 @@ Warning! LUT value is adjusted to account for LUT combining. | 0 | Yes | - | - | | 0 | Yes | - | Set | | 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 18118 | Yes | Reset | - | +| 368 | Yes | Set | - | +| 17752 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -152,18 +152,19 @@ Warning! LUT value is adjusted to account for LUT combining. +----------+-------+---------------------+ | Ref Name | Used | Functional Category | +----------+-------+---------------------+ -| FDRE | 18118 | Flop & Latch | -| LUT6 | 6947 | LUT | -| MUXF7 | 2426 | MuxFx | +| FDRE | 17752 | Flop & Latch | +| LUT6 | 7147 | LUT | +| MUXF7 | 2373 | MuxFx | | MUXF8 | 1088 | MuxFx | -| LUT5 | 720 | LUT | -| LUT4 | 300 | LUT | -| LUT3 | 231 | LUT | -| LUT2 | 183 | LUT | +| LUT5 | 831 | LUT | +| FDSE | 368 | Flop & Latch | +| LUT4 | 279 | LUT | +| LUT3 | 229 | LUT | +| LUT2 | 155 | LUT | | CARRY4 | 39 | CarryLogic | +| LUT1 | 15 | LUT | | OBUF | 13 | IO | | DSP48E1 | 3 | Block Arithmetic | -| LUT1 | 2 | LUT | | IBUF | 1 | IO | +----------+-------+---------------------+ diff --git a/PipelineProcessor.runs/synth_1/vivado.jou b/PipelineProcessor.runs/synth_1/vivado.jou index d2d90e9..b13ccaf 100644 --- a/PipelineProcessor.runs/synth_1/vivado.jou +++ b/PipelineProcessor.runs/synth_1/vivado.jou @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Fri Jul 12 21:03:30 2024 -# Process ID: 19744 +# Start of session at: Sat Jul 13 14:22:20 2024 +# Process ID: 3472 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1 # Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds diff --git a/PipelineProcessor.runs/synth_1/vivado.pb b/PipelineProcessor.runs/synth_1/vivado.pb index 6b4e59c..fcd6e03 100644 Binary files a/PipelineProcessor.runs/synth_1/vivado.pb and b/PipelineProcessor.runs/synth_1/vivado.pb differ diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem index c17d8c2..ae63b48 100644 Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem and b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem differ diff --git a/PipelineProcessor.srcs/sources_1/new/DataMemory.v b/PipelineProcessor.srcs/sources_1/new/DataMemory.v index 1eb3ba5..9d8a759 100644 --- a/PipelineProcessor.srcs/sources_1/new/DataMemory.v +++ b/PipelineProcessor.srcs/sources_1/new/DataMemory.v @@ -23,16 +23,122 @@ module DataMemory ( integer i; initial begin - for (i = StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1) begin + for (i = StartAddressInWord; i < 24 + StartAddressInWord; i = i + 1) begin memory_data[i] <= 32'h00000000; end + for ( + i = 72 + StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1 + ) begin + memory_data[i] <= 32'h00000000; + end + memory_data[StartAddressInWord+24] <= 32'h0000002F; + memory_data[StartAddressInWord+25] <= 32'h000018D0; + memory_data[StartAddressInWord+26] <= 32'h00003A27; + memory_data[StartAddressInWord+27] <= 32'h00004786; + memory_data[StartAddressInWord+28] <= 32'h0000C94D; + memory_data[StartAddressInWord+29] <= 32'h000064CA; + memory_data[StartAddressInWord+30] <= 32'h00008027; + memory_data[StartAddressInWord+31] <= 32'h0000C8C3; + memory_data[StartAddressInWord+32] <= 32'h0000E08B; + memory_data[StartAddressInWord+33] <= 32'h00006E15; + memory_data[StartAddressInWord+34] <= 32'h0000AA22; + memory_data[StartAddressInWord+35] <= 32'h00002E07; + memory_data[StartAddressInWord+36] <= 32'h00009F23; + memory_data[StartAddressInWord+37] <= 32'h00002F2B; + memory_data[StartAddressInWord+38] <= 32'h00004227; + memory_data[StartAddressInWord+39] <= 32'h0000022C; + memory_data[StartAddressInWord+40] <= 32'h00009776; + memory_data[StartAddressInWord+41] <= 32'h00009477; + memory_data[StartAddressInWord+42] <= 32'h0000AAF5; + memory_data[StartAddressInWord+43] <= 32'h000080BE; + memory_data[StartAddressInWord+44] <= 32'h00002CC7; + memory_data[StartAddressInWord+45] <= 32'h00009D7D; + memory_data[StartAddressInWord+46] <= 32'h00000F95; + memory_data[StartAddressInWord+47] <= 32'h0000E060; + memory_data[StartAddressInWord+48] <= 32'h00002137; + memory_data[StartAddressInWord+49] <= 32'h0000A5E5; + memory_data[StartAddressInWord+50] <= 32'h00001C49; + memory_data[StartAddressInWord+51] <= 32'h0000C308; + memory_data[StartAddressInWord+52] <= 32'h00001A04; + memory_data[StartAddressInWord+53] <= 32'h00005F99; + memory_data[StartAddressInWord+54] <= 32'h0000124C; + memory_data[StartAddressInWord+55] <= 32'h0000ABB3; + memory_data[StartAddressInWord+56] <= 32'h00000E87; + memory_data[StartAddressInWord+57] <= 32'h00005E55; + memory_data[StartAddressInWord+58] <= 32'h00002197; + memory_data[StartAddressInWord+59] <= 32'h00000AA4; + memory_data[StartAddressInWord+60] <= 32'h0000F7FE; + memory_data[StartAddressInWord+61] <= 32'h00007F32; + memory_data[StartAddressInWord+62] <= 32'h0000C5A5; + memory_data[StartAddressInWord+63] <= 32'h0000D87C; + memory_data[StartAddressInWord+64] <= 32'h0000E996; + memory_data[StartAddressInWord+65] <= 32'h00007345; + memory_data[StartAddressInWord+66] <= 32'h00009213; + memory_data[StartAddressInWord+67] <= 32'h000076EE; + memory_data[StartAddressInWord+68] <= 32'h0000260B; + memory_data[StartAddressInWord+69] <= 32'h0000E0D8; + memory_data[StartAddressInWord+70] <= 32'h0000D9CA; + memory_data[StartAddressInWord+71] <= 32'h00003B9F; end always @(posedge clk) begin if (reset) begin - for (i = StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1) begin + for (i = StartAddressInWord; i < 24 + StartAddressInWord; i = i + 1) begin memory_data[i] <= 32'h00000000; end + for ( + i = 72 + StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1 + ) begin + memory_data[i] <= 32'h00000000; + end + memory_data[StartAddressInWord+24] <= 32'h0000002F; + memory_data[StartAddressInWord+25] <= 32'h000018D0; + memory_data[StartAddressInWord+26] <= 32'h00003A27; + memory_data[StartAddressInWord+27] <= 32'h00004786; + memory_data[StartAddressInWord+28] <= 32'h0000C94D; + memory_data[StartAddressInWord+29] <= 32'h000064CA; + memory_data[StartAddressInWord+30] <= 32'h00008027; + memory_data[StartAddressInWord+31] <= 32'h0000C8C3; + memory_data[StartAddressInWord+32] <= 32'h0000E08B; + memory_data[StartAddressInWord+33] <= 32'h00006E15; + memory_data[StartAddressInWord+34] <= 32'h0000AA22; + memory_data[StartAddressInWord+35] <= 32'h00002E07; + memory_data[StartAddressInWord+36] <= 32'h00009F23; + memory_data[StartAddressInWord+37] <= 32'h00002F2B; + memory_data[StartAddressInWord+38] <= 32'h00004227; + memory_data[StartAddressInWord+39] <= 32'h0000022C; + memory_data[StartAddressInWord+40] <= 32'h00009776; + memory_data[StartAddressInWord+41] <= 32'h00009477; + memory_data[StartAddressInWord+42] <= 32'h0000AAF5; + memory_data[StartAddressInWord+43] <= 32'h000080BE; + memory_data[StartAddressInWord+44] <= 32'h00002CC7; + memory_data[StartAddressInWord+45] <= 32'h00009D7D; + memory_data[StartAddressInWord+46] <= 32'h00000F95; + memory_data[StartAddressInWord+47] <= 32'h0000E060; + memory_data[StartAddressInWord+48] <= 32'h00002137; + memory_data[StartAddressInWord+49] <= 32'h0000A5E5; + memory_data[StartAddressInWord+50] <= 32'h00001C49; + memory_data[StartAddressInWord+51] <= 32'h0000C308; + memory_data[StartAddressInWord+52] <= 32'h00001A04; + memory_data[StartAddressInWord+53] <= 32'h00005F99; + memory_data[StartAddressInWord+54] <= 32'h0000124C; + memory_data[StartAddressInWord+55] <= 32'h0000ABB3; + memory_data[StartAddressInWord+56] <= 32'h00000E87; + memory_data[StartAddressInWord+57] <= 32'h00005E55; + memory_data[StartAddressInWord+58] <= 32'h00002197; + memory_data[StartAddressInWord+59] <= 32'h00000AA4; + memory_data[StartAddressInWord+60] <= 32'h0000F7FE; + memory_data[StartAddressInWord+61] <= 32'h00007F32; + memory_data[StartAddressInWord+62] <= 32'h0000C5A5; + memory_data[StartAddressInWord+63] <= 32'h0000D87C; + memory_data[StartAddressInWord+64] <= 32'h0000E996; + memory_data[StartAddressInWord+65] <= 32'h00007345; + memory_data[StartAddressInWord+66] <= 32'h00009213; + memory_data[StartAddressInWord+67] <= 32'h000076EE; + memory_data[StartAddressInWord+68] <= 32'h0000260B; + memory_data[StartAddressInWord+69] <= 32'h0000E0D8; + memory_data[StartAddressInWord+70] <= 32'h0000D9CA; + memory_data[StartAddressInWord+71] <= 32'h00003B9F; end else begin if (write_enable) begin memory_data[address[31:2]] <= write_data; diff --git a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v index 010d037..149800d 100644 --- a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v +++ b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v @@ -43,221 +43,174 @@ module InstructionMemory ( 20'd33: instruction <= 32'hae110038; 20'd34: instruction <= 32'h20110071; 20'd35: instruction <= 32'hae11003c; - 20'd36: instruction <= 32'h3c104000; - 20'd37: instruction <= 32'h22100060; - 20'd38: instruction <= 32'h20114b8d; - 20'd39: instruction <= 32'hae110000; - 20'd40: instruction <= 32'h20112307; - 20'd41: instruction <= 32'hae110004; - 20'd42: instruction <= 32'h3c010000; - 20'd43: instruction <= 32'h3421fae0; - 20'd44: instruction <= 32'h00018820; - 20'd45: instruction <= 32'hae110008; - 20'd46: instruction <= 32'h20117815; - 20'd47: instruction <= 32'hae11000c; - 20'd48: instruction <= 32'h3c010000; - 20'd49: instruction <= 32'h3421c105; - 20'd50: instruction <= 32'h00018820; - 20'd51: instruction <= 32'hae110010; - 20'd52: instruction <= 32'h3c010000; - 20'd53: instruction <= 32'h342184f0; - 20'd54: instruction <= 32'h00018820; - 20'd55: instruction <= 32'hae110014; - 20'd56: instruction <= 32'h20110db6; - 20'd57: instruction <= 32'hae110018; - 20'd58: instruction <= 32'h3c010000; - 20'd59: instruction <= 32'h3421f21d; - 20'd60: instruction <= 32'h00018820; - 20'd61: instruction <= 32'hae11001c; - 20'd62: instruction <= 32'h3c010000; - 20'd63: instruction <= 32'h3421e97a; - 20'd64: instruction <= 32'h00018820; - 20'd65: instruction <= 32'hae110020; - 20'd66: instruction <= 32'h3c010000; - 20'd67: instruction <= 32'h3421a3b6; - 20'd68: instruction <= 32'h00018820; - 20'd69: instruction <= 32'hae110024; - 20'd70: instruction <= 32'h3c010000; - 20'd71: instruction <= 32'h34218466; - 20'd72: instruction <= 32'h00018820; - 20'd73: instruction <= 32'hae110028; - 20'd74: instruction <= 32'h20113a25; - 20'd75: instruction <= 32'hae11002c; - 20'd76: instruction <= 32'h201105df; - 20'd77: instruction <= 32'hae110030; - 20'd78: instruction <= 32'h3c010000; - 20'd79: instruction <= 32'h3421d2de; - 20'd80: instruction <= 32'h00018820; - 20'd81: instruction <= 32'hae110034; - 20'd82: instruction <= 32'h3c010000; - 20'd83: instruction <= 32'h3421ba7a; - 20'd84: instruction <= 32'h00018820; - 20'd85: instruction <= 32'hae110038; - 20'd86: instruction <= 32'h20117809; - 20'd87: instruction <= 32'hae11003c; - 20'd88: instruction <= 32'h3c010000; - 20'd89: instruction <= 32'h3421f6a8; - 20'd90: instruction <= 32'h00018820; - 20'd91: instruction <= 32'hae110040; - 20'd92: instruction <= 32'h2011361d; - 20'd93: instruction <= 32'hae110044; - 20'd94: instruction <= 32'h20113adb; - 20'd95: instruction <= 32'hae110048; - 20'd96: instruction <= 32'h3c010000; - 20'd97: instruction <= 32'h3421969a; - 20'd98: instruction <= 32'h00018820; - 20'd99: instruction <= 32'hae11004c; - 20'd100: instruction <= 32'h20040014; - 20'd101: instruction <= 32'h0c0000a6; - 20'd102: instruction <= 32'h3c104000; - 20'd103: instruction <= 32'h22110010; - 20'd104: instruction <= 32'h22100060; - 20'd105: instruction <= 32'h20120000; - 20'd106: instruction <= 32'h20130014; - 20'd107: instruction <= 32'h00124080; - 20'd108: instruction <= 32'h02084020; - 20'd109: instruction <= 32'h8d040000; - 20'd110: instruction <= 32'h22250000; - 20'd111: instruction <= 32'h0c000075; - 20'd112: instruction <= 32'h22520001; - 20'd113: instruction <= 32'h02724022; - 20'd114: instruction <= 32'h1d00fff8; - 20'd115: instruction <= 32'h0c00009f; - 20'd116: instruction <= 32'h08000069; - 20'd117: instruction <= 32'h23bdffe0; - 20'd118: instruction <= 32'hafbf0004; - 20'd119: instruction <= 32'hafb00008; - 20'd120: instruction <= 32'hafb1000c; - 20'd121: instruction <= 32'hafb20010; - 20'd122: instruction <= 32'hafb30014; - 20'd123: instruction <= 32'hafb40018; - 20'd124: instruction <= 32'hafb5001c; - 20'd125: instruction <= 32'hafb60020; - 20'd126: instruction <= 32'h20900000; - 20'd127: instruction <= 32'h20b10000; - 20'd128: instruction <= 32'h3c124000; - 20'd129: instruction <= 32'h22520020; - 20'd130: instruction <= 32'h20130be2; - 20'd131: instruction <= 32'h22140000; - 20'd132: instruction <= 32'h20160100; - 20'd133: instruction <= 32'h20150004; - 20'd134: instruction <= 32'h3288000f; - 20'd135: instruction <= 32'h00084080; - 20'd136: instruction <= 32'h02484020; - 20'd137: instruction <= 32'h8d080000; - 20'd138: instruction <= 32'h01164025; - 20'd139: instruction <= 32'hae280000; - 20'd140: instruction <= 32'h0014a102; - 20'd141: instruction <= 32'h0016b040; - 20'd142: instruction <= 32'h20080400; - 20'd143: instruction <= 32'h2108ffff; - 20'd144: instruction <= 32'h1d00fffe; - 20'd145: instruction <= 32'h22b5ffff; - 20'd146: instruction <= 32'h1ea0fff3; - 20'd147: instruction <= 32'h2273ffff; - 20'd148: instruction <= 32'h1e60ffee; - 20'd149: instruction <= 32'h8fbf0004; - 20'd150: instruction <= 32'h8fb00008; - 20'd151: instruction <= 32'h8fb1000c; - 20'd152: instruction <= 32'h8fb20010; - 20'd153: instruction <= 32'h8fb30014; - 20'd154: instruction <= 32'h8fb40018; - 20'd155: instruction <= 32'h8fb5001c; - 20'd156: instruction <= 32'h8fb60020; - 20'd157: instruction <= 32'h23bd0020; - 20'd158: instruction <= 32'h03e00008; - 20'd159: instruction <= 32'h3c084000; - 20'd160: instruction <= 32'h21080010; - 20'd161: instruction <= 32'had000000; - 20'd162: instruction <= 32'h3c080100; - 20'd163: instruction <= 32'h2108ffff; - 20'd164: instruction <= 32'h1d00fffe; - 20'd165: instruction <= 32'h03e00008; - 20'd166: instruction <= 32'h23bdfff4; - 20'd167: instruction <= 32'hafbf0004; - 20'd168: instruction <= 32'hafb00008; - 20'd169: instruction <= 32'hafb1000c; - 20'd170: instruction <= 32'h20900000; - 20'd171: instruction <= 32'h20110001; - 20'd172: instruction <= 32'h02114022; - 20'd173: instruction <= 32'h19000009; - 20'd174: instruction <= 32'h24040000; - 20'd175: instruction <= 32'h2225ffff; - 20'd176: instruction <= 32'h00113021; - 20'd177: instruction <= 32'h0c0000bc; - 20'd178: instruction <= 32'h00022021; - 20'd179: instruction <= 32'h00112821; - 20'd180: instruction <= 32'h0c0000e1; - 20'd181: instruction <= 32'h22310001; - 20'd182: instruction <= 32'h080000ac; - 20'd183: instruction <= 32'h8fbf0004; - 20'd184: instruction <= 32'h8fb00008; - 20'd185: instruction <= 32'h8fb1000c; - 20'd186: instruction <= 32'h23bd000c; - 20'd187: instruction <= 32'h03e00008; - 20'd188: instruction <= 32'h23bdffec; - 20'd189: instruction <= 32'hafb00004; - 20'd190: instruction <= 32'hafb10008; - 20'd191: instruction <= 32'hafb2000c; - 20'd192: instruction <= 32'hafb30010; - 20'd193: instruction <= 32'hafbf0014; - 20'd194: instruction <= 32'h00854022; - 20'd195: instruction <= 32'h19000002; - 20'd196: instruction <= 32'h00801020; - 20'd197: instruction <= 32'h080000da; - 20'd198: instruction <= 32'h00048021; - 20'd199: instruction <= 32'h00058821; - 20'd200: instruction <= 32'h00069021; - 20'd201: instruction <= 32'h02119820; - 20'd202: instruction <= 32'h00139842; - 20'd203: instruction <= 32'h3c084000; - 20'd204: instruction <= 32'h21080060; - 20'd205: instruction <= 32'h00134880; - 20'd206: instruction <= 32'h01284820; - 20'd207: instruction <= 32'h8d290000; - 20'd208: instruction <= 32'h00125080; - 20'd209: instruction <= 32'h01485020; - 20'd210: instruction <= 32'h8d4a0000; - 20'd211: instruction <= 32'h012a4022; - 20'd212: instruction <= 32'h19000003; - 20'd213: instruction <= 32'h2265ffff; - 20'd214: instruction <= 32'h0c0000bc; - 20'd215: instruction <= 32'h080000da; - 20'd216: instruction <= 32'h22640001; - 20'd217: instruction <= 32'h0c0000bc; - 20'd218: instruction <= 32'h8fb00004; - 20'd219: instruction <= 32'h8fb10008; - 20'd220: instruction <= 32'h8fb2000c; - 20'd221: instruction <= 32'h8fb30010; - 20'd222: instruction <= 32'h8fbf0014; - 20'd223: instruction <= 32'h23bd0014; - 20'd224: instruction <= 32'h03e00008; - 20'd225: instruction <= 32'h23bdfff4; - 20'd226: instruction <= 32'hafb00004; - 20'd227: instruction <= 32'hafb10008; - 20'd228: instruction <= 32'hafbf000c; - 20'd229: instruction <= 32'h3c104000; - 20'd230: instruction <= 32'h22100060; - 20'd231: instruction <= 32'h00054080; - 20'd232: instruction <= 32'h02089020; - 20'd233: instruction <= 32'h8e520000; - 20'd234: instruction <= 32'h20b1ffff; - 20'd235: instruction <= 32'h02244022; - 20'd236: instruction <= 32'h05000006; - 20'd237: instruction <= 32'h00114080; - 20'd238: instruction <= 32'h02084020; - 20'd239: instruction <= 32'h8d090000; - 20'd240: instruction <= 32'had090004; - 20'd241: instruction <= 32'h2231ffff; - 20'd242: instruction <= 32'h080000eb; - 20'd243: instruction <= 32'h00044080; - 20'd244: instruction <= 32'h02084020; - 20'd245: instruction <= 32'had120000; - 20'd246: instruction <= 32'h8fb00004; - 20'd247: instruction <= 32'h8fb10008; - 20'd248: instruction <= 32'h8fbf000c; - 20'd249: instruction <= 32'h23bd000c; - 20'd250: instruction <= 32'h03e00008; + 20'd36: instruction <= 32'h0c00002a; + 20'd37: instruction <= 32'h3c084000; + 20'd38: instruction <= 32'h8d040060; + 20'd39: instruction <= 32'h0c000077; + 20'd40: instruction <= 32'h0c00002a; + 20'd41: instruction <= 32'h08000028; + 20'd42: instruction <= 32'h23bdffec; + 20'd43: instruction <= 32'hafbf0004; + 20'd44: instruction <= 32'hafb00008; + 20'd45: instruction <= 32'hafb1000c; + 20'd46: instruction <= 32'hafb20010; + 20'd47: instruction <= 32'hafb30014; + 20'd48: instruction <= 32'h3c104000; + 20'd49: instruction <= 32'h22110010; + 20'd50: instruction <= 32'h22100060; + 20'd51: instruction <= 32'h20120000; + 20'd52: instruction <= 32'h8e130000; + 20'd53: instruction <= 32'h22100004; + 20'd54: instruction <= 32'h00124080; + 20'd55: instruction <= 32'h02084020; + 20'd56: instruction <= 32'h8d040000; + 20'd57: instruction <= 32'h22250000; + 20'd58: instruction <= 32'h0c000046; + 20'd59: instruction <= 32'h22520001; + 20'd60: instruction <= 32'h02724022; + 20'd61: instruction <= 32'h1d00fff8; + 20'd62: instruction <= 32'h0c000070; + 20'd63: instruction <= 32'h8fbf0004; + 20'd64: instruction <= 32'h8fb00008; + 20'd65: instruction <= 32'h8fb1000c; + 20'd66: instruction <= 32'h8fb20010; + 20'd67: instruction <= 32'h8fb30014; + 20'd68: instruction <= 32'h23bd0014; + 20'd69: instruction <= 32'h03e00008; + 20'd70: instruction <= 32'h23bdffe0; + 20'd71: instruction <= 32'hafbf0004; + 20'd72: instruction <= 32'hafb00008; + 20'd73: instruction <= 32'hafb1000c; + 20'd74: instruction <= 32'hafb20010; + 20'd75: instruction <= 32'hafb30014; + 20'd76: instruction <= 32'hafb40018; + 20'd77: instruction <= 32'hafb5001c; + 20'd78: instruction <= 32'hafb60020; + 20'd79: instruction <= 32'h20900000; + 20'd80: instruction <= 32'h20b10000; + 20'd81: instruction <= 32'h3c124000; + 20'd82: instruction <= 32'h22520020; + 20'd83: instruction <= 32'h20130be2; + 20'd84: instruction <= 32'h22140000; + 20'd85: instruction <= 32'h20160100; + 20'd86: instruction <= 32'h20150004; + 20'd87: instruction <= 32'h3288000f; + 20'd88: instruction <= 32'h00084080; + 20'd89: instruction <= 32'h02484020; + 20'd90: instruction <= 32'h8d080000; + 20'd91: instruction <= 32'h01164025; + 20'd92: instruction <= 32'hae280000; + 20'd93: instruction <= 32'h0014a102; + 20'd94: instruction <= 32'h0016b040; + 20'd95: instruction <= 32'h20080400; + 20'd96: instruction <= 32'h2108ffff; + 20'd97: instruction <= 32'h1d00fffe; + 20'd98: instruction <= 32'h22b5ffff; + 20'd99: instruction <= 32'h1ea0fff3; + 20'd100: instruction <= 32'h2273ffff; + 20'd101: instruction <= 32'h1e60ffee; + 20'd102: instruction <= 32'h8fbf0004; + 20'd103: instruction <= 32'h8fb00008; + 20'd104: instruction <= 32'h8fb1000c; + 20'd105: instruction <= 32'h8fb20010; + 20'd106: instruction <= 32'h8fb30014; + 20'd107: instruction <= 32'h8fb40018; + 20'd108: instruction <= 32'h8fb5001c; + 20'd109: instruction <= 32'h8fb60020; + 20'd110: instruction <= 32'h23bd0020; + 20'd111: instruction <= 32'h03e00008; + 20'd112: instruction <= 32'h3c084000; + 20'd113: instruction <= 32'h21080010; + 20'd114: instruction <= 32'had000000; + 20'd115: instruction <= 32'h3c080100; + 20'd116: instruction <= 32'h2108ffff; + 20'd117: instruction <= 32'h1d00fffe; + 20'd118: instruction <= 32'h03e00008; + 20'd119: instruction <= 32'h23bdfff4; + 20'd120: instruction <= 32'hafbf0004; + 20'd121: instruction <= 32'hafb00008; + 20'd122: instruction <= 32'hafb1000c; + 20'd123: instruction <= 32'h20900000; + 20'd124: instruction <= 32'h20110001; + 20'd125: instruction <= 32'h02114022; + 20'd126: instruction <= 32'h19000009; + 20'd127: instruction <= 32'h24040000; + 20'd128: instruction <= 32'h2225ffff; + 20'd129: instruction <= 32'h00113021; + 20'd130: instruction <= 32'h0c00008d; + 20'd131: instruction <= 32'h00022021; + 20'd132: instruction <= 32'h00112821; + 20'd133: instruction <= 32'h0c0000b2; + 20'd134: instruction <= 32'h22310001; + 20'd135: instruction <= 32'h0800007d; + 20'd136: instruction <= 32'h8fbf0004; + 20'd137: instruction <= 32'h8fb00008; + 20'd138: instruction <= 32'h8fb1000c; + 20'd139: instruction <= 32'h23bd000c; + 20'd140: instruction <= 32'h03e00008; + 20'd141: instruction <= 32'h23bdffec; + 20'd142: instruction <= 32'hafb00004; + 20'd143: instruction <= 32'hafb10008; + 20'd144: instruction <= 32'hafb2000c; + 20'd145: instruction <= 32'hafb30010; + 20'd146: instruction <= 32'hafbf0014; + 20'd147: instruction <= 32'h00854022; + 20'd148: instruction <= 32'h19000002; + 20'd149: instruction <= 32'h00801020; + 20'd150: instruction <= 32'h080000ab; + 20'd151: instruction <= 32'h00048021; + 20'd152: instruction <= 32'h00058821; + 20'd153: instruction <= 32'h00069021; + 20'd154: instruction <= 32'h02119820; + 20'd155: instruction <= 32'h00139842; + 20'd156: instruction <= 32'h3c084000; + 20'd157: instruction <= 32'h21080064; + 20'd158: instruction <= 32'h00134880; + 20'd159: instruction <= 32'h01284820; + 20'd160: instruction <= 32'h8d290000; + 20'd161: instruction <= 32'h00125080; + 20'd162: instruction <= 32'h01485020; + 20'd163: instruction <= 32'h8d4a0000; + 20'd164: instruction <= 32'h012a4022; + 20'd165: instruction <= 32'h19000003; + 20'd166: instruction <= 32'h2265ffff; + 20'd167: instruction <= 32'h0c00008d; + 20'd168: instruction <= 32'h080000ab; + 20'd169: instruction <= 32'h22640001; + 20'd170: instruction <= 32'h0c00008d; + 20'd171: instruction <= 32'h8fb00004; + 20'd172: instruction <= 32'h8fb10008; + 20'd173: instruction <= 32'h8fb2000c; + 20'd174: instruction <= 32'h8fb30010; + 20'd175: instruction <= 32'h8fbf0014; + 20'd176: instruction <= 32'h23bd0014; + 20'd177: instruction <= 32'h03e00008; + 20'd178: instruction <= 32'h23bdfff4; + 20'd179: instruction <= 32'hafb00004; + 20'd180: instruction <= 32'hafb10008; + 20'd181: instruction <= 32'hafbf000c; + 20'd182: instruction <= 32'h3c104000; + 20'd183: instruction <= 32'h22100064; + 20'd184: instruction <= 32'h00054080; + 20'd185: instruction <= 32'h02089020; + 20'd186: instruction <= 32'h8e520000; + 20'd187: instruction <= 32'h20b1ffff; + 20'd188: instruction <= 32'h02244022; + 20'd189: instruction <= 32'h05000006; + 20'd190: instruction <= 32'h00114080; + 20'd191: instruction <= 32'h02084020; + 20'd192: instruction <= 32'h8d090000; + 20'd193: instruction <= 32'had090004; + 20'd194: instruction <= 32'h2231ffff; + 20'd195: instruction <= 32'h080000bc; + 20'd196: instruction <= 32'h00044080; + 20'd197: instruction <= 32'h02084020; + 20'd198: instruction <= 32'had120000; + 20'd199: instruction <= 32'h8fb00004; + 20'd200: instruction <= 32'h8fb10008; + 20'd201: instruction <= 32'h8fbf000c; + 20'd202: instruction <= 32'h23bd000c; + 20'd203: instruction <= 32'h03e00008; default: instruction <= 32'h00000000; endcase end diff --git a/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp b/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp index a18d6fc..afc36df 100644 Binary files a/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp and b/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp differ diff --git a/PipelineProcessor.xpr b/PipelineProcessor.xpr index 6e63286..2dff9e6 100644 --- a/PipelineProcessor.xpr +++ b/PipelineProcessor.xpr @@ -60,7 +60,7 @@