diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
index ae917a3..8b1c125 100644
Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem and b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem differ
diff --git a/PipelineProcessor.srcs/sources_1/new/ExecutionForward.v b/PipelineProcessor.srcs/sources_1/new/ExecutionForward.v
index 10dcf1f..e86859e 100644
--- a/PipelineProcessor.srcs/sources_1/new/ExecutionForward.v
+++ b/PipelineProcessor.srcs/sources_1/new/ExecutionForward.v
@@ -13,7 +13,7 @@ module ExecutionForward (
     always @(*) begin
         if (MEM_register_write == 1'b1 && MEM_register_write_address == EX_rs_address &&
         EX_rs_address != 5'b00000) begin
-            IDA_source <= 2'b00;
+            IDA_source <= 2'b01;
         end else begin
             if (WB_register_write == 1'b1 && WB_register_write_address == EX_rs_address &&
             EX_rs_address != 5'b00000) begin
@@ -25,7 +25,7 @@ module ExecutionForward (
 
         if (MEM_register_write == 1'b1 && MEM_register_write_address == EX_rt_address &&
         EX_rt_address != 5'b00000) begin
-            IDB_source <= 2'b00;
+            IDB_source <= 2'b01;
         end else begin
             if (WB_register_write == 1'b1 && WB_register_write_address == EX_rt_address &&
             EX_rt_address != 5'b00000) begin
diff --git a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
index 46665bb..05f3c23 100644
--- a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
+++ b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
@@ -7,26 +7,12 @@ module InstructionMemory (
 
     always @(*) begin
         case (address[31:2])
-            20'd0:   instruction <= 32'h20110002;  //     addi    $s1,    $zero,  2
-            20'd1:   instruction <= 32'h00000000;
-            20'd2:   instruction <= 32'h00000000;
-            20'd3:   instruction <= 32'h00000000;
-            20'd4:   instruction <= 32'h00000000;
-            20'd5:   instruction <= 32'h20120050;  //     addi    $s2,    $zero,  0x50
-            20'd6:   instruction <= 32'h00000000;
-            20'd7:   instruction <= 32'h00000000;
-            20'd8:   instruction <= 32'h00000000;
-            20'd9:   instruction <= 32'h00000000;
-            20'd10:  instruction <= 32'h02408009;  //     jalr    $s2,    $s0
-                                                   // end:
-            20'd11:  instruction <= 32'h0800000b;  //     j       end
-                                                   // Note the address
-            20'd20:  instruction <= 32'h20130003;  //     addi    $s3,    $zero,  3
-            20'd21:  instruction <= 32'h00000000;
-            20'd22:  instruction <= 32'h00000000;
-            20'd23:  instruction <= 32'h00000000;
-            20'd24:  instruction <= 32'h00000000;
-            20'd25:  instruction <= 32'h02000008;  //     jr      $s0
+            20'd0:   instruction <= 32'h20110001;
+            20'd1:   instruction <= 32'h20120002;
+            20'd2:   instruction <= 32'h02319820;
+            20'd3:   instruction <= 32'h02719820;
+            20'd4:   instruction <= 32'h20140003;
+            20'd5:   instruction <= 32'h02729820;
             default: instruction <= 32'h00000000;
         endcase
     end
diff --git a/PipelineProcessor.xpr b/PipelineProcessor.xpr
index 3b3f391..3b3f13e 100644
--- a/PipelineProcessor.xpr
+++ b/PipelineProcessor.xpr
@@ -60,7 +60,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
-    <Option Name="WTXSimLaunchSim" Val="218"/>
+    <Option Name="WTXSimLaunchSim" Val="229"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>