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Memory forward not needed

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un-lock-able
2024-07-11 11:35:55 +08:00
parent 50f625bf09
commit 5fae853c3e
7 changed files with 67 additions and 87 deletions
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BIN
PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb
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110
PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/obj/xsim_2.c
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PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
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13
PipelineProcessor.srcs/sources_1/new/CPU.v
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@@ -82,9 +82,6 @@ module CPU (
wire [1:0] EXforward_IDA_source;
wire [1:0] EXforward_IDB_source;
// Out of mem forward
wire MEMforward_MEM_write_data_source;
// Out of data memory
wire [31:0] datamemory_read_data;
wire [31:0] bcd_hardwire_control;
@@ -180,10 +177,7 @@ module CPU (
.prev_ALU_result(EX_ALU_result),
.prev_memory_write_data(EX_memory_write_data),
.prev_register_write_destination(EX_register_write_destination),
.prev_rt_address(EX_rt_address),
.MEM_write_data_source(MEMforward_MEM_write_data_source),
.WB_forwarded_data(WB_register_write_data),
.rt_address(MEM_rt_address),
.register_write(MEM_register_write),
.WB_source(MEM_WB_source),
.memory_read_data(MEM_memory_read_data),
@@ -230,13 +224,6 @@ module CPU (
.IDB_source(EXforward_IDB_source)
);
MemoryForward memory_forward (
.WB_register_write(WB_register_write),
.WB_register_write_address(WB_register_write_address),
.MEM_rt_address(MEM_rt_address),
.MEM_write_data_source(MEMforward_MEM_write_data_source)
);
HazardUnit hazard_unit (
.PC_jump(ID_PC_jump),
.is_loadword(ID_is_loadword),

17
PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
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@@ -7,12 +7,17 @@ module InstructionMemory (
always @(*) begin
case (address[31:2])
20'd0: instruction <= 32'h20110001;
20'd1: instruction <= 32'h20120002;
20'd2: instruction <= 32'h02319820;
20'd3: instruction <= 32'h02719820;
20'd4: instruction <= 32'h20140003;
20'd5: instruction <= 32'h02729820;
20'd0: instruction <= 32'h3c104000;
20'd6: instruction <= 32'h2011000a;
20'd11: instruction <= 32'hae110010;
20'd16: instruction <= 32'h8e120010;
20'd21: instruction <= 32'h2231fffe;
20'd26: instruction <= 32'h02329820;
20'd31: instruction <= 32'h02529821;
20'd36: instruction <= 32'h02519822;
20'd41: instruction <= 32'h02338823;
20'd46: instruction <= 32'h26310004;
20'd51: instruction <= 32'h02339018;
default: instruction <= 32'h00000000;
endcase
end

12
PipelineProcessor.srcs/sources_1/new/MemoryAccess.v
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@@ -9,13 +9,8 @@ module MemoryAccess (
input [31:0] prev_ALU_result,
input [31:0] prev_memory_write_data,
input [4:0] prev_register_write_destination,
input [4:0] prev_rt_address,
// From forward unit
input MEM_write_data_source,
// From WB
input [31:0] WB_forwarded_data,
// To Forward unit
output [4:0] rt_address,
// To next stage
output register_write,
output WB_source,
@@ -36,7 +31,6 @@ module MemoryAccess (
reg [31:0] MEM_ALU_result;
reg [31:0] MEM_memory_write_data;
reg [4:0] MEM_register_write_destination;
reg [4:0] MEM_rt_address;
// wire memory_write_data_include_forward;
// assign memory_write_data_include_forward = (MEM_write_data_source == 1'b0) ?
@@ -51,11 +45,9 @@ module MemoryAccess (
// );
assign data_memory_write = MEM_memory_write;
assign data_memory_address = MEM_ALU_result;
assign data_memory_write_data = (MEM_write_data_source == 1'b0) ?
MEM_memory_write_data : WB_forwarded_data;
assign data_memory_write_data = MEM_memory_write_data;
assign memory_read_data = data_memory_read_data;
assign rt_address = MEM_rt_address;
assign register_write = MEM_register_write;
assign WB_source = MEM_WB_source;
assign ALU_result = MEM_ALU_result;
@@ -69,7 +61,6 @@ module MemoryAccess (
MEM_ALU_result <= 32'h00000000;
MEM_memory_write_data <= 32'h00000000;
MEM_register_write_destination <= 5'b00000;
MEM_rt_address <= 5'b00000;
end else begin
MEM_register_write <= prev_register_write;
MEM_WB_source <= prev_WB_source;
@@ -77,7 +68,6 @@ module MemoryAccess (
MEM_ALU_result <= prev_ALU_result;
MEM_memory_write_data <= prev_memory_write_data;
MEM_register_write_destination <= prev_register_write_destination;
MEM_rt_address <= prev_rt_address;
end
end
endmodule

2
PipelineProcessor.xpr
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@@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="229"/>
<Option Name="WTXSimLaunchSim" Val="233"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>