diff --git a/PipelineProcessor.cache/ip/2023.2/1/1/11b3438a8319906c/stats.txt b/PipelineProcessor.cache/ip/2023.2/1/1/11b3438a8319906c/stats.txt new file mode 100644 index 0000000..abffcc4 --- /dev/null +++ b/PipelineProcessor.cache/ip/2023.2/1/1/11b3438a8319906c/stats.txt @@ -0,0 +1,2 @@ +NumberHits:1 +Timestamp: Mon Jul 15 13:17:30 UTC 2024 diff --git a/PipelineProcessor.cache/ip/2023.2/4/7/479d0a32832fbf86/479d0a32832fbf86.xci b/PipelineProcessor.cache/ip/2023.2/4/7/479d0a32832fbf86/479d0a32832fbf86.xci new file mode 100644 index 0000000..7c3a428 --- /dev/null +++ b/PipelineProcessor.cache/ip/2023.2/4/7/479d0a32832fbf86/479d0a32832fbf86.xci @@ -0,0 +1,295 @@ + + + xilinx.com + ipcache + 479d0a32832fbf86 + 0 + + + phase_locked_loop + + + 100000000 + 100000000 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + BUFG + 249.979 + false + 300.046 + 50.000 + 68.000 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + phase_locked_loop + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 51 + 0.000 + false + 10.000 + 10.000 + 15 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 5 + None + 0.010 + 0.010 + false + 1 + false + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + PLL + mmcm_adv + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + artix7 + xc7a35t + fgg484 + VERILOG + + -1 + + + e6a05ff8 + 479d0a32832fbf86 + phase_locked_loop + $Change: 4016217 $ + 401ad827 + 27 + IP_Unknown + 13 + TRUE + . + + . + 2023.2 + GLOBAL + + + + diff --git a/PipelineProcessor.cache/ip/2023.2/4/7/479d0a32832fbf86/phase_locked_loop.dcp b/PipelineProcessor.cache/ip/2023.2/4/7/479d0a32832fbf86/phase_locked_loop.dcp new file mode 100644 index 0000000..8e2a3f3 Binary files /dev/null and b/PipelineProcessor.cache/ip/2023.2/4/7/479d0a32832fbf86/phase_locked_loop.dcp differ diff --git a/PipelineProcessor.cache/ip/2023.2/4/7/479d0a32832fbf86/phase_locked_loop_sim_netlist.v b/PipelineProcessor.cache/ip/2023.2/4/7/479d0a32832fbf86/phase_locked_loop_sim_netlist.v new file mode 100644 index 0000000..51130d8 --- /dev/null +++ b/PipelineProcessor.cache/ip/2023.2/4/7/479d0a32832fbf86/phase_locked_loop_sim_netlist.v @@ -0,0 +1,220 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 +// Date : Mon Jul 15 20:50:13 2024 +// Host : Viviana running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_sim_netlist.v +// Design : phase_locked_loop +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a35tfgg484-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (clk_out1, + reset, + locked, + clk_in1); + output clk_out1; + input reset; + output locked; + input clk_in1; + + (* IBUF_LOW_PWR *) wire clk_in1; + wire clk_out1; + wire locked; + wire reset; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_phase_locked_loop_clk_wiz inst + (.clk_in1(clk_in1), + .clk_out1(clk_out1), + .locked(locked), + .reset(reset)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_phase_locked_loop_clk_wiz + (clk_out1, + reset, + locked, + clk_in1); + output clk_out1; + input reset; + output locked; + input clk_in1; + + wire clk_in1; + wire clk_in1_phase_locked_loop; + wire clk_out1; + wire clk_out1_phase_locked_loop; + wire clkfbout_buf_phase_locked_loop; + wire clkfbout_phase_locked_loop; + wire locked; + wire reset; + wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_plle2_adv_inst_DRDY_UNCONNECTED; + wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_phase_locked_loop), + .O(clkfbout_buf_phase_locked_loop)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufg + (.I(clk_in1), + .O(clk_in1_phase_locked_loop)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(clk_out1_phase_locked_loop), + .O(clk_out1)); + (* BOX_TYPE = "PRIMITIVE" *) + PLLE2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT(51), + .CLKFBOUT_PHASE(0.000000), + .CLKIN1_PERIOD(10.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE(15), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(5), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .STARTUP_WAIT("FALSE")) + plle2_adv_inst + (.CLKFBIN(clkfbout_buf_phase_locked_loop), + .CLKFBOUT(clkfbout_phase_locked_loop), + .CLKIN1(clk_in1_phase_locked_loop), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKOUT0(clk_out1_phase_locked_loop), + .CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED), + .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(locked), + .PWRDWN(1'b0), + .RST(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/PipelineProcessor.ip_user_files/ip/phase_locked_loop/phase_locked_loop_stub.v b/PipelineProcessor.cache/ip/2023.2/4/7/479d0a32832fbf86/phase_locked_loop_stub.v similarity index 77% rename from PipelineProcessor.ip_user_files/ip/phase_locked_loop/phase_locked_loop_stub.v rename to PipelineProcessor.cache/ip/2023.2/4/7/479d0a32832fbf86/phase_locked_loop_stub.v index caf51d8..d18a9ba 100644 --- a/PipelineProcessor.ip_user_files/ip/phase_locked_loop/phase_locked_loop_stub.v +++ b/PipelineProcessor.cache/ip/2023.2/4/7/479d0a32832fbf86/phase_locked_loop_stub.v @@ -2,10 +2,10 @@ // Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -// Date : Thu Jul 11 13:35:55 2024 +// Date : Mon Jul 15 20:50:13 2024 // Host : Viviana running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_stub.v // Design : phase_locked_loop // Purpose : Stub declaration of top-level module interface // Device : xc7a35tfgg484-1 @@ -14,7 +14,7 @@ // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. -module phase_locked_loop(clk_out1, reset, locked, clk_in1) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, reset, locked, clk_in1) /* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */ /* synthesis syn_force_seq_prim="clk_out1" */; output clk_out1 /* synthesis syn_isclock = 1 */; diff --git a/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/de0769b94d28978f.xci b/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/de0769b94d28978f.xci new file mode 100644 index 0000000..8cc23ad --- /dev/null +++ b/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/de0769b94d28978f.xci @@ -0,0 +1,295 @@ + + + xilinx.com + ipcache + de0769b94d28978f + 0 + + + phase_locked_loop + + + 100000000 + 100000000 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + BUFG + 313.062 + false + 310.955 + 50.000 + 60.000 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + phase_locked_loop + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 42 + 0.000 + false + 10.000 + 10.000 + 14 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 5 + None + 0.010 + 0.010 + false + 1 + false + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + PLL + mmcm_adv + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + true + false + true + false + false + false + artix7 + xc7a35t + fgg484 + VERILOG + + -1 + + + e6a05ff8 + de0769b94d28978f + phase_locked_loop + $Change: 4016217 $ + 401ad827 + 28 + IP_Unknown + 13 + TRUE + . + + . + 2023.2 + GLOBAL + + + + diff --git a/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/phase_locked_loop.dcp b/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/phase_locked_loop.dcp new file mode 100644 index 0000000..3321428 Binary files /dev/null and b/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/phase_locked_loop.dcp differ diff --git a/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/phase_locked_loop_sim_netlist.v b/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/phase_locked_loop_sim_netlist.v new file mode 100644 index 0000000..c8664fc --- /dev/null +++ b/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/phase_locked_loop_sim_netlist.v @@ -0,0 +1,220 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 +// Date : Mon Jul 15 20:38:44 2024 +// Host : Viviana running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_sim_netlist.v +// Design : phase_locked_loop +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a35tfgg484-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (clk_out1, + reset, + locked, + clk_in1); + output clk_out1; + input reset; + output locked; + input clk_in1; + + (* IBUF_LOW_PWR *) wire clk_in1; + wire clk_out1; + wire locked; + wire reset; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_phase_locked_loop_clk_wiz inst + (.clk_in1(clk_in1), + .clk_out1(clk_out1), + .locked(locked), + .reset(reset)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_phase_locked_loop_clk_wiz + (clk_out1, + reset, + locked, + clk_in1); + output clk_out1; + input reset; + output locked; + input clk_in1; + + wire clk_in1; + wire clk_in1_phase_locked_loop; + wire clk_out1; + wire clk_out1_phase_locked_loop; + wire clkfbout_buf_phase_locked_loop; + wire clkfbout_phase_locked_loop; + wire locked; + wire reset; + wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_plle2_adv_inst_DRDY_UNCONNECTED; + wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_phase_locked_loop), + .O(clkfbout_buf_phase_locked_loop)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufg + (.I(clk_in1), + .O(clk_in1_phase_locked_loop)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(clk_out1_phase_locked_loop), + .O(clk_out1)); + (* BOX_TYPE = "PRIMITIVE" *) + PLLE2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT(42), + .CLKFBOUT_PHASE(0.000000), + .CLKIN1_PERIOD(10.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE(14), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(5), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .STARTUP_WAIT("FALSE")) + plle2_adv_inst + (.CLKFBIN(clkfbout_buf_phase_locked_loop), + .CLKFBOUT(clkfbout_phase_locked_loop), + .CLKIN1(clk_in1_phase_locked_loop), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKOUT0(clk_out1_phase_locked_loop), + .CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED), + .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(locked), + .PWRDWN(1'b0), + .RST(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/phase_locked_loop_stub.v b/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/phase_locked_loop_stub.v new file mode 100644 index 0000000..aa5de28 --- /dev/null +++ b/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/phase_locked_loop_stub.v @@ -0,0 +1,24 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 +// Date : Mon Jul 15 20:38:44 2024 +// Host : Viviana running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_stub.v +// Design : phase_locked_loop +// Purpose : Stub declaration of top-level module interface +// Device : xc7a35tfgg484-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, reset, locked, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */ +/* synthesis syn_force_seq_prim="clk_out1" */; + output clk_out1 /* synthesis syn_isclock = 1 */; + input reset; + output locked; + input clk_in1; +endmodule diff --git a/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/stats.txt b/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/stats.txt new file mode 100644 index 0000000..7d10d9b --- /dev/null +++ b/PipelineProcessor.cache/ip/2023.2/d/e/de0769b94d28978f/stats.txt @@ -0,0 +1,2 @@ +NumberHits:1 +Timestamp: Mon Jul 15 12:55:34 UTC 2024 diff --git a/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp b/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp index f0c0893..7caf4ae 100644 Binary files a/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp and b/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp differ diff --git a/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v b/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v index 4ae91f0..dff48cb 100644 --- a/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v +++ b/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v @@ -2,10 +2,10 @@ // Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -// Date : Thu Jul 11 13:35:55 2024 +// Date : Thu Jul 11 13:35:54 2024 // Host : Viviana running 64-bit major release (build 9200) -// Command : write_verilog -force -mode funcsim -// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v +// Command : write_verilog -force -mode funcsim -rename_top phase_locked_loop -prefix +// phase_locked_loop_ phase_locked_loop_sim_netlist.v // Design : phase_locked_loop // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -29,14 +29,14 @@ module phase_locked_loop wire locked; wire reset; - phase_locked_loop_clk_wiz inst + phase_locked_loop_phase_locked_loop_clk_wiz inst (.clk_in1(clk_in1), .clk_out1(clk_out1), .locked(locked), .reset(reset)); endmodule -module phase_locked_loop_clk_wiz +module phase_locked_loop_phase_locked_loop_clk_wiz (clk_out1, reset, locked, diff --git a/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v b/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v index caf51d8..5886057 100644 --- a/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v +++ b/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v @@ -2,10 +2,10 @@ // Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -// Date : Thu Jul 11 13:35:55 2024 +// Date : Thu Jul 11 13:35:54 2024 // Host : Viviana running 64-bit major release (build 9200) -// Command : write_verilog -force -mode synth_stub -// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v +// Command : write_verilog -force -mode synth_stub -rename_top phase_locked_loop -prefix +// phase_locked_loop_ phase_locked_loop_stub.v // Design : phase_locked_loop // Purpose : Stub declaration of top-level module interface // Device : xc7a35tfgg484-1 diff --git a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/activehdl/README.txt b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/activehdl/README.txt index ef41b4b..4e5ade7 100644 --- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/activehdl/README.txt +++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/activehdl/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024 +# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024 # ################################################################################ diff --git a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/modelsim/README.txt b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/modelsim/README.txt index ef41b4b..4e5ade7 100644 --- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/modelsim/README.txt +++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/modelsim/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024 +# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024 # ################################################################################ diff --git a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/questa/README.txt b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/questa/README.txt index ef41b4b..4e5ade7 100644 --- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/questa/README.txt +++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/questa/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024 +# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024 # ################################################################################ diff --git a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/riviera/README.txt b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/riviera/README.txt index ef41b4b..4e5ade7 100644 --- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/riviera/README.txt +++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/riviera/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024 +# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024 # ################################################################################ diff --git a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/vcs/README.txt b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/vcs/README.txt index ef41b4b..4e5ade7 100644 --- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/vcs/README.txt +++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/vcs/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024 +# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024 # ################################################################################ diff --git a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xcelium/README.txt b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xcelium/README.txt index ef41b4b..4e5ade7 100644 --- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xcelium/README.txt +++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xcelium/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024 +# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024 # ################################################################################ diff --git a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xsim/README.txt b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xsim/README.txt index ef41b4b..4e5ade7 100644 --- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xsim/README.txt +++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xsim/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024 +# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024 # ################################################################################ diff --git a/PipelineProcessor.runs/impl_1/CPU.vdi b/PipelineProcessor.runs/impl_1/CPU.vdi index ac2792c..416ca11 100644 --- a/PipelineProcessor.runs/impl_1/CPU.vdi +++ b/PipelineProcessor.runs/impl_1/CPU.vdi @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Sat Jul 13 23:39:15 2024 -# Process ID: 27020 +# Start of session at: Mon Jul 15 21:30:00 2024 +# Process ID: 34208 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1 # Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi @@ -12,13 +12,13 @@ # Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB #----------------------------------------------------------- source CPU.tcl -notrace -create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 461.707 ; gain = 184.406 +create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 462.992 ; gain = 184.602 Command: link_design -top CPU -part xc7a35tfgg484-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7a35tfgg484-1 INFO: [Project 1-454] Reading design checkpoint 'd:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp' for cell 'pll' -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 916.031 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.131 . Memory (MB): peak = 916.242 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 3508 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.2 @@ -28,18 +28,18 @@ Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/Pipelin Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54] INFO: [Timing 38-2] Deriving generated clocks [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54] -get_clocks: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1599.215 ; gain = 558.836 +get_clocks: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1599.602 ; gain = 559.164 Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst' Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc] Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1599.215 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1599.602 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:13 . Memory (MB): peak = 1599.215 ; gain = 1122.352 +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1599.602 ; gain = 1123.602 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' @@ -50,112 +50,112 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.715 . Memory (MB): peak = 1599.215 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.641 . Memory (MB): peak = 1599.602 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 1f0fa50d6 +Ending Cache Timing Information Task | Checksum: 2009eb4ca -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.490 . Memory (MB): peak = 1613.043 ; gain = 13.828 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1613.895 ; gain = 14.293 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup -Phase 1.1 Core Generation And Design Setup | Checksum: 1f0fa50d6 +Phase 1.1 Core Generation And Design Setup | Checksum: 2009eb4ca -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1979.137 ; gain = 0.000 Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1f0fa50d6 +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2009eb4ca -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Phase 1 Initialization | Checksum: 1f0fa50d6 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Phase 1 Initialization | Checksum: 2009eb4ca -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1979.137 ; gain = 0.000 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 1f0fa50d6 +Phase 2.1 Timer Update | Checksum: 2009eb4ca -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.387 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.360 . Memory (MB): peak = 1979.137 ; gain = 0.000 Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 1f0fa50d6 +Phase 2.2 Timing Data Collection | Checksum: 2009eb4ca -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.405 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Phase 2 Timer Update And Timing Data Collection | Checksum: 1f0fa50d6 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.374 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Phase 2 Timer Update And Timing Data Collection | Checksum: 2009eb4ca -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.407 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.375 . Memory (MB): peak = 1979.137 ; gain = 0.000 Phase 3 Retarget INFO: [Opt 31-1566] Pulled 13 inverters resulting in an inversion of 263 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: 1e587632b +Phase 3 Retarget | Checksum: 1362abf1f -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.567 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Retarget | Checksum: 1e587632b +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Retarget | Checksum: 1362abf1f INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 14 cells INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: 1b5603850 +Phase 4 Constant propagation | Checksum: 164c5dc3c -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.652 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Constant propagation | Checksum: 1b5603850 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.595 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Constant propagation | Checksum: 164c5dc3c INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep -Phase 5 Sweep | Checksum: 15ea6b1a3 +Phase 5 Sweep | Checksum: 1aad7b8f8 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.816 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Sweep | Checksum: 15ea6b1a3 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.753 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Sweep | Checksum: 1aad7b8f8 INFO: [Opt 31-389] Phase Sweep created 12 cells and removed 0 cells Phase 6 BUFG optimization -Phase 6 BUFG optimization | Checksum: 15ea6b1a3 +Phase 6 BUFG optimization | Checksum: 1aad7b8f8 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.949 . Memory (MB): peak = 1972.328 ; gain = 0.000 -BUFG optimization | Checksum: 15ea6b1a3 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.867 . Memory (MB): peak = 1979.137 ; gain = 0.000 +BUFG optimization | Checksum: 1aad7b8f8 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: 15ea6b1a3 +Phase 7 Shift Register Optimization | Checksum: 1aad7b8f8 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.959 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Shift Register Optimization | Checksum: 15ea6b1a3 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.876 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Shift Register Optimization | Checksum: 1aad7b8f8 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: 118407d59 +Phase 8 Post Processing Netlist | Checksum: 1e3f1f4ce -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.991 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Post Processing Netlist | Checksum: 118407d59 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.908 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Post Processing Netlist | Checksum: 1e3f1f4ce INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1587ffb16 +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2361cfa52 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Phase 9.2 Verifying Netlist Connectivity | Checksum: 1587ffb16 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Phase 9.2 Verifying Netlist Connectivity | Checksum: 2361cfa52 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Phase 9 Finalization | Checksum: 1587ffb16 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Phase 9 Finalization | Checksum: 2361cfa52 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000 Opt_design Change Summary ========================= @@ -172,28 +172,28 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- -Ending Logic Optimization Task | Checksum: 1587ffb16 +Ending Logic Optimization Task | Checksum: 2361cfa52 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1979.137 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 1587ffb16 +Ending Power Optimization Task | Checksum: 2361cfa52 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1979.137 ; gain = 0.000 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1587ffb16 +Ending Final Cleanup Task | Checksum: 2361cfa52 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1979.137 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1587ffb16 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 2361cfa52 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1979.137 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully @@ -204,16 +204,16 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt. report_drc completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1979.137 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1972.328 ; gain = 0.000 Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Wrote RouteStorage: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1979.137 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_opt.dcp' has been generated. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -233,54 +233,54 @@ Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1979.137 ; gain = 0.000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14ae9822c -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1972.328 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1979.137 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1979.137 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b434b971 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: c5c27cdb -Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: c5c27cdb -Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 1 Placer Initialization | Checksum: c5c27cdb -Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 146e69098 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 151ff6269 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 151ff6269 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: a33c0039 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:12 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 55 LUT instances to create LUTNM shape @@ -296,7 +296,7 @@ INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2039.625 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2034.871 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ @@ -320,53 +320,53 @@ Summary of Physical Synthesis Optimizations Phase 2.4.2 Physical Synthesis In Placer | Checksum: f4053bc8 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 2.4 Global Placement Core | Checksum: 1099bb7b7 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 2 Global Placement | Checksum: 1099bb7b7 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 10f07ac64 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:14 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1626a5454 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 14fc2b59e -Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 169ab9d86 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 10a431286 +Phase 3.5 Small Shape Detail Placement | Checksum: 1aa221702 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:24 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 145095dfd +Phase 3.6 Re-assign LUT pins | Checksum: 1a5685b79 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:24 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 1b6341a4b +Phase 3.7 Pipeline Register Optimization | Checksum: 2169317c7 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297 -Phase 3 Detail Placement | Checksum: 1b6341a4b +Time (s): cpu = 00:00:08 ; elapsed = 00:00:24 . Memory (MB): peak = 2034.871 ; gain = 55.734 +Phase 3 Detail Placement | Checksum: 2169317c7 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:24 . Memory (MB): peak = 2034.871 ; gain = 55.734 Phase 4 Post Placement Optimization and Clean-Up @@ -374,7 +374,7 @@ Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 253ce2c5c +Post Placement Optimization Initialization | Checksum: 2b42d29d8 Phase 4.1.1.1 BUFG Insertion @@ -383,33 +383,33 @@ Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.979 | TNS=0.000 | -Phase 1 Physical Synthesis Initialization | Checksum: 16956e8df +Phase 1 Physical Synthesis Initialization | Checksum: 2a752e597 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.808 . Memory (MB): peak = 2085.480 ; gain = 13.727 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.687 . Memory (MB): peak = 2077.816 ; gain = 9.480 INFO: [Place 46-33] Processed net data_memory/reset, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. -Ending Physical Synthesis Task | Checksum: 16956e8df +Ending Physical Synthesis Task | Checksum: 2a752e597 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2087.383 ; gain = 15.629 -Phase 4.1.1.1 BUFG Insertion | Checksum: 253ce2c5c +Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2079.719 ; gain = 11.383 +Phase 4.1.1.1 BUFG Insertion | Checksum: 2b42d29d8 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.719 ; gain = 100.582 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=2.979. For the most accurate timing information please run report_timing. -Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1e8b73056 +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 249162dd2 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.719 ; gain = 100.582 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 -Phase 4.1 Post Commit Optimization | Checksum: 1e8b73056 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.719 ; gain = 100.582 +Phase 4.1 Post Commit Optimization | Checksum: 249162dd2 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.719 ; gain = 100.582 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 1e8b73056 +Phase 4.2 Post Placement Cleanup | Checksum: 249162dd2 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582 Phase 4.3 Placer Reporting @@ -428,42 +428,42 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion | West| 1x1| 1x1| |___________|___________________|___________________| -Phase 4.3.1 Print Estimated Congestion | Checksum: 1e8b73056 +Phase 4.3.1 Print Estimated Congestion | Checksum: 249162dd2 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 -Phase 4.3 Placer Reporting | Checksum: 1e8b73056 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582 +Phase 4.3 Placer Reporting | Checksum: 249162dd2 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2087.383 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2079.719 ; gain = 0.000 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 11ee518f9 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17f441675 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 -Ending Placer Task | Checksum: 91ee5898 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582 +Ending Placer Task | Checksum: f24d5614 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582 66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:33 . Memory (MB): peak = 2087.383 ; gain = 115.055 +place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 2079.719 ; gain = 100.582 INFO: [runtcl-4] Executing : report_io -file CPU_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 2087.383 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 2079.719 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 2087.383 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 2079.719 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2105.285 ; gain = 2.945 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2105.285 ; gain = 2.945 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.285 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2095.105 ; gain = 1.957 +Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2095.105 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2095.105 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2105.285 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 2105.285 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2105.285 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2105.285 ; gain = 2.945 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2095.105 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2095.105 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2095.105 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2095.105 ; gain = 1.957 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_placed.dcp' has been generated. Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -471,23 +471,23 @@ INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc Starting Initial Update Timing Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 2150.406 ; gain = 45.121 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2141.781 ; gain = 46.676 INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 75 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 2175.750 ; gain = 7.027 -Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2177.184 ; gain = 1.434 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2177.184 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 2167.066 ; gain = 6.965 +Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2167.965 ; gain = 1.836 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2167.965 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2177.184 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 2177.184 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2177.184 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2177.184 ; gain = 8.461 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2167.965 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2167.965 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2167.965 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2167.965 ; gain = 7.863 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -502,29 +502,29 @@ Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design -Checksum: PlaceDB: 7d4dfd1d ConstDB: 0 ShapeSum: 14a05b7b RouteDB: 0 -Post Restoration Checksum: NetGraph: 678b964f | NumContArr: 2f28cab3 | Constraints: c2a8fa9d | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 21c06563c +Checksum: PlaceDB: ddacfa99 ConstDB: 0 ShapeSum: 14a05b7b RouteDB: 0 +Post Restoration Checksum: NetGraph: 7bb36a25 | NumContArr: 2f28cab3 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 2302e2a12 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 2288.059 ; gain = 82.391 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 2284.527 ; gain = 85.477 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 21c06563c +Phase 2.1 Fix Topology Constraints | Checksum: 2302e2a12 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 2288.059 ; gain = 82.391 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 2284.527 ; gain = 85.477 Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 21c06563c +Phase 2.2 Pre Route Cleanup | Checksum: 2302e2a12 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 2288.059 ; gain = 82.391 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 2284.527 ; gain = 85.477 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing -Phase 2.3 Update Timing | Checksum: 30afab1eb +Phase 2.3 Update Timing | Checksum: 2fed2e595 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:18 . Memory (MB): peak = 2305.797 ; gain = 100.129 +Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 2302.227 ; gain = 103.176 INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.232 | TNS=0.000 | WHS=-0.150 | THS=-18.367| @@ -540,87 +540,86 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 2 Router Initialization | Checksum: 3338dbc90 +Phase 2 Router Initialization | Checksum: 32765f03a -Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.363 ; gain = 141.695 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:20 . Memory (MB): peak = 2345.152 ; gain = 146.102 Phase 3 Initial Routing Phase 3.1 Global Routing -Phase 3.1 Global Routing | Checksum: 3338dbc90 +Phase 3.1 Global Routing | Checksum: 32765f03a -Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.363 ; gain = 141.695 +Time (s): cpu = 00:00:11 ; elapsed = 00:00:20 . Memory (MB): peak = 2345.152 ; gain = 146.102 Phase 3.2 Initial Net Routing -Phase 3.2 Initial Net Routing | Checksum: 18b5441e3 +Phase 3.2 Initial Net Routing | Checksum: 2af1be2f2 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:21 . Memory (MB): peak = 2348.094 ; gain = 142.426 -Phase 3 Initial Routing | Checksum: 18b5441e3 +Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 2349.547 ; gain = 150.496 +Phase 3 Initial Routing | Checksum: 2af1be2f2 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:21 . Memory (MB): peak = 2348.094 ; gain = 142.426 +Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 2349.547 ; gain = 150.496 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 3428 - Number of Nodes with overlaps = 278 - Number of Nodes with overlaps = 35 - Number of Nodes with overlaps = 12 - Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 3351 + Number of Nodes with overlaps = 253 + Number of Nodes with overlaps = 33 + Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.537 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.748 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 2a3342fb1 +Phase 4.1 Global Iteration 0 | Checksum: 1c65aeb4f -Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.875 ; gain = 147.207 -Phase 4 Rip-up And Reroute | Checksum: 2a3342fb1 +Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.629 ; gain = 156.578 +Phase 4 Rip-up And Reroute | Checksum: 1c65aeb4f -Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.875 ; gain = 147.207 +Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.629 ; gain = 156.578 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing -Phase 5.1.1 Update Timing | Checksum: 294396ac7 +Phase 5.1.1 Update Timing | Checksum: 19ccb358b -Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.879 ; gain = 147.211 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.537 | TNS=0.000 | WHS=N/A | THS=N/A | +Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.629 ; gain = 156.578 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.748 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 5.1 Delay CleanUp | Checksum: 294396ac7 +Phase 5.1 Delay CleanUp | Checksum: 19ccb358b -Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.879 ; gain = 147.211 +Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.633 ; gain = 156.582 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 294396ac7 +Phase 5.2 Clock Skew Optimization | Checksum: 19ccb358b -Time (s): cpu = 00:00:06 ; elapsed = 00:00:34 . Memory (MB): peak = 2352.879 ; gain = 147.211 -Phase 5 Delay and Skew Optimization | Checksum: 294396ac7 +Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.633 ; gain = 156.582 +Phase 5 Delay and Skew Optimization | Checksum: 19ccb358b -Time (s): cpu = 00:00:06 ; elapsed = 00:00:34 . Memory (MB): peak = 2352.879 ; gain = 147.211 +Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.633 ; gain = 156.582 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 26ed22ad4 +Phase 6.1.1 Update Timing | Checksum: 1aefd8a0c -Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.537 | TNS=0.000 | WHS=0.055 | THS=0.000 | +Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2355.633 ; gain = 156.582 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.748 | TNS=0.000 | WHS=0.055 | THS=0.000 | -Phase 6.1 Hold Fix Iter | Checksum: 26dd53850 +Phase 6.1 Hold Fix Iter | Checksum: 1aff898c0 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211 -Phase 6 Post Hold Fix | Checksum: 26dd53850 +Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2355.633 ; gain = 156.582 +Phase 6 Post Hold Fix | Checksum: 1aff898c0 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211 +Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2355.633 ; gain = 156.582 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 15.1075 % - Global Horizontal Routing Utilization = 15.2186 % + Global Vertical Routing Utilization = 15.1128 % + Global Horizontal Routing Utilization = 15.1869 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -630,44 +629,44 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 7 Route finalize | Checksum: 26dd53850 +Phase 7 Route finalize | Checksum: 1aff898c0 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211 +Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2355.633 ; gain = 156.582 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 26dd53850 +Phase 8 Verifying routed nets | Checksum: 1aff898c0 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.930 ; gain = 149.262 +Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2357.648 ; gain = 158.598 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 1e498ff47 +Phase 9 Depositing Routes | Checksum: 17c6dc57b -Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.930 ; gain = 149.262 +Time (s): cpu = 00:00:15 ; elapsed = 00:00:34 . Memory (MB): peak = 2357.648 ; gain = 158.598 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=3.537 | TNS=0.000 | WHS=0.055 | THS=0.000 | +INFO: [Route 35-57] Estimated Timing Summary | WNS=3.748 | TNS=0.000 | WHS=0.055 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 1e498ff47 +Phase 10 Post Router Timing | Checksum: 17c6dc57b -Time (s): cpu = 00:00:07 ; elapsed = 00:00:36 . Memory (MB): peak = 2354.930 ; gain = 149.262 +Time (s): cpu = 00:00:15 ; elapsed = 00:00:35 . Memory (MB): peak = 2357.648 ; gain = 158.598 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing -Phase 11 Post-Route Event Processing | Checksum: 118a89fd7 +Phase 11 Post-Route Event Processing | Checksum: ff332dbf -Time (s): cpu = 00:00:07 ; elapsed = 00:00:37 . Memory (MB): peak = 2354.930 ; gain = 149.262 -Ending Routing Task | Checksum: 118a89fd7 +Time (s): cpu = 00:00:15 ; elapsed = 00:00:35 . Memory (MB): peak = 2357.648 ; gain = 158.598 +Ending Routing Task | Checksum: ff332dbf -Time (s): cpu = 00:00:07 ; elapsed = 00:00:37 . Memory (MB): peak = 2354.930 ; gain = 149.262 +Time (s): cpu = 00:00:15 ; elapsed = 00:00:36 . Memory (MB): peak = 2357.648 ; gain = 158.598 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 90 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:38 . Memory (MB): peak = 2354.930 ; gain = 177.746 +route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:37 . Memory (MB): peak = 2357.648 ; gain = 189.684 INFO: [runtcl-4] Executing : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx Command: report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. @@ -680,7 +679,7 @@ INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt. report_methodology completed successfully -report_methodology: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2436.516 ; gain = 81.586 +report_methodology: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2430.602 ; gain = 72.953 INFO: [runtcl-4] Executing : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx Command: report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. @@ -700,16 +699,16 @@ INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU_bus_sk INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2498.938 ; gain = 4.973 -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2499.391 ; gain = 0.453 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2499.391 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2499.625 ; gain = 4.914 +Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2499.625 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2499.625 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.230 . Memory (MB): peak = 2499.391 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 2499.391 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2499.391 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2499.391 ; gain = 5.426 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.218 . Memory (MB): peak = 2499.625 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2499.625 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2499.625 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2499.625 ; gain = 4.914 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_routed.dcp' has been generated. Command: write_bitstream -force CPU.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -753,5 +752,5 @@ INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT dev INFO: [Common 17-83] Releasing license: Implementation 14 Infos, 13 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2964.719 ; gain = 465.328 -INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 23:41:35 2024... +write_bitstream: Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 2965.840 ; gain = 466.215 +INFO: [Common 17-206] Exiting Vivado at Mon Jul 15 21:32:10 2024... diff --git a/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt index 5aff5a0..2957080 100644 --- a/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 23:41:19 2024 +| Date : Mon Jul 15 21:31:56 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_bus_skew -warn_on_violation -file CPU_bus_skew_routed.rpt -pb CPU_bus_skew_routed.pb -rpx CPU_bus_skew_routed.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt index efb197d..53153a8 100644 --- a/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 23:41:19 2024 +| Date : Mon Jul 15 21:31:56 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_clock_utilization -file CPU_clock_utilization_routed.rpt | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt b/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt index 421c6d5..d619175 100644 --- a/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 23:40:17 2024 +| Date : Mon Jul 15 21:30:56 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_control_sets -verbose -file CPU_control_sets_placed.rpt | Design : CPU @@ -73,549 +73,549 @@ Table of Contents +--------------------+------------------------------------------------------------+------------------------------+------------------+----------------+--------------+ | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | +--------------------+------------------------------------------------------------+------------------------------+------------------+----------------+--------------+ -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_20[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_4[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | instruction_decode/register_file/p_0_in | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[10][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[24][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[2][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[12][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[30][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[21][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[25][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[31][31]_i_1_n_0 | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[23][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[29][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[13][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[26][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[4][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[8][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[11][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[16][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[19][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[17][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[5][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[28][31]_i_1_n_0 | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[27][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[3][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[9][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[14][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[18][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[22][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[7][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | execution/alu/E[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_5[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_24[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_27[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_52[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_43[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_3[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_37[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_4[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_23[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_25[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_38[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_39[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_42[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_45[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_8[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_7[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_22[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_34[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_46[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_48[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_9[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_50[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_36[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_35[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_0[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_7[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_8[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_28[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_29[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_30[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_40[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_58[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_6[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_5[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_31[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_19[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_49[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_4[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_26[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_44[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_47[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_6[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_51[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_32[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_33[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_41[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_12[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_13[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_4[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_11[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_11[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_14[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_0[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_19[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_20[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_26[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_6[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_12[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_10[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_18[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_21[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_15[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_22[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_8[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_13[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_9[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_7[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_10[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_16[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_17[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_23[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_24[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_28[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_30[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_30[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_31[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_27[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_32[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_33[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_25[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_29[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_5[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_3[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_57[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_4[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_33[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_35[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_19[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_42[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_44[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_27[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_6[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_56[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_52[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_34[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_21[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_27[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_30[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_7[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_23[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_10[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_35[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_29[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_36[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_22[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_37[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_13[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_38[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_39[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_25[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_31[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_46[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_14[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_47[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_15[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_20[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_48[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_54[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_11[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_40[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_5[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_24[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_32[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_5[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_53[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_55[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_36[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_16[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_17[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_45[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_41[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_49[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_50[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_2[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_34[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_28[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_43[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_51[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_63[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_8[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_60[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_7[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_62[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_6[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_59[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_61[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_2[0] | data_memory/reset | 10 | 32 | 3.20 | | pll/inst/clk_out1 | write_back/E[0] | data_memory/reset | 13 | 32 | 2.46 | | pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[1]_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[3]_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_13[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_24[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_5[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_7[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_11[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_16[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_40[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_5[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_30[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_6[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_6[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_11[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_23[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_12[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_32[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_41[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_7[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_15[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_12[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_29[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_11[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_13[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_14[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_15[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_26[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_16[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_8[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_14[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_20[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_9[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_13[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_9[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_10[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_17[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_7[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_25[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_6[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_10[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_31[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_17[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_9[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_22[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_27[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_28[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_4[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_8[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_10[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_12[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/E[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_26[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_19[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_21[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_4[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_0[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_0[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_11[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_1[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_0[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_4[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_12[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_6[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_14[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_0[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_17[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_18[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__9_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_5[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_10[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__14_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__17_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[13][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[16][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[21][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[22][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[23][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[26][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[27][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[29][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[30][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[31][31]_i_1_n_0 | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[28][31]_i_1_n_0 | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[4][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[3][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[14][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[10][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[19][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[5][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[7][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[18][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[8][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[24][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[9][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[25][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[12][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[17][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[11][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[2][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/p_0_in | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | execution/alu/E[0] | data_memory/reset | 9 | 32 | 3.56 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_2[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__26_1[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_13[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_16[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_3[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_15[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_2[0] | data_memory/reset | 7 | 32 | 4.57 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_22[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__17_1[0] | data_memory/reset | 11 | 32 | 2.91 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_1[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_2[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_4[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_2[0] | data_memory/reset | 11 | 32 | 2.91 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_0[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_0[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_20[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_4[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__26_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__9_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_1[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_10[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_23[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_24[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_25[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__27_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__30_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_4[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__29_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__30_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_3[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_0[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_5[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_0[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_6[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__14_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_0[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/E[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_4[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_2[0] | data_memory/reset | 10 | 32 | 3.20 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_28[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_9[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_0[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_0[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_0[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_6[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_5[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_4[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_4[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_21[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_14[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_24[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_17[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_4[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_4[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_18[0] | data_memory/reset | 9 | 32 | 3.56 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_27[0] | data_memory/reset | 16 | 32 | 2.00 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_2[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_2[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_4[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_20[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_5[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_1[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_2[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_4[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_5[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_1[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_8[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_7[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_1[0] | data_memory/reset | 13 | 32 | 2.46 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_3[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_4[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_6[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_5[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_12[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_3[0] | data_memory/reset | 15 | 32 | 2.13 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_2[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_11[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_2[0] | data_memory/reset | 7 | 32 | 4.57 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_22[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_2[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_16[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_5[0] | data_memory/reset | 11 | 32 | 2.91 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_19[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_26[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_13[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_8[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_2[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[3]_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_5[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_23[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_25[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_15[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_9[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_0[0] | data_memory/reset | 13 | 32 | 2.46 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_19[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_23[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_11[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_5[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_20[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_12[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_10[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_26[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_9[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_4[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_7[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_10[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_30[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_13[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_8[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_25[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_18[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_15[0] | data_memory/reset | 9 | 32 | 3.56 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_24[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_11[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_9[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_26[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__29_1[0] | data_memory/reset | 13 | 32 | 2.46 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_27[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_6[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_11[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_12[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_13[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_14[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_14[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_17[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_19[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_22[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_29[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_0[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_16[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_0[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_28[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_16[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_25[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_30[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_5[0] | data_memory/reset | 18 | 32 | 1.78 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_6[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_12[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_29[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_4[0] | data_memory/reset | 11 | 32 | 2.91 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_31[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_4[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_5[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_1[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_10[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_15[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_16[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_17[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_18[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_13[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_20[0] | data_memory/reset | 15 | 32 | 2.13 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_7[0] | data_memory/reset | 13 | 32 | 2.46 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_8[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_21[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_9[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_10[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_15[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__30_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_19[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_11[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_18[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_22[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_12[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_10[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_12[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_13[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_0[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_4[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_14[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_6[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__27_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_2[0] | data_memory/reset | 14 | 32 | 2.29 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_14[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_7[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_14[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_17[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_23[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_29[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_3[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_25[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_32[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_22[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_34[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_20[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_9[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_25[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_27[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_30[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_21[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_5[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_7[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_28[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_8[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_0[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_23[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_5[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_17[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_11[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_20[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__30_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_13[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_21[0] | data_memory/reset | 14 | 32 | 2.29 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_38[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_35[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_23[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_5[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_11[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_24[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_37[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_1[0] | data_memory/reset | 19 | 32 | 1.68 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_16[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_17[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_28[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_5[0] | data_memory/reset | 13 | 32 | 2.46 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_6[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_11[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_25[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_8[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_6[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_15[0] | data_memory/reset | 10 | 32 | 3.20 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_22[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_8[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_11[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_10[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_12[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_36[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_33[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_13[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_15[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_14[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_13[0] | data_memory/reset | 13 | 32 | 2.46 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_30[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_23[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_12[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_24[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_18[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_8[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_31[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_23[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_33[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_21[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_7[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_9[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_22[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_20[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_20[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_24[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_35[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_17[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_5[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_10[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_36[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_9[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_3[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_13[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_25[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_3[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_37[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_16[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_21[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_14[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_29[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_12[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_32[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_19[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_34[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_10[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_15[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_4[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_13[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_14[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_27[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_20[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_26[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_30[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_31[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_35[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_27[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_37[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_12[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_7[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_18[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_13[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_28[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_21[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_29[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_38[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_39[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_34[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_9[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_10[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_4[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_11[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_12[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_13[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_25[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_33[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_14[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_15[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_16[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_11[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_40[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_23[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_41[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_32[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_17[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_24[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_36[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_8[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_20[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_22[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_22[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_10[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_15[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_23[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_8[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_19[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_24[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_25[0] | data_memory/reset | 11 | 32 | 2.91 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_16[0] | data_memory/reset | 11 | 32 | 2.91 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_17[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_19[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_18[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_6[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_20[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_26[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_6[0] | data_memory/reset | 13 | 32 | 2.46 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_31[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_24[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_4[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_12[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_15[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_10[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_16[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_21[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_32[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_33[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_35[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_24[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_31[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_36[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_37[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_25[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_26[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_29[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_34[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_21[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_23[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_28[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_22[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_38[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_39[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_0[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_14[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_29[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_28[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_31[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_37[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_39[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_4[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_40[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_38[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_19[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_29[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_8[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_28[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_9[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_6[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_11[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_10[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_11[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_17[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_33[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_9[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_34[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_35[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_41[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_13[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_30[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_32[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_12[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_14[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_23[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_32[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_5[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_6[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_12[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_16[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_26[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_27[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_30[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_27[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_20[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_22[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_36[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_10[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_5[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_7[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_15[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_31[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_24[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_13[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_25[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_43[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_47[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_48[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_4[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_50[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_7[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_8[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_52[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_8[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_5[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_42[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_3[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_51[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_9[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_0[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_45[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_44[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_46[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_6[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_49[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_5[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_6[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_9[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_10[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_11[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_14[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_20[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_21[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_22[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_6[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_23[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_22[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_23[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_26[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_18[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_16[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_19[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_9[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_30[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_34[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_5[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_11[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_13[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_20[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_10[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_15[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_29[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_19[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_24[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_7[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_10[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_8[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_2[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_5[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_0[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_33[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_13[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_25[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_4[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_16[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_35[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_28[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_15[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_3[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_17[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_6[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_11[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_21[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_17[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_27[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_12[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_14[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_31[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_7[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_32[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_36[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_12[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_13[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_7[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_39[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_52[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_50[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_53[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_42[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_8[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_37[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_24[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_46[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_25[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_55[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_34[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_44[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_45[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_41[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_31[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_58[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_57[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_43[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_59[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_48[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_62[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_36[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_5[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_51[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_35[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_27[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_29[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_6[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_63[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_33[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_54[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_60[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_9[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_56[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_30[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_49[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_28[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_38[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_40[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_32[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_47[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_61[0] | data_memory/reset | 18 | 32 | 1.78 | | pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_3[0] | data_memory/reset | 15 | 44 | 2.93 | | pll/inst/clk_out1 | | execution/alu/IFID_PC_plus_4 | 20 | 67 | 3.35 | | pll/inst/clk_out1 | | execution/alu/SR[0] | 41 | 160 | 3.90 | diff --git a/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt b/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt index b39c5a2..5042f28 100644 --- a/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 23:39:42 2024 +| Date : Mon Jul 15 21:30:24 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt index 9971a5c..7d31d75 100644 --- a/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 23:41:07 2024 +| Date : Mon Jul 15 21:31:43 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt b/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt index 0399a2d..f41ccbc 100644 --- a/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 23:40:16 2024 +| Date : Mon Jul 15 21:30:56 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_io -file CPU_io_placed.rpt | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt index ddca496..c736933 100644 --- a/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 23:41:13 2024 +| Date : Mon Jul 15 21:31:49 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_opt.dcp b/PipelineProcessor.runs/impl_1/CPU_opt.dcp index bf4e1f3..cd87cf0 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_opt.dcp and b/PipelineProcessor.runs/impl_1/CPU_opt.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_physopt.dcp b/PipelineProcessor.runs/impl_1/CPU_physopt.dcp index 812ab7a..d0df80e 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_physopt.dcp and b/PipelineProcessor.runs/impl_1/CPU_physopt.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_placed.dcp b/PipelineProcessor.runs/impl_1/CPU_placed.dcp index 46e9daa..c4c2d16 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_placed.dcp and b/PipelineProcessor.runs/impl_1/CPU_placed.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt index 2422188..ae1843b 100644 --- a/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 23:41:18 2024 +| Date : Mon Jul 15 21:31:54 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx | Design : CPU @@ -74,7 +74,7 @@ Table of Contents +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ -| Vccint | 1.000 | 0.038 | 0.029 | 0.010 | NA | Unspecified | NA | +| Vccint | 1.000 | 0.039 | 0.029 | 0.010 | NA | Unspecified | NA | | Vccaux | 1.800 | 0.063 | 0.050 | 0.013 | NA | Unspecified | NA | | Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | diff --git a/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb b/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb index bf66feb..a78ed81 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb and b/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_routed.dcp b/PipelineProcessor.runs/impl_1/CPU_routed.dcp index 8a2948b..7554fd7 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_routed.dcp and b/PipelineProcessor.runs/impl_1/CPU_routed.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb index 9db88e4..91df9ff 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb and b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt index 4f4daf3..7838601 100644 --- a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 23:41:19 2024 +| Date : Mon Jul 15 21:31:55 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -report_unconstrained -file CPU_timing_summary_routed.rpt -pb CPU_timing_summary_routed.pb -rpx CPU_timing_summary_routed.rpx -warn_on_violation | Design : CPU @@ -142,7 +142,7 @@ Table of Contents WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 3.567 0.000 0 35779 0.055 0.000 0 35779 3.000 0.000 0 18138 + 3.719 0.000 0 35779 0.055 0.000 0 35779 3.000 0.000 0 18138 All user specified timing constraints are met. @@ -168,7 +168,7 @@ hardware_clk {0.000 5.000} 10.000 100.000 Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- hardware_clk 3.000 0.000 0 1 - clk_out1_phase_locked_loop 3.567 0.000 0 35779 0.055 0.000 0 35779 9.500 0.000 0 18134 + clk_out1_phase_locked_loop 3.719 0.000 0 35779 0.055 0.000 0 35779 9.500 0.000 0 18134 clkfbout_phase_locked_loop 17.845 0.000 0 3 @@ -248,7 +248,7 @@ High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 5.000 From Clock: clk_out1_phase_locked_loop To Clock: clk_out1_phase_locked_loop -Setup : 0 Failing Endpoints, Worst Slack 3.567ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 3.719ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.055ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 9.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- @@ -256,19 +256,19 @@ PW : 0 Failing Endpoints, Worst Slack 9.500ns, Total Vio Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 3.567ns (required time - arrival time) - Source: write_back/WB_WB_source_reg/C +Slack (MET) : 3.719ns (required time - arrival time) + Source: write_back/WB_register_write_destination_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[30]_rep/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.219ns (logic 8.344ns (51.446%) route 7.875ns (48.554%)) - Logic Levels: 12 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=2) - Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Data Path Delay: 15.999ns (logic 8.309ns (51.935%) route 7.690ns (48.065%)) + Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT6=3) + Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.956ns = ( 18.044 - 20.000 ) - Source Clock Delay (SCD): -2.421ns + Source Clock Delay (SCD): -2.353ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -287,41 +287,43 @@ Slack (MET) : 3.567ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 - SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C + net (fo=18132, routed) 1.623 -2.353 write_back/clk_out1 + SLICE_X5Y53 FDRE r write_back/WB_register_write_destination_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q - net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source - SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O - net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] - SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O - net (fo=2, routed) 0.560 2.844 execution/result0__0_4 - SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O - net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] - DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) - 4.240 8.261 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + SLICE_X5Y53 FDRE (Prop_fdre_C_Q) 0.456 -1.897 r write_back/WB_register_write_destination_reg[2]/Q + net (fo=26, routed) 1.478 -0.419 write_back/Q[2] + SLICE_X3Y54 LUT4 (Prop_lut4_I0_O) 0.152 -0.267 r write_back/result0_i_55/O + net (fo=1, routed) 0.640 0.373 write_back/result0_i_55_n_0 + SLICE_X3Y53 LUT6 (Prop_lut6_I2_O) 0.332 0.705 r write_back/result0_i_34/O + net (fo=34, routed) 1.251 1.956 memory_access/result0__0_0 + SLICE_X15Y45 LUT6 (Prop_lut6_I4_O) 0.124 2.080 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.654 2.734 execution/result0__0_3 + SLICE_X12Y45 LUT3 (Prop_lut3_I2_O) 0.124 2.858 r execution/result0__0_i_16/O + net (fo=141, routed) 1.215 4.073 execution/alu/ALU_in1[1] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.109 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.111 execution/alu/result0__0_n_106 DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.781 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 - SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + 1.518 9.629 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.423 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.547 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.547 execution/alu/i__carry_i_3__0_n_0 SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + 0.550 11.097 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.097 execution/alu/result0_inferred__11/i__carry_n_0 SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.363 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.363 execution/alu/result0_inferred__11/i__carry__0_n_0 + 0.114 11.211 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.211 execution/alu/result0_inferred__11/i__carry__0_n_0 SLICE_X11Y37 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.477 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.477 execution/alu/result0_inferred__11/i__carry__1_n_0 + 0.114 11.325 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.325 execution/alu/result0_inferred__11/i__carry__1_n_0 SLICE_X11Y38 CARRY4 (Prop_carry4_CI_O[2]) - 0.239 11.716 r execution/alu/result0_inferred__11/i__carry__2/O[2] - net (fo=1, routed) 0.667 12.383 execution/alu/result0_inferred__11/i__carry__2_n_5 - SLICE_X5Y38 LUT4 (Prop_lut4_I3_O) 0.302 12.685 r execution/alu/MEM_ALU_result[30]_i_3/O - net (fo=2, routed) 0.506 13.191 execution/alu/MEM_ALU_result[30]_i_3_n_0 - SLICE_X4Y38 LUT6 (Prop_lut6_I2_O) 0.124 13.315 r execution/alu/MEM_ALU_result[30]_rep_i_1/O - net (fo=1, routed) 0.483 13.798 memory_access/MEM_ALU_result_reg[30]_rep_29 + 0.239 11.564 r execution/alu/result0_inferred__11/i__carry__2/O[2] + net (fo=1, routed) 0.667 12.231 execution/alu/result0_inferred__11/i__carry__2_n_5 + SLICE_X5Y38 LUT4 (Prop_lut4_I3_O) 0.302 12.533 r execution/alu/MEM_ALU_result[30]_i_3/O + net (fo=2, routed) 0.506 13.039 execution/alu/MEM_ALU_result[30]_i_3_n_0 + SLICE_X4Y38 LUT6 (Prop_lut6_I2_O) 0.124 13.163 r execution/alu/MEM_ALU_result[30]_rep_i_1/O + net (fo=1, routed) 0.483 13.646 memory_access/MEM_ALU_result_reg[30]_rep_29 SLICE_X5Y40 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/D ------------------------------------------------------------------- ------------------- @@ -342,109 +344,23 @@ Slack (MET) : 3.567ns (required time - arrival time) SLICE_X5Y40 FDRE (Setup_fdre_C_D) -0.067 17.364 memory_access/MEM_ALU_result_reg[30]_rep ------------------------------------------------------------------- required time 17.364 - arrival time -13.798 + arrival time -13.646 ------------------------------------------------------------------- - slack 3.567 + slack 3.719 -Slack (MET) : 3.609ns (required time - arrival time) - Source: write_back/WB_WB_source_reg/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[23]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.276ns (logic 8.318ns (51.107%) route 7.958ns (48.893%)) - Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) - Clock Path Skew: -0.039ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.955ns = ( 18.045 - 20.000 ) - Source Clock Delay (SCD): -2.421ns - Clock Pessimism Removal (CPR): -0.505ns - Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 - SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q - net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source - SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O - net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] - SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O - net (fo=2, routed) 0.560 2.844 execution/result0__0_4 - SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O - net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] - DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) - 4.240 8.261 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 - DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.781 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 - SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 - SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[3]) - 0.313 11.562 r execution/alu/result0_inferred__11/i__carry__0/O[3] - net (fo=1, routed) 0.559 12.121 execution/alu/result0_inferred__11/i__carry__0_n_4 - SLICE_X6Y36 LUT4 (Prop_lut4_I3_O) 0.306 12.427 r execution/alu/MEM_ALU_result[23]_i_11/O - net (fo=1, routed) 0.722 13.150 execution/alu/MEM_ALU_result[23]_i_11_n_0 - SLICE_X3Y40 LUT6 (Prop_lut6_I5_O) 0.124 13.274 r execution/alu/MEM_ALU_result[23]_i_4/O - net (fo=1, routed) 0.456 13.730 execution/alu/MEM_ALU_result[23]_i_4_n_0 - SLICE_X5Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.854 r execution/alu/MEM_ALU_result[23]_i_1/O - net (fo=1, routed) 0.000 13.854 memory_access/prev_ALU_result[23] - SLICE_X5Y42 FDRE r memory_access/MEM_ALU_result_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 20.000 20.000 r - R4 0.000 20.000 r hardware_clk (IN) - net (fo=0) 0.000 20.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.516 18.045 memory_access/clk_out1 - SLICE_X5Y42 FDRE r memory_access/MEM_ALU_result_reg[23]/C - clock pessimism -0.505 17.540 - clock uncertainty -0.108 17.432 - SLICE_X5Y42 FDRE (Setup_fdre_C_D) 0.031 17.463 memory_access/MEM_ALU_result_reg[23] - ------------------------------------------------------------------- - required time 17.463 - arrival time -13.854 - ------------------------------------------------------------------- - slack 3.609 - -Slack (MET) : 3.610ns (required time - arrival time) - Source: write_back/WB_WB_source_reg/C +Slack (MET) : 3.762ns (required time - arrival time) + Source: write_back/WB_register_write_destination_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[25]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.271ns (logic 8.450ns (51.933%) route 7.821ns (48.067%)) - Logic Levels: 12 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) - Clock Path Skew: -0.041ns (DCD - SCD + CPR) + Data Path Delay: 16.051ns (logic 8.415ns (52.427%) route 7.636ns (47.573%)) + Logic Levels: 13 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT6=4) + Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.957ns = ( 18.043 - 20.000 ) - Source Clock Delay (SCD): -2.421ns + Source Clock Delay (SCD): -2.353ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -463,40 +379,42 @@ Slack (MET) : 3.610ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 - SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C + net (fo=18132, routed) 1.623 -2.353 write_back/clk_out1 + SLICE_X5Y53 FDRE r write_back/WB_register_write_destination_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q - net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source - SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O - net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] - SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O - net (fo=2, routed) 0.560 2.844 execution/result0__0_4 - SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O - net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] - DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) - 4.240 8.261 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + SLICE_X5Y53 FDRE (Prop_fdre_C_Q) 0.456 -1.897 r write_back/WB_register_write_destination_reg[2]/Q + net (fo=26, routed) 1.478 -0.419 write_back/Q[2] + SLICE_X3Y54 LUT4 (Prop_lut4_I0_O) 0.152 -0.267 r write_back/result0_i_55/O + net (fo=1, routed) 0.640 0.373 write_back/result0_i_55_n_0 + SLICE_X3Y53 LUT6 (Prop_lut6_I2_O) 0.332 0.705 r write_back/result0_i_34/O + net (fo=34, routed) 1.251 1.956 memory_access/result0__0_0 + SLICE_X15Y45 LUT6 (Prop_lut6_I4_O) 0.124 2.080 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.654 2.734 execution/result0__0_3 + SLICE_X12Y45 LUT3 (Prop_lut3_I2_O) 0.124 2.858 r execution/result0__0_i_16/O + net (fo=141, routed) 1.215 4.073 execution/alu/ALU_in1[1] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.109 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.111 execution/alu/result0__0_n_106 DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.781 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 - SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + 1.518 9.629 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.423 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.547 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.547 execution/alu/i__carry_i_3__0_n_0 SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + 0.550 11.097 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.097 execution/alu/result0_inferred__11/i__carry_n_0 SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.363 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.363 execution/alu/result0_inferred__11/i__carry__0_n_0 + 0.114 11.211 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.211 execution/alu/result0_inferred__11/i__carry__0_n_0 SLICE_X11Y37 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 11.697 r execution/alu/result0_inferred__11/i__carry__1/O[1] - net (fo=1, routed) 0.683 12.380 execution/alu/result0_inferred__11/i__carry__1_n_6 - SLICE_X5Y37 LUT4 (Prop_lut4_I3_O) 0.303 12.683 r execution/alu/MEM_ALU_result[25]_i_11/O - net (fo=1, routed) 0.469 13.153 execution/alu/MEM_ALU_result[25]_i_11_n_0 - SLICE_X2Y39 LUT6 (Prop_lut6_I5_O) 0.124 13.277 r execution/alu/MEM_ALU_result[25]_i_4/O - net (fo=1, routed) 0.449 13.726 execution/alu/MEM_ALU_result[25]_i_4_n_0 - SLICE_X4Y38 LUT6 (Prop_lut6_I3_O) 0.124 13.850 r execution/alu/MEM_ALU_result[25]_i_1/O - net (fo=1, routed) 0.000 13.850 memory_access/prev_ALU_result[25] + 0.334 11.545 r execution/alu/result0_inferred__11/i__carry__1/O[1] + net (fo=1, routed) 0.683 12.228 execution/alu/result0_inferred__11/i__carry__1_n_6 + SLICE_X5Y37 LUT4 (Prop_lut4_I3_O) 0.303 12.531 r execution/alu/MEM_ALU_result[25]_i_11/O + net (fo=1, routed) 0.469 13.000 execution/alu/MEM_ALU_result[25]_i_11_n_0 + SLICE_X2Y39 LUT6 (Prop_lut6_I5_O) 0.124 13.124 r execution/alu/MEM_ALU_result[25]_i_4/O + net (fo=1, routed) 0.449 13.574 execution/alu/MEM_ALU_result[25]_i_4_n_0 + SLICE_X4Y38 LUT6 (Prop_lut6_I3_O) 0.124 13.698 r execution/alu/MEM_ALU_result[25]_i_1/O + net (fo=1, routed) 0.000 13.698 memory_access/prev_ALU_result[25] SLICE_X4Y38 FDRE r memory_access/MEM_ALU_result_reg[25]/D ------------------------------------------------------------------- ------------------- @@ -517,23 +435,23 @@ Slack (MET) : 3.610ns (required time - arrival time) SLICE_X4Y38 FDRE (Setup_fdre_C_D) 0.029 17.459 memory_access/MEM_ALU_result_reg[25] ------------------------------------------------------------------- required time 17.459 - arrival time -13.850 + arrival time -13.698 ------------------------------------------------------------------- - slack 3.610 + slack 3.762 -Slack (MET) : 3.670ns (required time - arrival time) - Source: write_back/WB_WB_source_reg/C +Slack (MET) : 3.782ns (required time - arrival time) + Source: write_back/WB_register_write_destination_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[29]/D + Destination: memory_access/MEM_ALU_result_reg[23]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.213ns (logic 8.564ns (52.823%) route 7.649ns (47.177%)) - Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=2) - Clock Path Skew: -0.041ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.957ns = ( 18.043 - 20.000 ) - Source Clock Delay (SCD): -2.421ns + Data Path Delay: 16.035ns (logic 8.283ns (51.657%) route 7.752ns (48.343%)) + Logic Levels: 12 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT6=4) + Clock Path Skew: -0.107ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.955ns = ( 18.045 - 20.000 ) + Source Clock Delay (SCD): -2.353ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -552,43 +470,133 @@ Slack (MET) : 3.670ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 - SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C + net (fo=18132, routed) 1.623 -2.353 write_back/clk_out1 + SLICE_X5Y53 FDRE r write_back/WB_register_write_destination_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q - net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source - SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O - net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] - SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O - net (fo=2, routed) 0.560 2.844 execution/result0__0_4 - SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O - net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] - DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) - 4.240 8.261 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + SLICE_X5Y53 FDRE (Prop_fdre_C_Q) 0.456 -1.897 r write_back/WB_register_write_destination_reg[2]/Q + net (fo=26, routed) 1.478 -0.419 write_back/Q[2] + SLICE_X3Y54 LUT4 (Prop_lut4_I0_O) 0.152 -0.267 r write_back/result0_i_55/O + net (fo=1, routed) 0.640 0.373 write_back/result0_i_55_n_0 + SLICE_X3Y53 LUT6 (Prop_lut6_I2_O) 0.332 0.705 r write_back/result0_i_34/O + net (fo=34, routed) 1.251 1.956 memory_access/result0__0_0 + SLICE_X15Y45 LUT6 (Prop_lut6_I4_O) 0.124 2.080 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.654 2.734 execution/result0__0_3 + SLICE_X12Y45 LUT3 (Prop_lut3_I2_O) 0.124 2.858 r execution/result0__0_i_16/O + net (fo=141, routed) 1.215 4.073 execution/alu/ALU_in1[1] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.109 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.111 execution/alu/result0__0_n_106 DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.781 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 - SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + 1.518 9.629 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.423 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.547 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.547 execution/alu/i__carry_i_3__0_n_0 SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + 0.550 11.097 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.097 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 11.410 r execution/alu/result0_inferred__11/i__carry__0/O[3] + net (fo=1, routed) 0.559 11.969 execution/alu/result0_inferred__11/i__carry__0_n_4 + SLICE_X6Y36 LUT4 (Prop_lut4_I3_O) 0.306 12.275 r execution/alu/MEM_ALU_result[23]_i_11/O + net (fo=1, routed) 0.702 12.977 execution/alu/MEM_ALU_result[23]_i_11_n_0 + SLICE_X3Y40 LUT6 (Prop_lut6_I5_O) 0.124 13.101 r execution/alu/MEM_ALU_result[23]_i_4/O + net (fo=1, routed) 0.456 13.557 execution/alu/MEM_ALU_result[23]_i_4_n_0 + SLICE_X5Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.681 r execution/alu/MEM_ALU_result[23]_i_1/O + net (fo=1, routed) 0.000 13.681 memory_access/prev_ALU_result[23] + SLICE_X5Y42 FDRE r memory_access/MEM_ALU_result_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 20.000 20.000 r + R4 0.000 20.000 r hardware_clk (IN) + net (fo=0) 0.000 20.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.516 18.045 memory_access/clk_out1 + SLICE_X5Y42 FDRE r memory_access/MEM_ALU_result_reg[23]/C + clock pessimism -0.505 17.540 + clock uncertainty -0.108 17.432 + SLICE_X5Y42 FDRE (Setup_fdre_C_D) 0.031 17.463 memory_access/MEM_ALU_result_reg[23] + ------------------------------------------------------------------- + required time 17.463 + arrival time -13.681 + ------------------------------------------------------------------- + slack 3.782 + +Slack (MET) : 3.822ns (required time - arrival time) + Source: write_back/WB_register_write_destination_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: memory_access/MEM_ALU_result_reg[29]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 15.993ns (logic 8.529ns (53.331%) route 7.464ns (46.669%)) + Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT5=1 LUT6=3) + Clock Path Skew: -0.109ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.957ns = ( 18.043 - 20.000 ) + Source Clock Delay (SCD): -2.353ns + Clock Pessimism Removal (CPR): -0.505ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.623 -2.353 write_back/clk_out1 + SLICE_X5Y53 FDRE r write_back/WB_register_write_destination_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y53 FDRE (Prop_fdre_C_Q) 0.456 -1.897 r write_back/WB_register_write_destination_reg[2]/Q + net (fo=26, routed) 1.478 -0.419 write_back/Q[2] + SLICE_X3Y54 LUT4 (Prop_lut4_I0_O) 0.152 -0.267 r write_back/result0_i_55/O + net (fo=1, routed) 0.640 0.373 write_back/result0_i_55_n_0 + SLICE_X3Y53 LUT6 (Prop_lut6_I2_O) 0.332 0.705 r write_back/result0_i_34/O + net (fo=34, routed) 1.251 1.956 memory_access/result0__0_0 + SLICE_X15Y45 LUT6 (Prop_lut6_I4_O) 0.124 2.080 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.654 2.734 execution/result0__0_3 + SLICE_X12Y45 LUT3 (Prop_lut3_I2_O) 0.124 2.858 r execution/result0__0_i_16/O + net (fo=141, routed) 1.215 4.073 execution/alu/ALU_in1[1] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.109 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.111 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.629 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.423 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.547 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.547 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.097 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.097 execution/alu/result0_inferred__11/i__carry_n_0 SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.363 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.363 execution/alu/result0_inferred__11/i__carry__0_n_0 + 0.114 11.211 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.211 execution/alu/result0_inferred__11/i__carry__0_n_0 SLICE_X11Y37 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.477 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.477 execution/alu/result0_inferred__11/i__carry__1_n_0 + 0.114 11.325 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.325 execution/alu/result0_inferred__11/i__carry__1_n_0 SLICE_X11Y38 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 11.811 r execution/alu/result0_inferred__11/i__carry__2/O[1] - net (fo=1, routed) 0.671 12.482 execution/alu/result0_inferred__11/i__carry__2_n_6 - SLICE_X5Y38 LUT4 (Prop_lut4_I3_O) 0.303 12.785 r execution/alu/MEM_ALU_result[29]_i_10/O - net (fo=1, routed) 0.438 13.222 execution/alu/MEM_ALU_result[29]_i_10_n_0 - SLICE_X3Y39 LUT5 (Prop_lut5_I4_O) 0.124 13.346 r execution/alu/MEM_ALU_result[29]_i_4/O - net (fo=1, routed) 0.321 13.667 execution/alu/MEM_ALU_result[29]_i_4_n_0 - SLICE_X4Y38 LUT6 (Prop_lut6_I3_O) 0.124 13.791 r execution/alu/MEM_ALU_result[29]_i_1/O - net (fo=1, routed) 0.000 13.791 memory_access/prev_ALU_result[29] + 0.334 11.659 r execution/alu/result0_inferred__11/i__carry__2/O[1] + net (fo=1, routed) 0.671 12.330 execution/alu/result0_inferred__11/i__carry__2_n_6 + SLICE_X5Y38 LUT4 (Prop_lut4_I3_O) 0.303 12.633 r execution/alu/MEM_ALU_result[29]_i_10/O + net (fo=1, routed) 0.438 13.070 execution/alu/MEM_ALU_result[29]_i_10_n_0 + SLICE_X3Y39 LUT5 (Prop_lut5_I4_O) 0.124 13.194 r execution/alu/MEM_ALU_result[29]_i_4/O + net (fo=1, routed) 0.321 13.515 execution/alu/MEM_ALU_result[29]_i_4_n_0 + SLICE_X4Y38 LUT6 (Prop_lut6_I3_O) 0.124 13.639 r execution/alu/MEM_ALU_result[29]_i_1/O + net (fo=1, routed) 0.000 13.639 memory_access/prev_ALU_result[29] SLICE_X4Y38 FDRE r memory_access/MEM_ALU_result_reg[29]/D ------------------------------------------------------------------- ------------------- @@ -609,202 +617,23 @@ Slack (MET) : 3.670ns (required time - arrival time) SLICE_X4Y38 FDRE (Setup_fdre_C_D) 0.031 17.461 memory_access/MEM_ALU_result_reg[29] ------------------------------------------------------------------- required time 17.461 - arrival time -13.791 + arrival time -13.639 ------------------------------------------------------------------- - slack 3.670 + slack 3.822 -Slack (MET) : 3.737ns (required time - arrival time) - Source: write_back/WB_WB_source_reg/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[31]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.148ns (logic 8.546ns (52.923%) route 7.602ns (47.077%)) - Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT5=1 LUT6=3) - Clock Path Skew: -0.040ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.956ns = ( 18.044 - 20.000 ) - Source Clock Delay (SCD): -2.421ns - Clock Pessimism Removal (CPR): -0.505ns - Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 - SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q - net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source - SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O - net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] - SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O - net (fo=2, routed) 0.560 2.844 execution/result0__0_4 - SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O - net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] - DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) - 4.240 8.261 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 - DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.781 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 - SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 - SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.363 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.363 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X11Y37 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.477 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.477 execution/alu/result0_inferred__11/i__carry__1_n_0 - SLICE_X11Y38 CARRY4 (Prop_carry4_CI_O[3]) - 0.313 11.790 r execution/alu/result0_inferred__11/i__carry__2/O[3] - net (fo=1, routed) 0.570 12.361 execution/alu/result0_inferred__11/i__carry__2_n_4 - SLICE_X6Y39 LUT5 (Prop_lut5_I0_O) 0.306 12.667 r execution/alu/MEM_ALU_result[31]_i_16/O - net (fo=1, routed) 0.409 13.076 execution/alu/MEM_ALU_result[31]_i_16_n_0 - SLICE_X4Y39 LUT6 (Prop_lut6_I2_O) 0.124 13.200 r execution/alu/MEM_ALU_result[31]_i_5/O - net (fo=1, routed) 0.403 13.603 execution/alu/MEM_ALU_result[31]_i_5_n_0 - SLICE_X5Y40 LUT6 (Prop_lut6_I3_O) 0.124 13.727 r execution/alu/MEM_ALU_result[31]_i_1/O - net (fo=1, routed) 0.000 13.727 memory_access/prev_ALU_result[31] - SLICE_X5Y40 FDRE r memory_access/MEM_ALU_result_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 20.000 20.000 r - R4 0.000 20.000 r hardware_clk (IN) - net (fo=0) 0.000 20.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.515 18.044 memory_access/clk_out1 - SLICE_X5Y40 FDRE r memory_access/MEM_ALU_result_reg[31]/C - clock pessimism -0.505 17.539 - clock uncertainty -0.108 17.431 - SLICE_X5Y40 FDRE (Setup_fdre_C_D) 0.032 17.463 memory_access/MEM_ALU_result_reg[31] - ------------------------------------------------------------------- - required time 17.463 - arrival time -13.727 - ------------------------------------------------------------------- - slack 3.737 - -Slack (MET) : 3.792ns (required time - arrival time) - Source: write_back/WB_WB_source_reg/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[27]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.142ns (logic 8.308ns (51.469%) route 7.834ns (48.531%)) - Logic Levels: 11 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=2 LUT6=3) - Clock Path Skew: -0.036ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.952ns = ( 18.048 - 20.000 ) - Source Clock Delay (SCD): -2.421ns - Clock Pessimism Removal (CPR): -0.505ns - Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 - SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q - net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source - SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O - net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] - SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O - net (fo=2, routed) 0.560 2.844 execution/result0__0_4 - SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O - net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] - DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) - 4.240 8.261 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 - DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.781 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 - SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 - SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.363 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.363 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X11Y37 CARRY4 (Prop_carry4_CI_O[3]) - 0.313 11.676 r execution/alu/result0_inferred__11/i__carry__1/O[3] - net (fo=1, routed) 1.057 12.733 execution/alu/result0_inferred__11/i__carry__1_n_4 - SLICE_X2Y40 LUT6 (Prop_lut6_I3_O) 0.306 13.039 r execution/alu/MEM_ALU_result[27]_i_4/O - net (fo=1, routed) 0.557 13.596 execution/alu/MEM_ALU_result[27]_i_4_n_0 - SLICE_X2Y43 LUT6 (Prop_lut6_I3_O) 0.124 13.720 r execution/alu/MEM_ALU_result[27]_i_1/O - net (fo=1, routed) 0.000 13.720 memory_access/prev_ALU_result[27] - SLICE_X2Y43 FDRE r memory_access/MEM_ALU_result_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 20.000 20.000 r - R4 0.000 20.000 r hardware_clk (IN) - net (fo=0) 0.000 20.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.519 18.048 memory_access/clk_out1 - SLICE_X2Y43 FDRE r memory_access/MEM_ALU_result_reg[27]/C - clock pessimism -0.505 17.543 - clock uncertainty -0.108 17.435 - SLICE_X2Y43 FDRE (Setup_fdre_C_D) 0.077 17.512 memory_access/MEM_ALU_result_reg[27] - ------------------------------------------------------------------- - required time 17.512 - arrival time -13.720 - ------------------------------------------------------------------- - slack 3.792 - -Slack (MET) : 3.795ns (required time - arrival time) - Source: write_back/WB_WB_source_reg/C +Slack (MET) : 3.883ns (required time - arrival time) + Source: write_back/WB_register_write_destination_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[21]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.135ns (logic 8.336ns (51.663%) route 7.799ns (48.337%)) - Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) - Clock Path Skew: -0.039ns (DCD - SCD + CPR) + Data Path Delay: 15.980ns (logic 8.301ns (51.947%) route 7.679ns (48.053%)) + Logic Levels: 12 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT6=4) + Clock Path Skew: -0.107ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.955ns = ( 18.045 - 20.000 ) - Source Clock Delay (SCD): -2.421ns + Source Clock Delay (SCD): -2.353ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -823,37 +652,39 @@ Slack (MET) : 3.795ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 - SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C + net (fo=18132, routed) 1.623 -2.353 write_back/clk_out1 + SLICE_X5Y53 FDRE r write_back/WB_register_write_destination_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q - net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source - SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O - net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] - SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O - net (fo=2, routed) 0.560 2.844 execution/result0__0_4 - SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O - net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] - DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) - 4.240 8.261 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + SLICE_X5Y53 FDRE (Prop_fdre_C_Q) 0.456 -1.897 r write_back/WB_register_write_destination_reg[2]/Q + net (fo=26, routed) 1.478 -0.419 write_back/Q[2] + SLICE_X3Y54 LUT4 (Prop_lut4_I0_O) 0.152 -0.267 r write_back/result0_i_55/O + net (fo=1, routed) 0.640 0.373 write_back/result0_i_55_n_0 + SLICE_X3Y53 LUT6 (Prop_lut6_I2_O) 0.332 0.705 r write_back/result0_i_34/O + net (fo=34, routed) 1.251 1.956 memory_access/result0__0_0 + SLICE_X15Y45 LUT6 (Prop_lut6_I4_O) 0.124 2.080 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.654 2.734 execution/result0__0_3 + SLICE_X12Y45 LUT3 (Prop_lut3_I2_O) 0.124 2.858 r execution/result0__0_i_16/O + net (fo=141, routed) 1.215 4.073 execution/alu/ALU_in1[1] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.109 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.111 execution/alu/result0__0_n_106 DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.781 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 - SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + 1.518 9.629 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.423 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.547 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.547 execution/alu/i__carry_i_3__0_n_0 SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + 0.550 11.097 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.097 execution/alu/result0_inferred__11/i__carry_n_0 SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 11.583 r execution/alu/result0_inferred__11/i__carry__0/O[1] - net (fo=1, routed) 0.691 12.274 execution/alu/result0_inferred__11/i__carry__0_n_6 - SLICE_X3Y37 LUT4 (Prop_lut4_I1_O) 0.303 12.577 r execution/alu/MEM_ALU_result[21]_i_12/O - net (fo=1, routed) 0.433 13.010 execution/alu/MEM_ALU_result[21]_i_12_n_0 - SLICE_X0Y38 LUT6 (Prop_lut6_I5_O) 0.124 13.134 r execution/alu/MEM_ALU_result[21]_i_4/O - net (fo=1, routed) 0.456 13.590 execution/alu/MEM_ALU_result[21]_i_4_n_0 - SLICE_X2Y38 LUT6 (Prop_lut6_I3_O) 0.124 13.714 r execution/alu/MEM_ALU_result[21]_i_1/O - net (fo=1, routed) 0.000 13.714 memory_access/prev_ALU_result[21] + 0.334 11.431 r execution/alu/result0_inferred__11/i__carry__0/O[1] + net (fo=1, routed) 0.691 12.122 execution/alu/result0_inferred__11/i__carry__0_n_6 + SLICE_X3Y37 LUT4 (Prop_lut4_I1_O) 0.303 12.425 r execution/alu/MEM_ALU_result[21]_i_12/O + net (fo=1, routed) 0.498 12.923 execution/alu/MEM_ALU_result[21]_i_12_n_0 + SLICE_X0Y38 LUT6 (Prop_lut6_I5_O) 0.124 13.047 r execution/alu/MEM_ALU_result[21]_i_4/O + net (fo=1, routed) 0.456 13.503 execution/alu/MEM_ALU_result[21]_i_4_n_0 + SLICE_X2Y38 LUT6 (Prop_lut6_I3_O) 0.124 13.627 r execution/alu/MEM_ALU_result[21]_i_1/O + net (fo=1, routed) 0.000 13.627 memory_access/prev_ALU_result[21] SLICE_X2Y38 FDRE r memory_access/MEM_ALU_result_reg[21]/D ------------------------------------------------------------------- ------------------- @@ -874,23 +705,23 @@ Slack (MET) : 3.795ns (required time - arrival time) SLICE_X2Y38 FDRE (Setup_fdre_C_D) 0.077 17.509 memory_access/MEM_ALU_result_reg[21] ------------------------------------------------------------------- required time 17.509 - arrival time -13.714 + arrival time -13.627 ------------------------------------------------------------------- - slack 3.795 + slack 3.883 -Slack (MET) : 3.828ns (required time - arrival time) - Source: write_back/WB_WB_source_reg/C +Slack (MET) : 3.889ns (required time - arrival time) + Source: write_back/WB_register_write_destination_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[28]/D + Destination: memory_access/MEM_ALU_result_reg[31]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.055ns (logic 8.448ns (52.618%) route 7.607ns (47.382%)) - Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=2) - Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Data Path Delay: 15.928ns (logic 8.511ns (53.435%) route 7.417ns (46.565%)) + Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4) + Clock Path Skew: -0.108ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.956ns = ( 18.044 - 20.000 ) - Source Clock Delay (SCD): -2.421ns + Source Clock Delay (SCD): -2.353ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -909,43 +740,139 @@ Slack (MET) : 3.828ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 - SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C + net (fo=18132, routed) 1.623 -2.353 write_back/clk_out1 + SLICE_X5Y53 FDRE r write_back/WB_register_write_destination_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q - net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source - SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O - net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] - SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O - net (fo=2, routed) 0.560 2.844 execution/result0__0_4 - SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O - net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] - DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) - 4.240 8.261 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + SLICE_X5Y53 FDRE (Prop_fdre_C_Q) 0.456 -1.897 r write_back/WB_register_write_destination_reg[2]/Q + net (fo=26, routed) 1.478 -0.419 write_back/Q[2] + SLICE_X3Y54 LUT4 (Prop_lut4_I0_O) 0.152 -0.267 r write_back/result0_i_55/O + net (fo=1, routed) 0.640 0.373 write_back/result0_i_55_n_0 + SLICE_X3Y53 LUT6 (Prop_lut6_I2_O) 0.332 0.705 r write_back/result0_i_34/O + net (fo=34, routed) 1.251 1.956 memory_access/result0__0_0 + SLICE_X15Y45 LUT6 (Prop_lut6_I4_O) 0.124 2.080 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.654 2.734 execution/result0__0_3 + SLICE_X12Y45 LUT3 (Prop_lut3_I2_O) 0.124 2.858 r execution/result0__0_i_16/O + net (fo=141, routed) 1.215 4.073 execution/alu/ALU_in1[1] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.109 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.111 execution/alu/result0__0_n_106 DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.781 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 - SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + 1.518 9.629 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.423 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.547 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.547 execution/alu/i__carry_i_3__0_n_0 SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + 0.550 11.097 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.097 execution/alu/result0_inferred__11/i__carry_n_0 SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.363 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.363 execution/alu/result0_inferred__11/i__carry__0_n_0 + 0.114 11.211 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.211 execution/alu/result0_inferred__11/i__carry__0_n_0 SLICE_X11Y37 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 11.477 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.477 execution/alu/result0_inferred__11/i__carry__1_n_0 + 0.114 11.325 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.325 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X11Y38 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 11.638 r execution/alu/result0_inferred__11/i__carry__2/O[3] + net (fo=1, routed) 0.570 12.209 execution/alu/result0_inferred__11/i__carry__2_n_4 + SLICE_X6Y39 LUT5 (Prop_lut5_I0_O) 0.306 12.515 r execution/alu/MEM_ALU_result[31]_i_16/O + net (fo=1, routed) 0.409 12.924 execution/alu/MEM_ALU_result[31]_i_16_n_0 + SLICE_X4Y39 LUT6 (Prop_lut6_I2_O) 0.124 13.048 r execution/alu/MEM_ALU_result[31]_i_5/O + net (fo=1, routed) 0.403 13.451 execution/alu/MEM_ALU_result[31]_i_5_n_0 + SLICE_X5Y40 LUT6 (Prop_lut6_I3_O) 0.124 13.575 r execution/alu/MEM_ALU_result[31]_i_1/O + net (fo=1, routed) 0.000 13.575 memory_access/prev_ALU_result[31] + SLICE_X5Y40 FDRE r memory_access/MEM_ALU_result_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 20.000 20.000 r + R4 0.000 20.000 r hardware_clk (IN) + net (fo=0) 0.000 20.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.515 18.044 memory_access/clk_out1 + SLICE_X5Y40 FDRE r memory_access/MEM_ALU_result_reg[31]/C + clock pessimism -0.505 17.539 + clock uncertainty -0.108 17.431 + SLICE_X5Y40 FDRE (Setup_fdre_C_D) 0.032 17.463 memory_access/MEM_ALU_result_reg[31] + ------------------------------------------------------------------- + required time 17.463 + arrival time -13.575 + ------------------------------------------------------------------- + slack 3.889 + +Slack (MET) : 3.980ns (required time - arrival time) + Source: write_back/WB_register_write_destination_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: memory_access/MEM_ALU_result_reg[28]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 15.835ns (logic 8.413ns (53.128%) route 7.422ns (46.872%)) + Logic Levels: 14 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT5=1 LUT6=3) + Clock Path Skew: -0.108ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.956ns = ( 18.044 - 20.000 ) + Source Clock Delay (SCD): -2.353ns + Clock Pessimism Removal (CPR): -0.505ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.623 -2.353 write_back/clk_out1 + SLICE_X5Y53 FDRE r write_back/WB_register_write_destination_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y53 FDRE (Prop_fdre_C_Q) 0.456 -1.897 r write_back/WB_register_write_destination_reg[2]/Q + net (fo=26, routed) 1.478 -0.419 write_back/Q[2] + SLICE_X3Y54 LUT4 (Prop_lut4_I0_O) 0.152 -0.267 r write_back/result0_i_55/O + net (fo=1, routed) 0.640 0.373 write_back/result0_i_55_n_0 + SLICE_X3Y53 LUT6 (Prop_lut6_I2_O) 0.332 0.705 r write_back/result0_i_34/O + net (fo=34, routed) 1.251 1.956 memory_access/result0__0_0 + SLICE_X15Y45 LUT6 (Prop_lut6_I4_O) 0.124 2.080 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.654 2.734 execution/result0__0_3 + SLICE_X12Y45 LUT3 (Prop_lut3_I2_O) 0.124 2.858 r execution/result0__0_i_16/O + net (fo=141, routed) 1.215 4.073 execution/alu/ALU_in1[1] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.109 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.111 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.629 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.423 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.547 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.547 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.097 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.097 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.211 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.211 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y37 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.325 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.325 execution/alu/result0_inferred__11/i__carry__1_n_0 SLICE_X11Y38 CARRY4 (Prop_carry4_CI_O[0]) - 0.222 11.699 r execution/alu/result0_inferred__11/i__carry__2/O[0] - net (fo=1, routed) 0.661 12.360 execution/alu/result0_inferred__11/i__carry__2_n_7 - SLICE_X7Y39 LUT4 (Prop_lut4_I3_O) 0.299 12.659 r execution/alu/MEM_ALU_result[28]_i_12/O - net (fo=1, routed) 0.436 13.095 execution/alu/MEM_ALU_result[28]_i_12_n_0 - SLICE_X4Y40 LUT5 (Prop_lut5_I4_O) 0.124 13.219 r execution/alu/MEM_ALU_result[28]_i_4/O - net (fo=1, routed) 0.291 13.510 execution/alu/MEM_ALU_result[28]_i_4_n_0 - SLICE_X5Y40 LUT6 (Prop_lut6_I3_O) 0.124 13.634 r execution/alu/MEM_ALU_result[28]_i_1/O - net (fo=1, routed) 0.000 13.634 memory_access/prev_ALU_result[28] + 0.222 11.547 r execution/alu/result0_inferred__11/i__carry__2/O[0] + net (fo=1, routed) 0.661 12.208 execution/alu/result0_inferred__11/i__carry__2_n_7 + SLICE_X7Y39 LUT4 (Prop_lut4_I3_O) 0.299 12.507 r execution/alu/MEM_ALU_result[28]_i_12/O + net (fo=1, routed) 0.436 12.943 execution/alu/MEM_ALU_result[28]_i_12_n_0 + SLICE_X4Y40 LUT5 (Prop_lut5_I4_O) 0.124 13.067 r execution/alu/MEM_ALU_result[28]_i_4/O + net (fo=1, routed) 0.291 13.358 execution/alu/MEM_ALU_result[28]_i_4_n_0 + SLICE_X5Y40 LUT6 (Prop_lut6_I3_O) 0.124 13.482 r execution/alu/MEM_ALU_result[28]_i_1/O + net (fo=1, routed) 0.000 13.482 memory_access/prev_ALU_result[28] SLICE_X5Y40 FDRE r memory_access/MEM_ALU_result_reg[28]/D ------------------------------------------------------------------- ------------------- @@ -966,23 +893,23 @@ Slack (MET) : 3.828ns (required time - arrival time) SLICE_X5Y40 FDRE (Setup_fdre_C_D) 0.031 17.462 memory_access/MEM_ALU_result_reg[28] ------------------------------------------------------------------- required time 17.462 - arrival time -13.634 + arrival time -13.482 ------------------------------------------------------------------- - slack 3.828 + slack 3.980 -Slack (MET) : 3.929ns (required time - arrival time) - Source: write_back/WB_WB_source_reg/C +Slack (MET) : 4.081ns (required time - arrival time) + Source: write_back/WB_register_write_destination_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[20]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 15.952ns (logic 8.220ns (51.530%) route 7.732ns (48.470%)) - Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) - Clock Path Skew: -0.043ns (DCD - SCD + CPR) + Data Path Delay: 15.732ns (logic 8.185ns (52.028%) route 7.547ns (47.972%)) + Logic Levels: 12 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT6=4) + Clock Path Skew: -0.111ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.959ns = ( 18.041 - 20.000 ) - Source Clock Delay (SCD): -2.421ns + Source Clock Delay (SCD): -2.353ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -1001,37 +928,39 @@ Slack (MET) : 3.929ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 - SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C + net (fo=18132, routed) 1.623 -2.353 write_back/clk_out1 + SLICE_X5Y53 FDRE r write_back/WB_register_write_destination_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q - net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source - SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O - net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] - SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O - net (fo=2, routed) 0.560 2.844 execution/result0__0_4 - SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O - net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] - DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) - 4.240 8.261 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + SLICE_X5Y53 FDRE (Prop_fdre_C_Q) 0.456 -1.897 r write_back/WB_register_write_destination_reg[2]/Q + net (fo=26, routed) 1.478 -0.419 write_back/Q[2] + SLICE_X3Y54 LUT4 (Prop_lut4_I0_O) 0.152 -0.267 r write_back/result0_i_55/O + net (fo=1, routed) 0.640 0.373 write_back/result0_i_55_n_0 + SLICE_X3Y53 LUT6 (Prop_lut6_I2_O) 0.332 0.705 r write_back/result0_i_34/O + net (fo=34, routed) 1.251 1.956 memory_access/result0__0_0 + SLICE_X15Y45 LUT6 (Prop_lut6_I4_O) 0.124 2.080 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.654 2.734 execution/result0__0_3 + SLICE_X12Y45 LUT3 (Prop_lut3_I2_O) 0.124 2.858 r execution/result0__0_i_16/O + net (fo=141, routed) 1.215 4.073 execution/alu/ALU_in1[1] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.109 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.111 execution/alu/result0__0_n_106 DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.781 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 - SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + 1.518 9.629 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.423 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.547 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.547 execution/alu/i__carry_i_3__0_n_0 SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + 0.550 11.097 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.097 execution/alu/result0_inferred__11/i__carry_n_0 SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[0]) - 0.222 11.471 r execution/alu/result0_inferred__11/i__carry__0/O[0] - net (fo=1, routed) 0.653 12.124 execution/alu/result0_inferred__11/i__carry__0_n_7 - SLICE_X5Y36 LUT4 (Prop_lut4_I3_O) 0.299 12.423 r execution/alu/MEM_ALU_result[20]_i_12/O - net (fo=1, routed) 0.567 12.990 execution/alu/MEM_ALU_result[20]_i_12_n_0 - SLICE_X3Y34 LUT6 (Prop_lut6_I5_O) 0.124 13.114 r execution/alu/MEM_ALU_result[20]_i_4/O - net (fo=1, routed) 0.292 13.407 execution/alu/MEM_ALU_result[20]_i_4_n_0 - SLICE_X3Y33 LUT6 (Prop_lut6_I3_O) 0.124 13.531 r execution/alu/MEM_ALU_result[20]_i_1/O - net (fo=1, routed) 0.000 13.531 memory_access/prev_ALU_result[20] + 0.222 11.319 r execution/alu/result0_inferred__11/i__carry__0/O[0] + net (fo=1, routed) 0.653 11.972 execution/alu/result0_inferred__11/i__carry__0_n_7 + SLICE_X5Y36 LUT4 (Prop_lut4_I3_O) 0.299 12.271 r execution/alu/MEM_ALU_result[20]_i_12/O + net (fo=1, routed) 0.567 12.838 execution/alu/MEM_ALU_result[20]_i_12_n_0 + SLICE_X3Y34 LUT6 (Prop_lut6_I5_O) 0.124 12.962 r execution/alu/MEM_ALU_result[20]_i_4/O + net (fo=1, routed) 0.292 13.254 execution/alu/MEM_ALU_result[20]_i_4_n_0 + SLICE_X3Y33 LUT6 (Prop_lut6_I3_O) 0.124 13.378 r execution/alu/MEM_ALU_result[20]_i_1/O + net (fo=1, routed) 0.000 13.378 memory_access/prev_ALU_result[20] SLICE_X3Y33 FDRE r memory_access/MEM_ALU_result_reg[20]/D ------------------------------------------------------------------- ------------------- @@ -1052,23 +981,23 @@ Slack (MET) : 3.929ns (required time - arrival time) SLICE_X3Y33 FDRE (Setup_fdre_C_D) 0.031 17.459 memory_access/MEM_ALU_result_reg[20] ------------------------------------------------------------------- required time 17.459 - arrival time -13.531 + arrival time -13.378 ------------------------------------------------------------------- - slack 3.929 + slack 4.081 -Slack (MET) : 3.938ns (required time - arrival time) - Source: write_back/WB_WB_source_reg/C +Slack (MET) : 4.090ns (required time - arrival time) + Source: write_back/WB_register_write_destination_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[22]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 15.943ns (logic 8.240ns (51.684%) route 7.703ns (48.316%)) - Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) - Clock Path Skew: -0.041ns (DCD - SCD + CPR) + Data Path Delay: 15.723ns (logic 8.205ns (52.185%) route 7.518ns (47.815%)) + Logic Levels: 12 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=1 LUT4=2 LUT6=4) + Clock Path Skew: -0.109ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.957ns = ( 18.043 - 20.000 ) - Source Clock Delay (SCD): -2.421ns + Source Clock Delay (SCD): -2.353ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -1087,37 +1016,39 @@ Slack (MET) : 3.938ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 - SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C + net (fo=18132, routed) 1.623 -2.353 write_back/clk_out1 + SLICE_X5Y53 FDRE r write_back/WB_register_write_destination_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q - net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source - SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O - net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] - SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O - net (fo=2, routed) 0.560 2.844 execution/result0__0_4 - SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O - net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] - DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) - 4.240 8.261 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + SLICE_X5Y53 FDRE (Prop_fdre_C_Q) 0.456 -1.897 r write_back/WB_register_write_destination_reg[2]/Q + net (fo=26, routed) 1.478 -0.419 write_back/Q[2] + SLICE_X3Y54 LUT4 (Prop_lut4_I0_O) 0.152 -0.267 r write_back/result0_i_55/O + net (fo=1, routed) 0.640 0.373 write_back/result0_i_55_n_0 + SLICE_X3Y53 LUT6 (Prop_lut6_I2_O) 0.332 0.705 r write_back/result0_i_34/O + net (fo=34, routed) 1.251 1.956 memory_access/result0__0_0 + SLICE_X15Y45 LUT6 (Prop_lut6_I4_O) 0.124 2.080 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.654 2.734 execution/result0__0_3 + SLICE_X12Y45 LUT3 (Prop_lut3_I2_O) 0.124 2.858 r execution/result0__0_i_16/O + net (fo=141, routed) 1.215 4.073 execution/alu/ALU_in1[1] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.109 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.111 execution/alu/result0__0_n_106 DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 9.781 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 - SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + 1.518 9.629 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.423 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.547 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.547 execution/alu/i__carry_i_3__0_n_0 SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + 0.550 11.097 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.097 execution/alu/result0_inferred__11/i__carry_n_0 SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[2]) - 0.239 11.488 r execution/alu/result0_inferred__11/i__carry__0/O[2] - net (fo=1, routed) 0.709 12.197 execution/alu/result0_inferred__11/i__carry__0_n_5 - SLICE_X2Y36 LUT4 (Prop_lut4_I3_O) 0.302 12.499 r execution/alu/MEM_ALU_result[22]_i_12/O - net (fo=1, routed) 0.291 12.790 execution/alu/MEM_ALU_result[22]_i_12_n_0 - SLICE_X0Y36 LUT6 (Prop_lut6_I5_O) 0.124 12.914 r execution/alu/MEM_ALU_result[22]_i_4/O - net (fo=1, routed) 0.484 13.398 execution/alu/MEM_ALU_result[22]_i_4_n_0 - SLICE_X1Y36 LUT6 (Prop_lut6_I3_O) 0.124 13.522 r execution/alu/MEM_ALU_result[22]_i_1/O - net (fo=1, routed) 0.000 13.522 memory_access/prev_ALU_result[22] + 0.239 11.336 r execution/alu/result0_inferred__11/i__carry__0/O[2] + net (fo=1, routed) 0.709 12.045 execution/alu/result0_inferred__11/i__carry__0_n_5 + SLICE_X2Y36 LUT4 (Prop_lut4_I3_O) 0.302 12.347 r execution/alu/MEM_ALU_result[22]_i_12/O + net (fo=1, routed) 0.291 12.638 execution/alu/MEM_ALU_result[22]_i_12_n_0 + SLICE_X0Y36 LUT6 (Prop_lut6_I5_O) 0.124 12.762 r execution/alu/MEM_ALU_result[22]_i_4/O + net (fo=1, routed) 0.484 13.246 execution/alu/MEM_ALU_result[22]_i_4_n_0 + SLICE_X1Y36 LUT6 (Prop_lut6_I3_O) 0.124 13.370 r execution/alu/MEM_ALU_result[22]_i_1/O + net (fo=1, routed) 0.000 13.370 memory_access/prev_ALU_result[22] SLICE_X1Y36 FDRE r memory_access/MEM_ALU_result_reg[22]/D ------------------------------------------------------------------- ------------------- @@ -1138,9 +1069,98 @@ Slack (MET) : 3.938ns (required time - arrival time) SLICE_X1Y36 FDRE (Setup_fdre_C_D) 0.029 17.459 memory_access/MEM_ALU_result_reg[22] ------------------------------------------------------------------- required time 17.459 - arrival time -13.522 + arrival time -13.370 ------------------------------------------------------------------- - slack 3.938 + slack 4.090 + +Slack (MET) : 4.121ns (required time - arrival time) + Source: write_back/WB_register_write_destination_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: memory_access/MEM_ALU_result_reg[27]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 15.745ns (logic 8.273ns (52.545%) route 7.472ns (47.455%)) + Logic Levels: 12 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT6=4) + Clock Path Skew: -0.104ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.952ns = ( 18.048 - 20.000 ) + Source Clock Delay (SCD): -2.353ns + Clock Pessimism Removal (CPR): -0.505ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.623 -2.353 write_back/clk_out1 + SLICE_X5Y53 FDRE r write_back/WB_register_write_destination_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y53 FDRE (Prop_fdre_C_Q) 0.456 -1.897 r write_back/WB_register_write_destination_reg[2]/Q + net (fo=26, routed) 1.478 -0.419 write_back/Q[2] + SLICE_X3Y54 LUT4 (Prop_lut4_I0_O) 0.152 -0.267 r write_back/result0_i_55/O + net (fo=1, routed) 0.640 0.373 write_back/result0_i_55_n_0 + SLICE_X3Y53 LUT6 (Prop_lut6_I2_O) 0.332 0.705 r write_back/result0_i_34/O + net (fo=34, routed) 1.251 1.956 memory_access/result0__0_0 + SLICE_X15Y45 LUT6 (Prop_lut6_I4_O) 0.124 2.080 f memory_access/result0__0_i_22/O + net (fo=2, routed) 0.654 2.734 execution/result0__0_3 + SLICE_X12Y45 LUT3 (Prop_lut3_I2_O) 0.124 2.858 r execution/result0__0_i_16/O + net (fo=141, routed) 1.215 4.073 execution/alu/ALU_in1[1] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) + 4.036 8.109 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.111 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.629 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.423 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.547 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.547 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.097 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.097 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.211 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.211 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y37 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 11.524 r execution/alu/result0_inferred__11/i__carry__1/O[3] + net (fo=1, routed) 0.880 12.404 execution/alu/result0_inferred__11/i__carry__1_n_4 + SLICE_X2Y40 LUT6 (Prop_lut6_I3_O) 0.306 12.710 r execution/alu/MEM_ALU_result[27]_i_4/O + net (fo=1, routed) 0.557 13.267 execution/alu/MEM_ALU_result[27]_i_4_n_0 + SLICE_X2Y43 LUT6 (Prop_lut6_I3_O) 0.124 13.391 r execution/alu/MEM_ALU_result[27]_i_1/O + net (fo=1, routed) 0.000 13.391 memory_access/prev_ALU_result[27] + SLICE_X2Y43 FDRE r memory_access/MEM_ALU_result_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 20.000 20.000 r + R4 0.000 20.000 r hardware_clk (IN) + net (fo=0) 0.000 20.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.519 18.048 memory_access/clk_out1 + SLICE_X2Y43 FDRE r memory_access/MEM_ALU_result_reg[27]/C + clock pessimism -0.505 17.543 + clock uncertainty -0.108 17.435 + SLICE_X2Y43 FDRE (Setup_fdre_C_D) 0.077 17.512 memory_access/MEM_ALU_result_reg[27] + ------------------------------------------------------------------- + required time 17.512 + arrival time -13.391 + ------------------------------------------------------------------- + slack 4.121 @@ -1203,61 +1223,6 @@ Slack (MET) : 0.055ns (arrival time - required time) ------------------------------------------------------------------- slack 0.055 -Slack (MET) : 0.056ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[30]_rep__4/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435544][30]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.397ns (logic 0.141ns (35.524%) route 0.256ns (64.476%)) - Logic Levels: 0 - Clock Path Skew: 0.271ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.293ns - Source Clock Delay (SCD): -0.525ns - Clock Pessimism Removal (CPR): -0.039ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.562 -0.525 memory_access/clk_out1 - SLICE_X32Y52 FDRE r memory_access/MEM_memory_write_data_reg[30]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y52 FDRE (Prop_fdre_C_Q) 0.141 -0.384 r memory_access/MEM_memory_write_data_reg[30]_rep__4/Q - net (fo=64, routed) 0.256 -0.128 data_memory/memory_data_reg[268435521][31]_0[30] - SLICE_X32Y49 FDRE r data_memory/memory_data_reg[268435544][30]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.833 -0.293 data_memory/clk_out1 - SLICE_X32Y49 FDRE r data_memory/memory_data_reg[268435544][30]/C - clock pessimism 0.039 -0.254 - SLICE_X32Y49 FDRE (Hold_fdre_C_D) 0.070 -0.184 data_memory/memory_data_reg[268435544][30] - ------------------------------------------------------------------- - required time 0.184 - arrival time -0.128 - ------------------------------------------------------------------- - slack 0.056 - Slack (MET) : 0.058ns (arrival time - required time) Source: memory_access/MEM_memory_write_data_reg[10]_rep__5/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -1313,6 +1278,61 @@ Slack (MET) : 0.058ns (arrival time - required time) ------------------------------------------------------------------- slack 0.058 +Slack (MET) : 0.061ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[30]_rep__4/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435544][30]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.401ns (logic 0.141ns (35.126%) route 0.260ns (64.874%)) + Logic Levels: 0 + Clock Path Skew: 0.271ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.293ns + Source Clock Delay (SCD): -0.525ns + Clock Pessimism Removal (CPR): -0.039ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.562 -0.525 memory_access/clk_out1 + SLICE_X32Y52 FDRE r memory_access/MEM_memory_write_data_reg[30]_rep__4/C + ------------------------------------------------------------------- ------------------- + SLICE_X32Y52 FDRE (Prop_fdre_C_Q) 0.141 -0.384 r memory_access/MEM_memory_write_data_reg[30]_rep__4/Q + net (fo=64, routed) 0.260 -0.124 data_memory/memory_data_reg[268435521][31]_0[30] + SLICE_X32Y49 FDRE r data_memory/memory_data_reg[268435544][30]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.833 -0.293 data_memory/clk_out1 + SLICE_X32Y49 FDRE r data_memory/memory_data_reg[268435544][30]/C + clock pessimism 0.039 -0.254 + SLICE_X32Y49 FDRE (Hold_fdre_C_D) 0.070 -0.184 data_memory/memory_data_reg[268435544][30] + ------------------------------------------------------------------- + required time 0.184 + arrival time -0.124 + ------------------------------------------------------------------- + slack 0.061 + Slack (MET) : 0.068ns (arrival time - required time) Source: memory_access/MEM_memory_write_data_reg[10]_rep__5/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -1588,64 +1608,6 @@ Slack (MET) : 0.082ns (arrival time - required time) ------------------------------------------------------------------- slack 0.082 -Slack (MET) : 0.088ns (arrival time - required time) - Source: instruction_fetch/PC_reg[26]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: instruction_decode/IFID_PC_plus_4_reg[26]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.458ns (logic 0.274ns (59.790%) route 0.184ns (40.210%)) - Logic Levels: 1 (CARRY4=1) - Clock Path Skew: 0.268ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.291ns - Source Clock Delay (SCD): -0.520ns - Clock Pessimism Removal (CPR): -0.039ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.567 -0.520 instruction_fetch/clk_out1 - SLICE_X8Y49 FDRE r instruction_fetch/PC_reg[26]/C - ------------------------------------------------------------------- ------------------- - SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.356 r instruction_fetch/PC_reg[26]/Q - net (fo=2, routed) 0.184 -0.172 instruction_fetch/PC[26] - SLICE_X9Y50 CARRY4 (Prop_carry4_S[1]_O[1]) - 0.110 -0.062 r instruction_fetch/adder_out_carry__5/O[1] - net (fo=2, routed) 0.000 -0.062 instruction_decode/D[26] - SLICE_X9Y50 FDRE r instruction_decode/IFID_PC_plus_4_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.834 -0.291 instruction_decode/clk_out1 - SLICE_X9Y50 FDRE r instruction_decode/IFID_PC_plus_4_reg[26]/C - clock pessimism 0.039 -0.252 - SLICE_X9Y50 FDRE (Hold_fdre_C_D) 0.102 -0.150 instruction_decode/IFID_PC_plus_4_reg[26] - ------------------------------------------------------------------- - required time 0.150 - arrival time -0.062 - ------------------------------------------------------------------- - slack 0.088 - Slack (MET) : 0.089ns (arrival time - required time) Source: memory_access/MEM_memory_write_data_reg[9]_rep__1/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -1701,6 +1663,61 @@ Slack (MET) : 0.089ns (arrival time - required time) ------------------------------------------------------------------- slack 0.089 +Slack (MET) : 0.092ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435927][3]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.514ns (logic 0.141ns (27.427%) route 0.373ns (72.573%)) + Logic Levels: 0 + Clock Path Skew: 0.352ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.206ns + Source Clock Delay (SCD): -0.524ns + Clock Pessimism Removal (CPR): -0.034ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.563 -0.524 memory_access/clk_out1 + SLICE_X11Y90 FDRE r memory_access/MEM_memory_write_data_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y90 FDRE (Prop_fdre_C_Q) 0.141 -0.383 r memory_access/MEM_memory_write_data_reg[3]/Q + net (fo=64, routed) 0.373 -0.010 data_memory/memory_data_reg[268435905][31]_0[3] + SLICE_X9Y107 FDRE r data_memory/memory_data_reg[268435927][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.920 -0.206 data_memory/clk_out1 + SLICE_X9Y107 FDRE r data_memory/memory_data_reg[268435927][3]/C + clock pessimism 0.034 -0.172 + SLICE_X9Y107 FDRE (Hold_fdre_C_D) 0.070 -0.102 data_memory/memory_data_reg[268435927][3] + ------------------------------------------------------------------- + required time 0.102 + arrival time -0.010 + ------------------------------------------------------------------- + slack 0.092 + @@ -3362,8 +3379,8 @@ Slack: inf Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435520][4]/S - (rising edge-triggered cell FDSE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435520][4]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.167ns (logic 0.045ns (3.857%) route 1.122ns (96.143%)) @@ -3379,7 +3396,7 @@ Slack: inf net (fo=2, routed) 0.394 0.394 data_memory/locked SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O net (fo=17907, routed) 0.728 1.167 data_memory/reset - SLICE_X60Y46 FDSE r data_memory/memory_data_reg[268435520][4]/S + SLICE_X60Y46 FDRE r data_memory/memory_data_reg[268435520][4]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3393,7 +3410,7 @@ Slack: inf net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O net (fo=18132, routed) 0.864 -0.262 data_memory/clk_out1 - SLICE_X60Y46 FDSE r data_memory/memory_data_reg[268435520][4]/C + SLICE_X60Y46 FDRE r data_memory/memory_data_reg[268435520][4]/C diff --git a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt index 0f3fec7..6775cde 100644 --- a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 23:40:17 2024 +| Date : Mon Jul 15 21:30:56 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb | Design : CPU @@ -58,8 +58,8 @@ Table of Contents | 0 | Yes | - | - | | 0 | Yes | - | Set | | 0 | Yes | - | Reset | -| 368 | Yes | Set | - | -| 17764 | Yes | Reset | - | +| 152 | Yes | Set | - | +| 17980 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -180,15 +180,15 @@ Table of Contents +-----------+-------+---------------------+ | Ref Name | Used | Functional Category | +-----------+-------+---------------------+ -| FDRE | 17764 | Flop & Latch | +| FDRE | 17980 | Flop & Latch | | LUT6 | 7154 | LUT | | MUXF7 | 2377 | MuxFx | | MUXF8 | 1088 | MuxFx | | LUT5 | 825 | LUT | -| FDSE | 368 | Flop & Latch | | LUT4 | 281 | LUT | | LUT3 | 230 | LUT | | LUT2 | 154 | LUT | +| FDSE | 152 | Flop & Latch | | CARRY4 | 39 | CarryLogic | | OBUF | 13 | IO | | DSP48E1 | 3 | Block Arithmetic | diff --git a/PipelineProcessor.runs/impl_1/clockInfo.txt b/PipelineProcessor.runs/impl_1/clockInfo.txt index 7332a57..2a8d10b 100644 --- a/PipelineProcessor.runs/impl_1/clockInfo.txt +++ b/PipelineProcessor.runs/impl_1/clockInfo.txt @@ -1,6 +1,6 @@ ------------------------------------- | Tool Version : Vivado v.2023.2 -| Date : Sat Jul 13 23:39:48 2024 +| Date : Mon Jul 15 21:30:29 2024 | Host : Viviana | Design : design_1 | Device : xc7a35t-fgg484-1-- diff --git a/PipelineProcessor.runs/impl_1/init_design.pb b/PipelineProcessor.runs/impl_1/init_design.pb index 6d9f538..f9dcc34 100644 Binary files a/PipelineProcessor.runs/impl_1/init_design.pb and b/PipelineProcessor.runs/impl_1/init_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/opt_design.pb b/PipelineProcessor.runs/impl_1/opt_design.pb index 0f94a63..28c618c 100644 Binary files a/PipelineProcessor.runs/impl_1/opt_design.pb and b/PipelineProcessor.runs/impl_1/opt_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/phys_opt_design.pb b/PipelineProcessor.runs/impl_1/phys_opt_design.pb index 44cc91b..9f2f856 100644 Binary files a/PipelineProcessor.runs/impl_1/phys_opt_design.pb and b/PipelineProcessor.runs/impl_1/phys_opt_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/place_design.pb b/PipelineProcessor.runs/impl_1/place_design.pb index 94126a3..72b5c0b 100644 Binary files a/PipelineProcessor.runs/impl_1/place_design.pb and b/PipelineProcessor.runs/impl_1/place_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/route_design.pb b/PipelineProcessor.runs/impl_1/route_design.pb index d0fa912..ac01f96 100644 Binary files a/PipelineProcessor.runs/impl_1/route_design.pb and b/PipelineProcessor.runs/impl_1/route_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/vivado.jou b/PipelineProcessor.runs/impl_1/vivado.jou index 1e08ae5..843e35e 100644 --- a/PipelineProcessor.runs/impl_1/vivado.jou +++ b/PipelineProcessor.runs/impl_1/vivado.jou @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Sat Jul 13 23:39:15 2024 -# Process ID: 27020 +# Start of session at: Mon Jul 15 21:30:00 2024 +# Process ID: 34208 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1 # Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi diff --git a/PipelineProcessor.runs/impl_1/vivado.pb b/PipelineProcessor.runs/impl_1/vivado.pb index 61c3db1..061f07e 100644 Binary files a/PipelineProcessor.runs/impl_1/vivado.pb and b/PipelineProcessor.runs/impl_1/vivado.pb differ diff --git a/PipelineProcessor.runs/impl_1/write_bitstream.pb b/PipelineProcessor.runs/impl_1/write_bitstream.pb index 736867d..305619c 100644 Binary files a/PipelineProcessor.runs/impl_1/write_bitstream.pb and b/PipelineProcessor.runs/impl_1/write_bitstream.pb differ diff --git a/PipelineProcessor.runs/phase_locked_loop_synth_1/.Xil/phase_locked_loop_propImpl.xdc b/PipelineProcessor.runs/phase_locked_loop_synth_1/.Xil/phase_locked_loop_propImpl.xdc deleted file mode 100644 index ead314a..0000000 --- a/PipelineProcessor.runs/phase_locked_loop_synth_1/.Xil/phase_locked_loop_propImpl.xdc +++ /dev/null @@ -1,4 +0,0 @@ -set_property SRC_FILE_INFO {cfile:d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc rfile:../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc id:1 order:EARLY scoped_inst:inst} [current_design] -current_instance inst -set_property src_info {type:SCOPED_XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] -set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100 diff --git a/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc b/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc deleted file mode 100644 index f0ba149..0000000 --- a/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc +++ /dev/null @@ -1,32 +0,0 @@ -# This file is automatically generated. -# It contains project source information necessary for synthesis and implementation. - -# IP: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci -# IP: The module: 'phase_locked_loop' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc -# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint. -set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet - -# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc -# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint. -#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet - -# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint. -#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet - -# IP: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci -# IP: The module: 'phase_locked_loop' is the root of the design. Do not add the DONT_TOUCH constraint. - -# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc -# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint. -#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet - -# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc -# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint. -#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet - -# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc -# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint. -#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet diff --git a/PipelineProcessor.runs/phase_locked_loop_synth_1/htr.txt b/PipelineProcessor.runs/phase_locked_loop_synth_1/htr.txt deleted file mode 100644 index 6a47774..0000000 --- a/PipelineProcessor.runs/phase_locked_loop_synth_1/htr.txt +++ /dev/null @@ -1,10 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -REM Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -REM - -vivado -log phase_locked_loop.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source phase_locked_loop.tcl diff --git a/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp b/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp deleted file mode 100644 index f0c0893..0000000 Binary files a/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp and /dev/null differ diff --git a/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.tcl b/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.tcl deleted file mode 100644 index c48b522..0000000 --- a/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.tcl +++ /dev/null @@ -1,246 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -namespace eval ::optrace { - variable script "D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.tcl" - variable category "vivado_synth" -} - -# Try to connect to running dispatch if we haven't done so already. -# This code assumes that the Tcl interpreter is not using threads, -# since the ::dispatch::connected variable isn't mutex protected. -if {![info exists ::dispatch::connected]} { - namespace eval ::dispatch { - variable connected false - if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { - set result "true" - if {[catch { - if {[lsearch -exact [package names] DispatchTcl] < 0} { - set result [load librdi_cd_clienttcl[info sharedlibextension]] - } - if {$result eq "false"} { - puts "WARNING: Could not load dispatch client library" - } - set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] - if { $connect_id eq "" } { - puts "WARNING: Could not initialize dispatch client" - } else { - puts "INFO: Dispatch client connection id - $connect_id" - set connected true - } - } catch_res]} { - puts "WARNING: failed to connect to dispatch server - $catch_res" - } - } - } -} -if {$::dispatch::connected} { - # Remove the dummy proc if it exists. - if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { - rename ::OPTRACE "" - } - proc ::OPTRACE { task action {tags {} } } { - ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category - } - # dispatch is generic. We specifically want to attach logging. - ::vitis_log::connect_client -} else { - # Add dummy proc if it doesn't exist. - if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { - proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { - # Do nothing - } - } -} - -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -OPTRACE "phase_locked_loop_synth_1" START { ROLLUP_AUTO } -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -OPTRACE "Creating in-memory project" START { } -create_project -in_memory -part xc7a35tfgg484-1 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.cache/wt [current_project] -set_property parent.project_path D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.xpr [current_project] -set_property XPM_LIBRARIES XPM_CDC [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -OPTRACE "Creating in-memory project" END { } -OPTRACE "Adding files" START { } -read_ip -quiet D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci -set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc] -set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] -set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc] - -OPTRACE "Adding files" END { } -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -read_xdc dont_touch.xdc -set_property used_in_implementation false [get_files dont_touch.xdc] -set_param ips.enableIPCacheLiteLoad 1 -OPTRACE "Configure IP Cache" START { } - -set cacheID [config_ip_cache -export -no_bom -dir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1 -new_name phase_locked_loop -ip [get_ips phase_locked_loop]] - -OPTRACE "Configure IP Cache" END { } -if { $cacheID == "" } { -close [open __synthesis_is_running__ w] - -OPTRACE "synth_design" START { } -synth_design -top phase_locked_loop -part xc7a35tfgg484-1 -incremental_mode off -mode out_of_context -OPTRACE "synth_design" END { } -OPTRACE "Write IP Cache" START { } - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix phase_locked_loop_ phase_locked_loop.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_stub.v - lappend ipCachedFiles phase_locked_loop_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_stub.vhdl - lappend ipCachedFiles phase_locked_loop_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_sim_netlist.v - lappend ipCachedFiles phase_locked_loop_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_sim_netlist.vhdl - lappend ipCachedFiles phase_locked_loop_sim_netlist.vhdl - set TIME_taken [expr [clock seconds] - $TIME_start] - - if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } { - config_ip_cache -add -dcp phase_locked_loop.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips phase_locked_loop] - } -OPTRACE "Write IP Cache" END { } -} -if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { - send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" -} - -rename_ref -prefix_all phase_locked_loop_ - -OPTRACE "write_checkpoint" START { CHECKPOINT } -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef phase_locked_loop.dcp -OPTRACE "write_checkpoint" END { } -OPTRACE "synth reports" START { REPORT } -create_report "phase_locked_loop_synth_1_synth_report_utilization_0" "report_utilization -file phase_locked_loop_utilization_synth.rpt -pb phase_locked_loop_utilization_synth.pb" -OPTRACE "synth reports" END { } - -if { [catch { - file copy -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp -} _RESULT ] } { - send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - write_verilog -force -mode synth_stub d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -if { [catch { - file copy -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp -} _RESULT ] } { - send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file." - error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." -} - -if { [catch { - file rename -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_stub.v d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_stub.vhdl d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_sim_netlist.v d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - file rename -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_sim_netlist.vhdl d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -close [open .end.used_ip_cache.rst w] -}; # end if cacheID - -if {[file isdir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.ip_user_files/ip/phase_locked_loop]} { - catch { - file copy -force d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.ip_user_files/ip/phase_locked_loop - } -} - -if {[file isdir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.ip_user_files/ip/phase_locked_loop]} { - catch { - file copy -force d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.vhdl D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.ip_user_files/ip/phase_locked_loop - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] -OPTRACE "phase_locked_loop_synth_1" END { } diff --git a/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds b/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds deleted file mode 100644 index e339cff..0000000 --- a/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds +++ /dev/null @@ -1,240 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2023.2 (64-bit) -# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 -# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 -# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Thu Jul 11 13:35:23 2024 -# Process ID: 33384 -# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1 -# Command line: vivado.exe -log phase_locked_loop.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source phase_locked_loop.tcl -# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds -# Journal file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1\vivado.jou -# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB -#----------------------------------------------------------- -source phase_locked_loop.tcl -notrace -create_project: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 464.625 ; gain = 187.449 -INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: phase_locked_loop -Command: synth_design -top phase_locked_loop -part xc7a35tfgg484-1 -incremental_mode off -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' -INFO: [Device 21-403] Loading part xc7a35tfgg484-1 -INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. -INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 27764 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 1306.332 ; gain = 439.227 ---------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v:65] -INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop_clk_wiz' [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v:65] -INFO: [Synth 8-6157] synthesizing module 'IBUF' [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631] -INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631] -INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111351] - Parameter BANDWIDTH bound to: OPTIMIZED - type: string - Parameter CLKFBOUT_MULT bound to: 17 - type: integer - Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double - Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double - Parameter CLKOUT0_DIVIDE bound to: 17 - type: integer - Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double - Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double - Parameter COMPENSATION bound to: ZHOLD - type: string - Parameter DIVCLK_DIVIDE bound to: 2 - type: integer - Parameter STARTUP_WAIT bound to: FALSE - type: string -INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111351] -INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951] -INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951] -INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop_clk_wiz' (0#1) [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v:65] -INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v:65] ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1415.195 ; gain = 548.090 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1415.195 ; gain = 548.090 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1415.195 ; gain = 548.090 ---------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1415.195 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc] for cell 'inst' -Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc] for cell 'inst' -Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc] for cell 'inst' -Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc] for cell 'inst' -Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'inst' -Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'inst' -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/phase_locked_loop_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/phase_locked_loop_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -INFO: [Timing 38-2] Deriving generated clocks -Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc] -Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1429.117 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1429.145 ; gain = 0.027 -INFO: [Designutils 20-5008] Incremental synthesis strategy off ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7a35tfgg484-1 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc, line 9). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 90 (col length:60) -BRAMs: 100 (col length: RAMB18 60 RAMB36 30) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -WARNING: [Synth 8-7080] Parallel synthesis criteria is not met ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+----------+------+ -| |Cell |Count | -+------+----------+------+ -|1 |BUFG | 2| -|2 |PLLE2_ADV | 1| -|3 |IBUF | 1| -+------+----------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1429.145 ; gain = 548.090 -Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039 -INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1429.145 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1434.039 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Synth Design complete | Checksum: 5cde1ffc -INFO: [Common 17-83] Releasing license: Synthesis -30 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:23 . Memory (MB): peak = 1434.039 ; gain = 956.965 -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1434.039 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp' has been generated. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP phase_locked_loop, cache-ID = 11b3438a8319906c -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1434.039 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file phase_locked_loop_utilization_synth.rpt -pb phase_locked_loop_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Thu Jul 11 13:35:55 2024... diff --git a/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_utilization_synth.pb b/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_utilization_synth.pb deleted file mode 100644 index 2afd0fc..0000000 Binary files a/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_utilization_synth.pb and /dev/null differ diff --git a/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_utilization_synth.rpt b/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_utilization_synth.rpt deleted file mode 100644 index e7bc71d..0000000 --- a/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_utilization_synth.rpt +++ /dev/null @@ -1,175 +0,0 @@ -Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Thu Jul 11 13:35:55 2024 -| Host : Viviana running 64-bit major release (build 9200) -| Command : report_utilization -file phase_locked_loop_utilization_synth.rpt -pb phase_locked_loop_utilization_synth.pb -| Design : phase_locked_loop -| Device : xc7a35tfgg484-1 -| Speed File : -1 -| Design State : Synthesized ---------------------------------------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-------------------------+------+-------+------------+-----------+-------+ -| Slice LUTs* | 0 | 0 | 0 | 20800 | 0.00 | -| LUT as Logic | 0 | 0 | 0 | 20800 | 0.00 | -| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | -| Slice Registers | 0 | 0 | 0 | 41600 | 0.00 | -| Register as Flip Flop | 0 | 0 | 0 | 41600 | 0.00 | -| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | -| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 | -| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 | -+-------------------------+------+-------+------------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. -Warning! LUT value is adjusted to account for LUT combining. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 0 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+----------------+------+-------+------------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 0 | 50 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 | -| RAMB18 | 0 | 0 | 0 | 100 | 0.00 | -+----------------+------+-------+------------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-----------+------+-------+------------+-----------+-------+ -| DSPs | 0 | 0 | 0 | 90 | 0.00 | -+-----------+------+-------+------------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-----------------------------+------+-------+------------+-----------+-------+ -| Bonded IOB | 1 | 0 | 0 | 250 | 0.40 | -| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 | -| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 | -| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 | -| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 | -| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 | -| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 | -| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 | -| IBUFDS | 0 | 0 | 0 | 240 | 0.00 | -| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 | -| ILOGIC | 0 | 0 | 0 | 250 | 0.00 | -| OLOGIC | 0 | 0 | 0 | 250 | 0.00 | -+-----------------------------+------+-------+------------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+------------+------+-------+------------+-----------+-------+ -| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 | -| BUFIO | 0 | 0 | 0 | 20 | 0.00 | -| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 | -| PLLE2_ADV | 1 | 0 | 0 | 5 | 20.00 | -| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 | -| BUFHCE | 0 | 0 | 0 | 72 | 0.00 | -| BUFR | 0 | 0 | 0 | 20 | 0.00 | -+------------+------+-------+------------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-------------+------+-------+------------+-----------+-------+ -| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+------------+-----------+-------+ - - -7. Primitives -------------- - -+-----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+-----------+------+---------------------+ -| BUFG | 2 | Clock | -| PLLE2_ADV | 1 | Clock | -| IBUF | 1 | IO | -+-----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.jou b/PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.jou deleted file mode 100644 index 22031c8..0000000 --- a/PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.jou +++ /dev/null @@ -1,14 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2023.2 (64-bit) -# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 -# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 -# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Thu Jul 11 13:35:23 2024 -# Process ID: 33384 -# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1 -# Command line: vivado.exe -log phase_locked_loop.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source phase_locked_loop.tcl -# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds -# Journal file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1\vivado.jou -# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB -#----------------------------------------------------------- -source phase_locked_loop.tcl -notrace diff --git a/PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.pb b/PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.pb deleted file mode 100644 index 9684c6f..0000000 Binary files a/PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.pb and /dev/null differ diff --git a/PipelineProcessor.runs/synth_1/CPU.dcp b/PipelineProcessor.runs/synth_1/CPU.dcp index f3baa75..07cec9d 100644 Binary files a/PipelineProcessor.runs/synth_1/CPU.dcp and b/PipelineProcessor.runs/synth_1/CPU.dcp differ diff --git a/PipelineProcessor.runs/synth_1/CPU.tcl b/PipelineProcessor.runs/synth_1/CPU.tcl index 1fb0494..74bfe41 100644 --- a/PipelineProcessor.runs/synth_1/CPU.tcl +++ b/PipelineProcessor.runs/synth_1/CPU.tcl @@ -70,7 +70,6 @@ proc create_report { reportName command } { } } OPTRACE "synth_1" START { ROLLUP_AUTO } -set_param chipscope.maxJobs 5 OPTRACE "Creating in-memory project" START { } create_project -in_memory -part xc7a35tfgg484-1 @@ -120,6 +119,8 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { read_xdc D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc set_property used_in_implementation false [get_files D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc] +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] set_param ips.enableIPCacheLiteLoad 1 read_checkpoint -auto_incremental -incremental D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp diff --git a/PipelineProcessor.runs/synth_1/CPU.vds b/PipelineProcessor.runs/synth_1/CPU.vds index fd00d79..d8e2c32 100644 --- a/PipelineProcessor.runs/synth_1/CPU.vds +++ b/PipelineProcessor.runs/synth_1/CPU.vds @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Sat Jul 13 23:37:30 2024 -# Process ID: 27796 +# Start of session at: Mon Jul 15 21:28:25 2024 +# Process ID: 34260 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1 # Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds @@ -12,7 +12,7 @@ # Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB #----------------------------------------------------------- source CPU.tcl -notrace -create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 462.984 ; gain = 184.277 +create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 463.656 ; gain = 184.578 Command: read_checkpoint -auto_incremental -incremental D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp INFO: [Vivado 12-5825] Read reference checkpoint from D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes @@ -25,13 +25,13 @@ INFO: [Designutils 20-5440] No compile time benefit to using incremental synthes INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 15424 +INFO: [Synth 8-7075] Helper process launched with PID 34600 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 1308.293 ; gain = 439.242 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 1309.031 ; gain = 440.004 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'CPU' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/CPU.v:2] -INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-27796-Viviana/realtime/phase_locked_loop_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-27796-Viviana/realtime/phase_locked_loop_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-34260-Viviana/realtime/phase_locked_loop_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-34260-Viviana/realtime/phase_locked_loop_stub.v:6] INFO: [Synth 8-6157] synthesizing module 'InstFetch' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstFetch.v:2] INFO: [Synth 8-6157] synthesizing module 'InstructionMemory' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3] INFO: [Synth 8-6155] done synthesizing module 'InstructionMemory' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3] @@ -66,18 +66,18 @@ WARNING: [Synth 8-7129] Port address[0] in module DataMemory is either unconnect WARNING: [Synth 8-7129] Port address[1] in module InstructionMemory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module InstructionMemory is either unconnected or has no load --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.973 ; gain = 609.922 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.824 ; gain = 609.797 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1478.973 ; gain = 609.922 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.824 ; gain = 609.797 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1478.973 ; gain = 609.922 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.824 ; gain = 609.797 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.191 . Memory (MB): peak = 1478.973 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.169 . Memory (MB): peak = 1478.824 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints @@ -88,24 +88,26 @@ Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcesso Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/CPU_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/CPU_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/dont_touch.xdc] +Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1586.277 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1583.539 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1586.277 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.061 . Memory (MB): peak = 1583.539 ; gain = 0.000 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 1586.277 ; gain = 717.227 +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1583.539 ; gain = 714.512 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tfgg484-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 1586.277 ; gain = 717.227 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1583.539 ; gain = 714.512 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints @@ -114,10 +116,10 @@ Applied set_property IO_BUFFER_TYPE = NONE for hardware_clk. (constraint file d Applied set_property CLOCK_BUFFER_TYPE = NONE for hardware_clk. (constraint file d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc, line 4). Applied set_property KEEP_HIERARCHY = SOFT for pll. (constraint file auto generated constraint). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 1586.277 ; gain = 717.227 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1583.539 ; gain = 714.512 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:22 . Memory (MB): peak = 1586.277 ; gain = 717.227 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:18 . Memory (MB): peak = 1583.539 ; gain = 714.512 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics @@ -173,7 +175,7 @@ DSP Report: Generating DSP alu/result0, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator alu/result0 is absorbed into DSP alu/result0. DSP Report: operator alu/result0 is absorbed into DSP alu/result0. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:00:44 . Memory (MB): peak = 1586.277 ; gain = 717.227 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:40 . Memory (MB): peak = 1583.539 ; gain = 714.512 --------------------------------------------------------------------------------- Sort Area is CPU__GC0 alu/result0_0 : 0 0 : 3101 5879 : Used 1 time 0 Sort Area is CPU__GC0 alu/result0_0 : 0 1 : 2778 5879 : Used 1 time 0 @@ -209,19 +211,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:51 . Memory (MB): peak = 1586.277 ; gain = 717.227 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:46 . Memory (MB): peak = 1583.539 ; gain = 714.512 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:01:07 . Memory (MB): peak = 1714.559 ; gain = 845.508 +Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:01:00 . Memory (MB): peak = 1713.750 ; gain = 844.723 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:02 ; elapsed = 00:01:14 . Memory (MB): peak = 1720.918 ; gain = 851.867 +Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:01:06 . Memory (MB): peak = 1720.066 ; gain = 851.039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -239,37 +241,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:03 ; elapsed = 00:01:19 . Memory (MB): peak = 1720.918 ; gain = 851.867 +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:01:11 . Memory (MB): peak = 1720.066 ; gain = 851.039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:03 ; elapsed = 00:01:19 . Memory (MB): peak = 1720.918 ; gain = 851.867 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:01:11 . Memory (MB): peak = 1720.066 ; gain = 851.039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:01:12 . Memory (MB): peak = 1720.066 ; gain = 851.039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:01:12 . Memory (MB): peak = 1720.066 ; gain = 851.039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:01:13 . Memory (MB): peak = 1720.066 ; gain = 851.039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:01:13 . Memory (MB): peak = 1720.066 ; gain = 851.039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -307,33 +309,33 @@ Report Cell Usage: |9 |LUT6 | 7154| |10 |MUXF7 | 2377| |11 |MUXF8 | 1088| -|12 |FDRE | 17752| -|13 |FDSE | 368| +|12 |FDRE | 17968| +|13 |FDSE | 152| |14 |IBUF | 1| |15 |OBUF | 13| +------+------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:01:13 . Memory (MB): peak = 1720.066 ; gain = 851.039 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:03 ; elapsed = 00:01:18 . Memory (MB): peak = 1720.918 ; gain = 744.562 -Synthesis Optimization Complete : Time (s): cpu = 00:00:03 ; elapsed = 00:01:22 . Memory (MB): peak = 1720.918 ; gain = 851.867 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:01:10 . Memory (MB): peak = 1720.066 ; gain = 746.324 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:01:13 . Memory (MB): peak = 1720.066 ; gain = 851.039 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.294 . Memory (MB): peak = 1720.918 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.237 . Memory (MB): peak = 1720.066 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 3507 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1720.918 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1720.688 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Synth Design complete | Checksum: 560bc728 +Synth Design complete | Checksum: 5b34e2bc INFO: [Common 17-83] Releasing license: Synthesis 51 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:03 ; elapsed = 00:01:29 . Memory (MB): peak = 1720.918 ; gain = 1244.781 -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1720.918 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:01:19 . Memory (MB): peak = 1720.688 ; gain = 1244.133 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1720.688 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 23:39:08 2024... +INFO: [Common 17-206] Exiting Vivado at Mon Jul 15 21:29:53 2024... diff --git a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt index 5936dd1..39305bc 100644 --- a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt +++ b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 23:39:08 2024 +| Date : Mon Jul 15 21:29:53 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb | Design : CPU @@ -58,8 +58,8 @@ Warning! LUT value is adjusted to account for LUT combining. | 0 | Yes | - | - | | 0 | Yes | - | Set | | 0 | Yes | - | Reset | -| 368 | Yes | Set | - | -| 17752 | Yes | Reset | - | +| 152 | Yes | Set | - | +| 17968 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -152,15 +152,15 @@ Warning! LUT value is adjusted to account for LUT combining. +----------+-------+---------------------+ | Ref Name | Used | Functional Category | +----------+-------+---------------------+ -| FDRE | 17752 | Flop & Latch | +| FDRE | 17968 | Flop & Latch | | LUT6 | 7154 | LUT | | MUXF7 | 2377 | MuxFx | | MUXF8 | 1088 | MuxFx | | LUT5 | 825 | LUT | -| FDSE | 368 | Flop & Latch | | LUT4 | 281 | LUT | | LUT3 | 230 | LUT | | LUT2 | 154 | LUT | +| FDSE | 152 | Flop & Latch | | CARRY4 | 39 | CarryLogic | | LUT1 | 15 | LUT | | OBUF | 13 | IO | diff --git a/PipelineProcessor.runs/synth_1/dont_touch.xdc b/PipelineProcessor.runs/synth_1/dont_touch.xdc new file mode 100644 index 0000000..9924d17 --- /dev/null +++ b/PipelineProcessor.runs/synth_1/dont_touch.xdc @@ -0,0 +1,7 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# XDC: new/top.xdc + +# IP: ip/phase_locked_loop/phase_locked_loop.xci +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==phase_locked_loop || ORIG_REF_NAME==phase_locked_loop} -quiet] -quiet diff --git a/PipelineProcessor.runs/synth_1/vivado.jou b/PipelineProcessor.runs/synth_1/vivado.jou index f702d7e..ef00eb3 100644 --- a/PipelineProcessor.runs/synth_1/vivado.jou +++ b/PipelineProcessor.runs/synth_1/vivado.jou @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Sat Jul 13 23:37:30 2024 -# Process ID: 27796 +# Start of session at: Mon Jul 15 21:28:25 2024 +# Process ID: 34260 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1 # Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds diff --git a/PipelineProcessor.runs/synth_1/vivado.pb b/PipelineProcessor.runs/synth_1/vivado.pb index 8786247..3737773 100644 Binary files a/PipelineProcessor.runs/synth_1/vivado.pb and b/PipelineProcessor.runs/synth_1/vivado.pb differ diff --git a/PipelineProcessor.srcs/sources_1/new/DataMemory.v b/PipelineProcessor.srcs/sources_1/new/DataMemory.v index 9d8a759..8e2e6fa 100644 --- a/PipelineProcessor.srcs/sources_1/new/DataMemory.v +++ b/PipelineProcessor.srcs/sources_1/new/DataMemory.v @@ -27,58 +27,31 @@ module DataMemory ( memory_data[i] <= 32'h00000000; end for ( - i = 72 + StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1 + i = 45 + StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1 ) begin memory_data[i] <= 32'h00000000; end - memory_data[StartAddressInWord+24] <= 32'h0000002F; - memory_data[StartAddressInWord+25] <= 32'h000018D0; - memory_data[StartAddressInWord+26] <= 32'h00003A27; - memory_data[StartAddressInWord+27] <= 32'h00004786; - memory_data[StartAddressInWord+28] <= 32'h0000C94D; - memory_data[StartAddressInWord+29] <= 32'h000064CA; - memory_data[StartAddressInWord+30] <= 32'h00008027; - memory_data[StartAddressInWord+31] <= 32'h0000C8C3; - memory_data[StartAddressInWord+32] <= 32'h0000E08B; - memory_data[StartAddressInWord+33] <= 32'h00006E15; - memory_data[StartAddressInWord+34] <= 32'h0000AA22; - memory_data[StartAddressInWord+35] <= 32'h00002E07; - memory_data[StartAddressInWord+36] <= 32'h00009F23; - memory_data[StartAddressInWord+37] <= 32'h00002F2B; - memory_data[StartAddressInWord+38] <= 32'h00004227; - memory_data[StartAddressInWord+39] <= 32'h0000022C; - memory_data[StartAddressInWord+40] <= 32'h00009776; - memory_data[StartAddressInWord+41] <= 32'h00009477; - memory_data[StartAddressInWord+42] <= 32'h0000AAF5; - memory_data[StartAddressInWord+43] <= 32'h000080BE; - memory_data[StartAddressInWord+44] <= 32'h00002CC7; - memory_data[StartAddressInWord+45] <= 32'h00009D7D; - memory_data[StartAddressInWord+46] <= 32'h00000F95; - memory_data[StartAddressInWord+47] <= 32'h0000E060; - memory_data[StartAddressInWord+48] <= 32'h00002137; - memory_data[StartAddressInWord+49] <= 32'h0000A5E5; - memory_data[StartAddressInWord+50] <= 32'h00001C49; - memory_data[StartAddressInWord+51] <= 32'h0000C308; - memory_data[StartAddressInWord+52] <= 32'h00001A04; - memory_data[StartAddressInWord+53] <= 32'h00005F99; - memory_data[StartAddressInWord+54] <= 32'h0000124C; - memory_data[StartAddressInWord+55] <= 32'h0000ABB3; - memory_data[StartAddressInWord+56] <= 32'h00000E87; - memory_data[StartAddressInWord+57] <= 32'h00005E55; - memory_data[StartAddressInWord+58] <= 32'h00002197; - memory_data[StartAddressInWord+59] <= 32'h00000AA4; - memory_data[StartAddressInWord+60] <= 32'h0000F7FE; - memory_data[StartAddressInWord+61] <= 32'h00007F32; - memory_data[StartAddressInWord+62] <= 32'h0000C5A5; - memory_data[StartAddressInWord+63] <= 32'h0000D87C; - memory_data[StartAddressInWord+64] <= 32'h0000E996; - memory_data[StartAddressInWord+65] <= 32'h00007345; - memory_data[StartAddressInWord+66] <= 32'h00009213; - memory_data[StartAddressInWord+67] <= 32'h000076EE; - memory_data[StartAddressInWord+68] <= 32'h0000260B; - memory_data[StartAddressInWord+69] <= 32'h0000E0D8; - memory_data[StartAddressInWord+70] <= 32'h0000D9CA; - memory_data[StartAddressInWord+71] <= 32'h00003B9F; + memory_data[StartAddressInWord+24] <= 32'h00000014; + memory_data[StartAddressInWord+25] <= 32'h000041A8; + memory_data[StartAddressInWord+26] <= 32'h00003AF2; + memory_data[StartAddressInWord+27] <= 32'h0000ACDA; + memory_data[StartAddressInWord+28] <= 32'h0000C0B2; + memory_data[StartAddressInWord+29] <= 32'h0000B783; + memory_data[StartAddressInWord+30] <= 32'h0000DAC9; + memory_data[StartAddressInWord+31] <= 32'h00008ED9; + memory_data[StartAddressInWord+32] <= 32'h000009FF; + memory_data[StartAddressInWord+33] <= 32'h00002F44; + memory_data[StartAddressInWord+34] <= 32'h0000044E; + memory_data[StartAddressInWord+35] <= 32'h00009899; + memory_data[StartAddressInWord+36] <= 32'h00003C56; + memory_data[StartAddressInWord+37] <= 32'h0000128D; + memory_data[StartAddressInWord+38] <= 32'h0000DBE3; + memory_data[StartAddressInWord+39] <= 32'h0000D4B4; + memory_data[StartAddressInWord+40] <= 32'h00003748; + memory_data[StartAddressInWord+41] <= 32'h00003918; + memory_data[StartAddressInWord+42] <= 32'h00004112; + memory_data[StartAddressInWord+43] <= 32'h0000C399; + memory_data[StartAddressInWord+44] <= 32'h00004955; end always @(posedge clk) begin @@ -87,58 +60,31 @@ module DataMemory ( memory_data[i] <= 32'h00000000; end for ( - i = 72 + StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1 + i = 45 + StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1 ) begin memory_data[i] <= 32'h00000000; end - memory_data[StartAddressInWord+24] <= 32'h0000002F; - memory_data[StartAddressInWord+25] <= 32'h000018D0; - memory_data[StartAddressInWord+26] <= 32'h00003A27; - memory_data[StartAddressInWord+27] <= 32'h00004786; - memory_data[StartAddressInWord+28] <= 32'h0000C94D; - memory_data[StartAddressInWord+29] <= 32'h000064CA; - memory_data[StartAddressInWord+30] <= 32'h00008027; - memory_data[StartAddressInWord+31] <= 32'h0000C8C3; - memory_data[StartAddressInWord+32] <= 32'h0000E08B; - memory_data[StartAddressInWord+33] <= 32'h00006E15; - memory_data[StartAddressInWord+34] <= 32'h0000AA22; - memory_data[StartAddressInWord+35] <= 32'h00002E07; - memory_data[StartAddressInWord+36] <= 32'h00009F23; - memory_data[StartAddressInWord+37] <= 32'h00002F2B; - memory_data[StartAddressInWord+38] <= 32'h00004227; - memory_data[StartAddressInWord+39] <= 32'h0000022C; - memory_data[StartAddressInWord+40] <= 32'h00009776; - memory_data[StartAddressInWord+41] <= 32'h00009477; - memory_data[StartAddressInWord+42] <= 32'h0000AAF5; - memory_data[StartAddressInWord+43] <= 32'h000080BE; - memory_data[StartAddressInWord+44] <= 32'h00002CC7; - memory_data[StartAddressInWord+45] <= 32'h00009D7D; - memory_data[StartAddressInWord+46] <= 32'h00000F95; - memory_data[StartAddressInWord+47] <= 32'h0000E060; - memory_data[StartAddressInWord+48] <= 32'h00002137; - memory_data[StartAddressInWord+49] <= 32'h0000A5E5; - memory_data[StartAddressInWord+50] <= 32'h00001C49; - memory_data[StartAddressInWord+51] <= 32'h0000C308; - memory_data[StartAddressInWord+52] <= 32'h00001A04; - memory_data[StartAddressInWord+53] <= 32'h00005F99; - memory_data[StartAddressInWord+54] <= 32'h0000124C; - memory_data[StartAddressInWord+55] <= 32'h0000ABB3; - memory_data[StartAddressInWord+56] <= 32'h00000E87; - memory_data[StartAddressInWord+57] <= 32'h00005E55; - memory_data[StartAddressInWord+58] <= 32'h00002197; - memory_data[StartAddressInWord+59] <= 32'h00000AA4; - memory_data[StartAddressInWord+60] <= 32'h0000F7FE; - memory_data[StartAddressInWord+61] <= 32'h00007F32; - memory_data[StartAddressInWord+62] <= 32'h0000C5A5; - memory_data[StartAddressInWord+63] <= 32'h0000D87C; - memory_data[StartAddressInWord+64] <= 32'h0000E996; - memory_data[StartAddressInWord+65] <= 32'h00007345; - memory_data[StartAddressInWord+66] <= 32'h00009213; - memory_data[StartAddressInWord+67] <= 32'h000076EE; - memory_data[StartAddressInWord+68] <= 32'h0000260B; - memory_data[StartAddressInWord+69] <= 32'h0000E0D8; - memory_data[StartAddressInWord+70] <= 32'h0000D9CA; - memory_data[StartAddressInWord+71] <= 32'h00003B9F; + memory_data[StartAddressInWord+24] <= 32'h00000014; + memory_data[StartAddressInWord+25] <= 32'h000041A8; + memory_data[StartAddressInWord+26] <= 32'h00003AF2; + memory_data[StartAddressInWord+27] <= 32'h0000ACDA; + memory_data[StartAddressInWord+28] <= 32'h0000C0B2; + memory_data[StartAddressInWord+29] <= 32'h0000B783; + memory_data[StartAddressInWord+30] <= 32'h0000DAC9; + memory_data[StartAddressInWord+31] <= 32'h00008ED9; + memory_data[StartAddressInWord+32] <= 32'h000009FF; + memory_data[StartAddressInWord+33] <= 32'h00002F44; + memory_data[StartAddressInWord+34] <= 32'h0000044E; + memory_data[StartAddressInWord+35] <= 32'h00009899; + memory_data[StartAddressInWord+36] <= 32'h00003C56; + memory_data[StartAddressInWord+37] <= 32'h0000128D; + memory_data[StartAddressInWord+38] <= 32'h0000DBE3; + memory_data[StartAddressInWord+39] <= 32'h0000D4B4; + memory_data[StartAddressInWord+40] <= 32'h00003748; + memory_data[StartAddressInWord+41] <= 32'h00003918; + memory_data[StartAddressInWord+42] <= 32'h00004112; + memory_data[StartAddressInWord+43] <= 32'h0000C399; + memory_data[StartAddressInWord+44] <= 32'h00004955; end else begin if (write_enable) begin memory_data[address[31:2]] <= write_data; diff --git a/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp b/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp index d6bde76..7ffac7b 100644 Binary files a/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp and b/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp differ diff --git a/PipelineProcessor.xpr b/PipelineProcessor.xpr index 0eaa488..f6fdab9 100644 --- a/PipelineProcessor.xpr +++ b/PipelineProcessor.xpr @@ -67,13 +67,13 @@