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Pass jal, fix jr problem

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un-lock-able
2024-07-11 01:10:21 +08:00
parent 78f6fb4d50
commit 6a0772225a
4 changed files with 14 additions and 15 deletions
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BIN
PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
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19
PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
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@@ -7,22 +7,21 @@ module InstructionMemory (
always @(*) begin
case (address[31:2])
20'd0: instruction <= 32'h2011fffe; // addi $s1, $zero, 2
20'd0: instruction <= 32'h20110001; // addi $s1, $zero, 1
20'd1: instruction <= 32'h00000000;
20'd2: instruction <= 32'h00000000;
20'd3: instruction <= 32'h00000000;
20'd4: instruction <= 32'h00000000; // start:
20'd5: instruction <= 32'h22310001; // addi $s1, $s1, -1
20'd6: instruction <= 32'h00000000;
20'd7: instruction <= 32'h00000000;
20'd4: instruction <= 32'h00000000;
20'd5: instruction <= 32'h0c000007; // jal func
// end:
20'd6: instruction <= 32'h08000006; // j end
// func:
20'd7: instruction <= 32'h20120002; // addi $s2, $zero, 2
20'd8: instruction <= 32'h00000000;
20'd9: instruction <= 32'h00000000;
20'd10: instruction <= 32'h0620fffa; // bgtz $s1, start
20'd10: instruction <= 32'h00000000;
20'd11: instruction <= 32'h00000000;
20'd12: instruction <= 32'h00000000;
20'd13: instruction <= 32'h00000000;
20'd14: instruction <= 32'h00000000; // end:
20'd15: instruction <= 32'h0800000f; // j end
20'd12: instruction <= 32'h03e00008; // jr $ra
default: instruction <= 32'h00000000;
endcase
end

8
PipelineProcessor.srcs/sources_1/new/RegisterFile.v
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@@ -19,12 +19,12 @@ module RegisterFile (
integer i;
assign read_output1 = (read_addr1 == 5'b00000) ? 32'h00000000 :
(read_addr1 == write_ra_addr) ? write_ra_data :
(read_addr1 == write_addr) ? write_data : registers[read_addr1];
(read_addr1 == write_ra_addr && write_ra == 1'b1) ? write_ra_data :
(read_addr1 == write_addr && write_enable == 1'b1) ? write_data : registers[read_addr1];
assign read_output2 = (read_addr2 == 5'b00000) ? 32'h00000000 :
(read_addr2 == write_ra_addr) ? write_ra_data :
(read_addr2 == write_addr) ? write_data : registers[read_addr2];
(read_addr2 == write_ra_addr && write_ra == 1'b1) ? write_ra_data :
(read_addr2 == write_addr && write_enable == 1'b1) ? write_data : registers[read_addr2];
initial begin
for (i = 1; i < 32; i = i + 1) begin

2
PipelineProcessor.xpr
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@@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="200"/>
<Option Name="WTXSimLaunchSim" Val="216"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>