diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
index 3e792f5..0a4223d 100644
Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem and b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem differ
diff --git a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
index e8ff037..fce9110 100644
--- a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
+++ b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
@@ -7,17 +7,17 @@ module InstructionMemory (
always @(*) begin
case (address[31:2])
- 20'd0: instruction <= 32'h20110002; // addi $s1, $zero, 2
+ 20'd0: instruction <= 32'h2011fffe; // addi $s1, $zero, 2
20'd1: instruction <= 32'h00000000;
20'd2: instruction <= 32'h00000000;
20'd3: instruction <= 32'h00000000;
20'd4: instruction <= 32'h00000000; // start:
- 20'd5: instruction <= 32'h2231ffff; // addi $s1, $s1, -1
+ 20'd5: instruction <= 32'h22310001; // addi $s1, $s1, -1
20'd6: instruction <= 32'h00000000;
20'd7: instruction <= 32'h00000000;
20'd8: instruction <= 32'h00000000;
20'd9: instruction <= 32'h00000000;
- 20'd10: instruction <= 32'h1e20fffa; // bgtz $s1, start
+ 20'd10: instruction <= 32'h0620fffa; // bgtz $s1, start
20'd11: instruction <= 32'h00000000;
20'd12: instruction <= 32'h00000000;
20'd13: instruction <= 32'h00000000;
diff --git a/PipelineProcessor.xpr b/PipelineProcessor.xpr
index c0b0717..5b7c1af 100644
--- a/PipelineProcessor.xpr
+++ b/PipelineProcessor.xpr
@@ -60,7 +60,7 @@
-
+