diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
index 49ea5c6..58b8ee2 100644
Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem and b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem differ
diff --git a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
index 1e9e50f..9f1a7c7 100644
--- a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
+++ b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
@@ -7,16 +7,15 @@ module InstructionMemory (
always @(*) begin
case (address[31:2])
- 20'd0: instruction <= 32'h20110001; // addi $s1, $zero, 1
- 20'd6: instruction <= 32'h20120001; // addi $s2, $zero, 1
- 20'd11: instruction <= 32'h12320009; // beq $s1, $s2, beq_target
- 20'd16: instruction <= 32'h20130001; // addi $s3, $zero, 1
- // beq_target:
- 20'd21: instruction <= 32'h22310001; // addi $s1, $s1, 1
- 20'd26: instruction <= 32'h12320009; // beq $s1, $s2, beq_target2
- 20'd31: instruction <= 32'h20130003; // addi $s3, $zero, 3
- // beq_target2:
- 20'd36: instruction <= 32'h08100023; // j beq_target2
+ 20'd0: instruction <= 32'h20110001; // addi $s1, $zero, 1
+ 20'd6: instruction <= 32'h16320009; // bne $s1, $s2, bne_target
+ 20'd11: instruction <= 32'h20130001; // addi $s3, $zero, 1
+ // bne_target:
+ 20'd16: instruction <= 32'h20120001; // addi $s2, $zero, 1
+ 20'd21: instruction <= 32'h16320009; // bne $s1, $s2, bne_target2
+ 20'd26: instruction <= 32'h20130002; // addi $s3, $zero, 2
+ // bne_target2:
+ 20'd31: instruction <= 32'h0810001e; // j bne_target2
default: instruction <= 32'h00000000;
endcase
end
diff --git a/PipelineProcessor.xpr b/PipelineProcessor.xpr
index 3a3c116..4f4a892 100644
--- a/PipelineProcessor.xpr
+++ b/PipelineProcessor.xpr
@@ -60,7 +60,7 @@
-
+