From c1e3ac203f92add3f85f4bdc7b0bd5f2a7354045 Mon Sep 17 00:00:00 2001 From: un-lock-able Date: Wed, 10 Jul 2024 12:06:19 +0800 Subject: [PATCH] Initial commit --- .gitignore | 86 +++ .../a/4/a4c5028597ba9ab4/a4c5028597ba9ab4.xci | 295 ++++++++ .../4/a4c5028597ba9ab4/phase_locked_loop.dcp | Bin 0 -> 12538 bytes .../phase_locked_loop_sim_netlist.v | 220 ++++++ .../a4c5028597ba9ab4/phase_locked_loop_stub.v | 24 + .../doc/clk_wiz_v6_0_changelog.txt | 311 ++++++++ .../phase_locked_loop/phase_locked_loop.dcp | Bin 0 -> 12622 bytes .../ip/phase_locked_loop/phase_locked_loop.v | 89 +++ .../phase_locked_loop/phase_locked_loop.xdc | 57 ++ .../phase_locked_loop_board.xdc | 2 + .../phase_locked_loop_clk_wiz.v | 181 +++++ .../phase_locked_loop_ooc.xdc | 55 ++ .../phase_locked_loop_sim_netlist.v | 220 ++++++ .../phase_locked_loop_stub.v | 24 + PipelineProcessor.ip_user_files/README.txt | 1 + .../phase_locked_loop_stub.v | 24 + .../phase_locked_loop/activehdl/README.txt | 50 ++ .../phase_locked_loop/activehdl/file_info.txt | 5 + .../phase_locked_loop/activehdl/glbl.v | 84 +++ .../phase_locked_loop/modelsim/README.txt | 50 ++ .../phase_locked_loop/modelsim/file_info.txt | 5 + .../phase_locked_loop/modelsim/glbl.v | 84 +++ .../phase_locked_loop/questa/README.txt | 50 ++ .../phase_locked_loop/questa/file_info.txt | 5 + .../phase_locked_loop/questa/glbl.v | 84 +++ .../phase_locked_loop/riviera/README.txt | 50 ++ .../phase_locked_loop/riviera/file_info.txt | 5 + .../phase_locked_loop/riviera/glbl.v | 84 +++ .../phase_locked_loop/vcs/README.txt | 50 ++ .../phase_locked_loop/vcs/file_info.txt | 5 + .../sim_scripts/phase_locked_loop/vcs/glbl.v | 84 +++ .../phase_locked_loop/xcelium/README.txt | 50 ++ .../phase_locked_loop/xcelium/file_info.txt | 5 + .../phase_locked_loop/xcelium/glbl.v | 84 +++ .../phase_locked_loop/xsim/README.txt | 50 ++ .../phase_locked_loop/xsim/cmd.tcl | 12 + .../phase_locked_loop/xsim/file_info.txt | 3 + .../sim_scripts/phase_locked_loop/xsim/glbl.v | 84 +++ .../phase_locked_loop/xsim/vlog.prj | 8 + .../.Xil/phase_locked_loop_propImpl.xdc | 4 + .../phase_locked_loop_synth_1/dont_touch.xdc | 32 + .../phase_locked_loop_synth_1/htr.txt | 10 + .../phase_locked_loop.dcp | Bin 0 -> 12622 bytes .../phase_locked_loop.tcl | 246 +++++++ .../phase_locked_loop.vds | 240 +++++++ .../phase_locked_loop_utilization_synth.pb | Bin 0 -> 276 bytes .../phase_locked_loop_utilization_synth.rpt | 175 +++++ .../phase_locked_loop_synth_1/vivado.jou | 14 + .../phase_locked_loop_synth_1/vivado.pb | Bin 0 -> 24812 bytes .../phase_locked_loop/phase_locked_loop.xci | 670 ++++++++++++++++++ PipelineProcessor.srcs/sources_1/new/ALU.v | 37 + PipelineProcessor.srcs/sources_1/new/CPU.v | 236 ++++++ .../sources_1/new/ControlUnit.v | 76 ++ .../sources_1/new/DataMemory.v | 24 + .../sources_1/new/Execution.v | 135 ++++ .../sources_1/new/ExecutionForward.v | 38 + .../sources_1/new/HazardUnit.v | 20 + .../sources_1/new/ImmediateExtender.v | 11 + .../sources_1/new/InstDecode.v | 138 ++++ .../sources_1/new/InstFetch.v | 39 + .../sources_1/new/InstructionMemory.v | 16 + .../sources_1/new/MemoryAccess.v | 72 ++ .../sources_1/new/MemoryForward.v | 11 + .../sources_1/new/RegisterFile.v | 46 ++ .../sources_1/new/WriteBack.v | 33 + PipelineProcessor.xpr | 354 +++++++++ 66 files changed, 5257 insertions(+) create mode 100644 .gitignore create mode 100644 PipelineProcessor.cache/ip/2023.2/a/4/a4c5028597ba9ab4/a4c5028597ba9ab4.xci create mode 100644 PipelineProcessor.cache/ip/2023.2/a/4/a4c5028597ba9ab4/phase_locked_loop.dcp create mode 100644 PipelineProcessor.cache/ip/2023.2/a/4/a4c5028597ba9ab4/phase_locked_loop_sim_netlist.v create mode 100644 PipelineProcessor.cache/ip/2023.2/a/4/a4c5028597ba9ab4/phase_locked_loop_stub.v create mode 100644 PipelineProcessor.gen/sources_1/ip/phase_locked_loop/doc/clk_wiz_v6_0_changelog.txt create mode 100644 PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp create mode 100644 PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v create mode 100644 PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc create mode 100644 PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc create mode 100644 PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v create mode 100644 PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc create mode 100644 PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v create mode 100644 PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v create mode 100644 PipelineProcessor.ip_user_files/README.txt create mode 100644 PipelineProcessor.ip_user_files/ip/phase_locked_loop/phase_locked_loop_stub.v create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/activehdl/README.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/activehdl/file_info.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/activehdl/glbl.v create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/modelsim/README.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/modelsim/file_info.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/modelsim/glbl.v create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/questa/README.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/questa/file_info.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/questa/glbl.v create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/riviera/README.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/riviera/file_info.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/riviera/glbl.v create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/vcs/README.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/vcs/file_info.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/vcs/glbl.v create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xcelium/README.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xcelium/file_info.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xcelium/glbl.v create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xsim/README.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xsim/cmd.tcl create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xsim/file_info.txt create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xsim/glbl.v create mode 100644 PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xsim/vlog.prj create mode 100644 PipelineProcessor.runs/phase_locked_loop_synth_1/.Xil/phase_locked_loop_propImpl.xdc create mode 100644 PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc create mode 100644 PipelineProcessor.runs/phase_locked_loop_synth_1/htr.txt create mode 100644 PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp create mode 100644 PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.tcl create mode 100644 PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds create mode 100644 PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_utilization_synth.pb create mode 100644 PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_utilization_synth.rpt create mode 100644 PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.jou create mode 100644 PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.pb create mode 100644 PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci create mode 100644 PipelineProcessor.srcs/sources_1/new/ALU.v create mode 100644 PipelineProcessor.srcs/sources_1/new/CPU.v create mode 100644 PipelineProcessor.srcs/sources_1/new/ControlUnit.v create mode 100644 PipelineProcessor.srcs/sources_1/new/DataMemory.v create mode 100644 PipelineProcessor.srcs/sources_1/new/Execution.v create mode 100644 PipelineProcessor.srcs/sources_1/new/ExecutionForward.v create mode 100644 PipelineProcessor.srcs/sources_1/new/HazardUnit.v create mode 100644 PipelineProcessor.srcs/sources_1/new/ImmediateExtender.v create mode 100644 PipelineProcessor.srcs/sources_1/new/InstDecode.v create mode 100644 PipelineProcessor.srcs/sources_1/new/InstFetch.v create mode 100644 PipelineProcessor.srcs/sources_1/new/InstructionMemory.v create mode 100644 PipelineProcessor.srcs/sources_1/new/MemoryAccess.v create mode 100644 PipelineProcessor.srcs/sources_1/new/MemoryForward.v create mode 100644 PipelineProcessor.srcs/sources_1/new/RegisterFile.v create mode 100644 PipelineProcessor.srcs/sources_1/new/WriteBack.v create mode 100644 PipelineProcessor.xpr diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..ba6053f --- /dev/null +++ b/.gitignore @@ -0,0 +1,86 @@ +######################################################################################################### +## This is an example .gitignore file for Vivado, please treat it as an example as +## it might not be complete. In addition, XAPP 1165 should be followed. +######################################################################################################### +######### +#Exclude all +######### +* +!*/ +!.gitignore +########################################################################### +## VIVADO +########################################################################### +######### +#Source files: +######### +#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. +!*.vhd +!*.v +!*.bd +!*.edif +######### +#IP files +######### +#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products +#.xci + .dcp: implementation possible but not re-synthesis +#*.xci(www.spiritconsortium.org) +!*.xci +#*.dcp(checkpoint files) +!*.dcp +!*.vds +!*.pb +#All bd comments and layout coordinates are stored within .ui +!*.ui +!*.ooc +######### +#System Generator +######### +!*.mdl +!*.slx +!*.bxml +######### +#Simulation logic analyzer +######### +!*.wcfg +!*.coe +######### +#MIG +######### +!*.prj +!*.mem +######### +#Project files +######### +#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) +#Do NOT ignore *.xpr files +!*.xpr +#Include *.xml files for 2013.4 or earlier version +#!*.xml +######### +#Constraint files +######### +#Do NOT ignore *.xdc files +!*.xdc +######### +#TCL - files +######### +!*.tcl +######### +#Journal - files +######### +!*.jou +######### +#Reports +######### +!*.rpt +!*.txt +!*.vdi +######### +#C-files +######### +!*.c +!*.h +!*.elf +!*.bmm +!*.xmp diff --git a/PipelineProcessor.cache/ip/2023.2/a/4/a4c5028597ba9ab4/a4c5028597ba9ab4.xci b/PipelineProcessor.cache/ip/2023.2/a/4/a4c5028597ba9ab4/a4c5028597ba9ab4.xci new file mode 100644 index 0000000..3c5afb5 --- /dev/null +++ b/PipelineProcessor.cache/ip/2023.2/a/4/a4c5028597ba9ab4/a4c5028597ba9ab4.xci @@ -0,0 +1,295 @@ + + + xilinx.com + ipcache + a4c5028597ba9ab4 + 0 + + + phase_locked_loop + + + 100000000 + 100000000 + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 100.0 + 0.010 + 100.0 + 0.010 + BUFG + 446.763 + false + 313.282 + 50.000 + 10.000 + 0.000 + 1 + true + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + BUFG + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + Custom + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + phase_locked_loop + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 41 + 0.000 + false + 10.000 + 10.000 + 82 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + ZHOLD + 5 + None + 0.010 + 0.010 + false + 1 + false + false + false + WAVEFORM + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + PLL + mmcm_adv + 100.000 + 0.010 + 10.000 + Single_ended_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + Custom + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false 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