Remove unused mem forward
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@@ -177,7 +177,6 @@ module CPU (
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.prev_ALU_result(EX_ALU_result),
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.prev_ALU_result(EX_ALU_result),
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.prev_memory_write_data(EX_memory_write_data),
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.prev_memory_write_data(EX_memory_write_data),
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.prev_register_write_destination(EX_register_write_destination),
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.prev_register_write_destination(EX_register_write_destination),
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.WB_forwarded_data(WB_register_write_data),
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.register_write(MEM_register_write),
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.register_write(MEM_register_write),
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.WB_source(MEM_WB_source),
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.WB_source(MEM_WB_source),
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.memory_read_data(MEM_memory_read_data),
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.memory_read_data(MEM_memory_read_data),
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@@ -203,7 +202,7 @@ module CPU (
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.register_write_addr(WB_register_write_address)
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.register_write_addr(WB_register_write_address)
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);
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);
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DataMemory #(.START_ADDRESS(32'h40000000)) data_memory (
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DataMemory #(.START_ADDRESS(32'h40000000), .MEM_SIZE_IN_WORD(512)) data_memory (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.address(MEM_data_memory_address),
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.address(MEM_data_memory_address),
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@@ -9,8 +9,6 @@ module MemoryAccess (
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input [31:0] prev_ALU_result,
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input [31:0] prev_ALU_result,
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input [31:0] prev_memory_write_data,
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input [31:0] prev_memory_write_data,
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input [4:0] prev_register_write_destination,
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input [4:0] prev_register_write_destination,
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// From WB
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input [31:0] WB_forwarded_data,
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// To next stage
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// To next stage
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output register_write,
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output register_write,
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output WB_source,
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output WB_source,
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@@ -1,11 +0,0 @@
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`timescale 1ns / 1ps
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module MemoryForward (
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input WB_register_write,
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input [4:0] WB_register_write_address,
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input [4:0] MEM_rt_address,
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output MEM_write_data_source
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);
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assign MEM_write_data_source = (WB_register_write == 1'b1) ?
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((MEM_rt_address != 5'b00000 && WB_register_write_address == MEM_rt_address) ? 1 : 0) : 0;
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endmodule
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