diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb b/PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb
index 71a5e13..83f391e 100644
Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb and b/PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
index 2bcc31b..b9d6d6d 100644
Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem and b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem differ
diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb b/PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb
index b635ca2..b155e40 100644
Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb and b/PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb differ
diff --git a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
index 576a8ed..e4b8198 100644
--- a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
+++ b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
@@ -7,17 +7,17 @@ module InstructionMemory (
always @(*) begin
case (address[31:2])
- 20'd0: instruction <= 32'h3c104000; // lui $s0, 0x4000
- 20'd6: instruction <= 32'h2011000a; // addi $s1, $0, 0xa
- 20'd11: instruction <= 32'hae110010; // sw $s1, 16($s0)
- 20'd16: instruction <= 32'h8e120010; // lw $s2, 16($s0)
- 20'd21: instruction <= 32'h2231fffe; // addi $s1, $s1, -2
- 20'd26: instruction <= 32'h02329820; // add $s3, $s1, $s2
- 20'd31: instruction <= 32'h02529821; // addu $s3, $s2, $s2
- 20'd36: instruction <= 32'h02519822; // sub $s3, $s2, $s1
- 20'd41: instruction <= 32'h02338823; // subu $s1, $s1, $s3
- 20'd46: instruction <= 32'h26310004; // addiu $s1, $s1, 4
- 20'd51: instruction <= 32'h02339018; // mul $s2, $s1, $s3
+ 20'd0: instruction <= 32'h3c1000ca; // lui $s0, 0xca
+ 20'd6: instruction <= 32'h221000fe; // addi $s0, $s0, 0xfe
+ 20'd11: instruction <= 32'h2011ffdf; // addi $s1, $zero, -0x21
+ 20'd16: instruction <= 32'h00109100; // sll $s2, $s0, 4
+ 20'd21: instruction <= 32'h00109082; // srl $s2, $s0, 2
+ 20'd26: instruction <= 32'h00119043; // sra $s2, $s1, 1
+ 20'd31: instruction <= 32'h0230902a; // slt $s2, $s1, $s0
+ 20'd36: instruction <= 32'h0211902a; // slt $s2, $s0, $s1
+ 20'd41: instruction <= 32'h0230882b; // sltu $s1, $s1, $s0
+ 20'd46: instruction <= 32'h2a120004; // slti $s2, $s0, 0x4
+ 20'd51: instruction <= 32'h2e12fffc; // sltiu $s2, $s0, -0x4
default: instruction <= 32'h00000000;
endcase
end
diff --git a/PipelineProcessor.xpr b/PipelineProcessor.xpr
index ba3b727..0aa2c70 100644
--- a/PipelineProcessor.xpr
+++ b/PipelineProcessor.xpr
@@ -60,7 +60,7 @@
-
+