diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
index c0ae0c5..f682f80 100644
Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem and b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem differ
diff --git a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
index c44a256..8975881 100644
--- a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
+++ b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
@@ -7,17 +7,11 @@ module InstructionMemory (
always @(*) begin
case (address[31:2])
- 20'd0: instruction <= 32'h3c104000;
- 20'd6: instruction <= 32'h2011000a;
- 20'd11: instruction <= 32'hae110010;
- 20'd16: instruction <= 32'h8e120010;
- 20'd21: instruction <= 32'h2231fffe;
- 20'd26: instruction <= 32'h02329820;
- 20'd31: instruction <= 32'h02529821;
- 20'd36: instruction <= 32'h02519822;
- 20'd41: instruction <= 32'h02338823;
- 20'd46: instruction <= 32'h26310004;
- 20'd51: instruction <= 32'h02339018;
+ 20'd0: instruction <= 32'h3c104000; // lui $s0, 0x4000
+ 20'd1: instruction <= 32'h20110001; // addi $s1, $zero, 1
+ 20'd2: instruction <= 32'hae110000; // sw $s1, 0($s0)
+ 20'd3: instruction <= 32'h8e120000; // lw $s2, 0($s0)
+ 20'd4: instruction <= 32'hae120004; // sw $s2, 4($s0)
default: instruction <= 32'h00000000;
endcase
end
diff --git a/PipelineProcessor.xpr b/PipelineProcessor.xpr
index 12c7679..0870fcd 100644
--- a/PipelineProcessor.xpr
+++ b/PipelineProcessor.xpr
@@ -60,7 +60,7 @@
-
+