diff --git a/PipelineProcessor.runs/impl_1/CPU.tcl b/PipelineProcessor.runs/impl_1/CPU.tcl index 4d857dd..c75b4d8 100644 --- a/PipelineProcessor.runs/impl_1/CPU.tcl +++ b/PipelineProcessor.runs/impl_1/CPU.tcl @@ -123,7 +123,6 @@ set ACTIVE_STEP init_design set rc [catch { create_msg_db init_design.pb set_param chipscope.maxJobs 5 - set_param xicom.use_bs_reader 1 set_param runs.launchOptions { -jobs 20 } OPTRACE "create in-memory project" START { } create_project -in_memory -part xc7a35tfgg484-1 diff --git a/PipelineProcessor.runs/impl_1/CPU.vdi b/PipelineProcessor.runs/impl_1/CPU.vdi index 25e0b58..ac2792c 100644 --- a/PipelineProcessor.runs/impl_1/CPU.vdi +++ b/PipelineProcessor.runs/impl_1/CPU.vdi @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Sat Jul 13 14:27:36 2024 -# Process ID: 19592 +# Start of session at: Sat Jul 13 23:39:15 2024 +# Process ID: 27020 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1 # Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi @@ -12,14 +12,14 @@ # Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB #----------------------------------------------------------- source CPU.tcl -notrace -create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 462.727 ; gain = 184.750 +create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 461.707 ; gain = 184.406 Command: link_design -top CPU -part xc7a35tfgg484-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7a35tfgg484-1 INFO: [Project 1-454] Reading design checkpoint 'd:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp' for cell 'pll' -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.175 . Memory (MB): peak = 915.922 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 3504 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 916.031 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 3508 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.2 INFO: [Project 1-570] Preparing netlist for logic optimization @@ -28,18 +28,18 @@ Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/Pipelin Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54] INFO: [Timing 38-2] Deriving generated clocks [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54] -get_clocks: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 1598.910 ; gain = 559.754 +get_clocks: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1599.215 ; gain = 558.836 Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst' Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc] Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1598.910 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1599.215 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 1598.910 ; gain = 1122.715 +link_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:13 . Memory (MB): peak = 1599.215 ; gain = 1122.352 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' @@ -50,112 +50,112 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1598.910 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.715 . Memory (MB): peak = 1599.215 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 144775da6 +Ending Cache Timing Information Task | Checksum: 1f0fa50d6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.821 . Memory (MB): peak = 1613.023 ; gain = 14.113 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.490 . Memory (MB): peak = 1613.043 ; gain = 13.828 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup -Phase 1.1 Core Generation And Design Setup | Checksum: 144775da6 +Phase 1.1 Core Generation And Design Setup | Checksum: 1f0fa50d6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.328 ; gain = 0.000 Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 144775da6 +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1f0fa50d6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Phase 1 Initialization | Checksum: 144775da6 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Phase 1 Initialization | Checksum: 1f0fa50d6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1972.328 ; gain = 0.000 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 144775da6 +Phase 2.1 Timer Update | Checksum: 1f0fa50d6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.617 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.387 . Memory (MB): peak = 1972.328 ; gain = 0.000 Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 144775da6 +Phase 2.2 Timing Data Collection | Checksum: 1f0fa50d6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.640 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Phase 2 Timer Update And Timing Data Collection | Checksum: 144775da6 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.405 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Phase 2 Timer Update And Timing Data Collection | Checksum: 1f0fa50d6 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.642 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.407 . Memory (MB): peak = 1972.328 ; gain = 0.000 Phase 3 Retarget INFO: [Opt 31-1566] Pulled 13 inverters resulting in an inversion of 263 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: 17395c2ed +Phase 3 Retarget | Checksum: 1e587632b -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.901 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Retarget | Checksum: 17395c2ed +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.567 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Retarget | Checksum: 1e587632b INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 14 cells INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: 1c089ccf4 +Phase 4 Constant propagation | Checksum: 1b5603850 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Constant propagation | Checksum: 1c089ccf4 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.652 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Constant propagation | Checksum: 1b5603850 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep -Phase 5 Sweep | Checksum: 12eb909f8 +Phase 5 Sweep | Checksum: 15ea6b1a3 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Sweep | Checksum: 12eb909f8 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.816 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Sweep | Checksum: 15ea6b1a3 INFO: [Opt 31-389] Phase Sweep created 12 cells and removed 0 cells Phase 6 BUFG optimization -Phase 6 BUFG optimization | Checksum: 12eb909f8 +Phase 6 BUFG optimization | Checksum: 15ea6b1a3 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000 -BUFG optimization | Checksum: 12eb909f8 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.949 . Memory (MB): peak = 1972.328 ; gain = 0.000 +BUFG optimization | Checksum: 15ea6b1a3 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: 12eb909f8 +Phase 7 Shift Register Optimization | Checksum: 15ea6b1a3 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Shift Register Optimization | Checksum: 12eb909f8 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.959 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Shift Register Optimization | Checksum: 15ea6b1a3 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: 17562fe4e +Phase 8 Post Processing Netlist | Checksum: 118407d59 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Post Processing Netlist | Checksum: 17562fe4e +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.991 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Post Processing Netlist | Checksum: 118407d59 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1329e1c39 +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1587ffb16 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Phase 9.2 Verifying Netlist Connectivity | Checksum: 1329e1c39 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Phase 9.2 Verifying Netlist Connectivity | Checksum: 1587ffb16 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Phase 9 Finalization | Checksum: 1329e1c39 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Phase 9 Finalization | Checksum: 1587ffb16 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000 Opt_design Change Summary ========================= @@ -172,32 +172,31 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- -Ending Logic Optimization Task | Checksum: 1329e1c39 +Ending Logic Optimization Task | Checksum: 1587ffb16 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.328 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 1329e1c39 +Ending Power Optimization Task | Checksum: 1587ffb16 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1972.328 ; gain = 0.000 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1329e1c39 +Ending Final Cleanup Task | Checksum: 1587ffb16 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.328 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 1329e1c39 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 1587ffb16 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1972.328 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 1972.844 ; gain = 373.934 INFO: [runtcl-4] Executing : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx Command: report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. @@ -205,16 +204,16 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt. report_drc completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. -Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1972.328 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1972.328 ; gain = 0.000 Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1972.328 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_opt.dcp' has been generated. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -234,59 +233,59 @@ Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9a573811 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14ae9822c -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1972.844 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1972.328 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1972.328 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 161645cda +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b434b971 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 254135206 +Phase 1.3 Build Placer Netlist Model | Checksum: c5c27cdb -Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 254135206 +Phase 1.4 Constrain Clocks/Macros | Checksum: c5c27cdb -Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2040.230 ; gain = 67.387 -Phase 1 Placer Initialization | Checksum: 254135206 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Phase 1 Placer Initialization | Checksum: c5c27cdb -Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 2 Global Placement Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 21edfd7da +Phase 2.1 Floorplanning | Checksum: 146e69098 -Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: 187f6e72f +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 151ff6269 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 2.3 Post-Processing in Floorplanning -Phase 2.3 Post-Processing in Floorplanning | Checksum: 187f6e72f +Phase 2.3 Post-Processing in Floorplanning | Checksum: 151ff6269 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis -Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 2bcb2d97a +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: a33c0039 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:12 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 2.4.2 Physical Synthesis In Placer -INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 61 LUT instances to create LUTNM shape +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 55 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 -INFO: [Physopt 32-1138] End 1 Pass. Optimized 29 nets or LUTs. Breaked 0 LUT, combined 29 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-1138] End 1 Pass. Optimized 25 nets or LUTs. Breaked 0 LUT, combined 25 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell @@ -297,7 +296,7 @@ INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2040.230 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2039.625 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ @@ -306,7 +305,7 @@ Summary of Physical Synthesis Optimizations ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- -| LUT Combining | 0 | 29 | 29 | 0 | 1 | 00:00:00 | +| LUT Combining | 0 | 25 | 25 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | @@ -315,59 +314,59 @@ Summary of Physical Synthesis Optimizations | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 29 | 29 | 0 | 4 | 00:00:00 | +| Total | 0 | 25 | 25 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- -Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1cd490dfe +Phase 2.4.2 Physical Synthesis In Placer | Checksum: f4053bc8 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2040.230 ; gain = 67.387 -Phase 2.4 Global Placement Core | Checksum: 2593ef06b +Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Phase 2.4 Global Placement Core | Checksum: 1099bb7b7 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2040.230 ; gain = 67.387 -Phase 2 Global Placement | Checksum: 2593ef06b +Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Phase 2 Global Placement | Checksum: 1099bb7b7 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 24c2e5196 +Phase 3.1 Commit Multi Column Macros | Checksum: 10f07ac64 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:14 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b29cdebe +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1626a5454 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 1fd1f47c3 +Phase 3.3 Area Swap Optimization | Checksum: 14fc2b59e -Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 1bbf6b047 +Phase 3.4 Pipeline Register Optimization | Checksum: 169ab9d86 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 1f0217d20 +Phase 3.5 Small Shape Detail Placement | Checksum: 10a431286 -Time (s): cpu = 00:00:09 ; elapsed = 00:00:26 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 149d47d39 +Phase 3.6 Re-assign LUT pins | Checksum: 145095dfd -Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 14f4d2963 +Phase 3.7 Pipeline Register Optimization | Checksum: 1b6341a4b -Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 2040.230 ; gain = 67.387 -Phase 3 Detail Placement | Checksum: 14f4d2963 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297 +Phase 3 Detail Placement | Checksum: 1b6341a4b -Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 2040.230 ; gain = 67.387 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297 Phase 4 Post Placement Optimization and Clean-Up @@ -375,7 +374,7 @@ Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 1b9a7b723 +Post Placement Optimization Initialization | Checksum: 253ce2c5c Phase 4.1.1.1 BUFG Insertion @@ -383,34 +382,34 @@ Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.040 | TNS=0.000 | -Phase 1 Physical Synthesis Initialization | Checksum: 19276cbb6 +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.979 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 16956e8df -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.744 . Memory (MB): peak = 2088.574 ; gain = 13.941 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.808 . Memory (MB): peak = 2085.480 ; gain = 13.727 INFO: [Place 46-33] Processed net data_memory/reset, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. -Ending Physical Synthesis Task | Checksum: 19276cbb6 +Ending Physical Synthesis Task | Checksum: 16956e8df -Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2090.840 ; gain = 16.207 -Phase 4.1.1.1 BUFG Insertion | Checksum: 1b9a7b723 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2087.383 ; gain = 15.629 +Phase 4.1.1.1 BUFG Insertion | Checksum: 253ce2c5c -Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 Phase 4.1.1.2 Post Placement Timing Optimization -INFO: [Place 30-746] Post Placement Timing Summary WNS=2.040. For the most accurate timing information please run report_timing. -Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1b853f6e8 +INFO: [Place 30-746] Post Placement Timing Summary WNS=2.979. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1e8b73056 -Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 -Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996 -Phase 4.1 Post Commit Optimization | Checksum: 1b853f6e8 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 +Phase 4.1 Post Commit Optimization | Checksum: 1e8b73056 -Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 1b853f6e8 +Phase 4.2 Post Placement Cleanup | Checksum: 1e8b73056 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 Phase 4.3 Placer Reporting @@ -420,51 +419,51 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| -| North| 4x4| 2x2| +| North| 2x2| 1x1| |___________|___________________|___________________| -| South| 1x1| 1x1| +| South| 1x1| 2x2| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| -Phase 4.3.1 Print Estimated Congestion | Checksum: 1b853f6e8 +Phase 4.3.1 Print Estimated Congestion | Checksum: 1e8b73056 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680 -Phase 4.3 Placer Reporting | Checksum: 1b853f6e8 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 +Phase 4.3 Placer Reporting | Checksum: 1e8b73056 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2091.523 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2087.383 ; gain = 0.000 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 10fcc6d31 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 11ee518f9 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680 -Ending Placer Task | Checksum: 51a85dd7 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 +Ending Placer Task | Checksum: 91ee5898 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055 66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.523 ; gain = 118.680 +place_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:33 . Memory (MB): peak = 2087.383 ; gain = 115.055 INFO: [runtcl-4] Executing : report_io -file CPU_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 2091.523 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 2087.383 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 2091.523 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 2087.383 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 2106.918 ; gain = 1.973 -Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2106.918 ; gain = 0.000 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2106.918 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2105.285 ; gain = 2.945 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2105.285 ; gain = 2.945 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.285 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2106.918 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2106.918 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2106.918 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2106.918 ; gain = 1.973 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2105.285 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 2105.285 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2105.285 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2105.285 ; gain = 2.945 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_placed.dcp' has been generated. Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -472,23 +471,23 @@ INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc Starting Initial Update Timing Task -Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2153.953 ; gain = 47.035 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 2150.406 ; gain = 45.121 INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 75 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2179.293 ; gain = 7.062 -Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2179.293 ; gain = 7.062 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2179.293 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 2175.750 ; gain = 7.027 +Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2177.184 ; gain = 1.434 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2177.184 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2179.293 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 2179.293 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2179.293 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2179.293 ; gain = 7.062 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2177.184 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 2177.184 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2177.184 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2177.184 ; gain = 8.461 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -503,30 +502,30 @@ Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design -Checksum: PlaceDB: 4fa4d64c ConstDB: 0 ShapeSum: 203878b RouteDB: 0 -Post Restoration Checksum: NetGraph: c8a283dc | NumContArr: aad6ec74 | Constraints: c2a8fa9d | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 2f8cb658a +Checksum: PlaceDB: 7d4dfd1d ConstDB: 0 ShapeSum: 14a05b7b RouteDB: 0 +Post Restoration Checksum: NetGraph: 678b964f | NumContArr: 2f28cab3 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 21c06563c -Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2289.805 ; gain = 79.008 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 2288.059 ; gain = 82.391 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 2f8cb658a +Phase 2.1 Fix Topology Constraints | Checksum: 21c06563c -Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2289.805 ; gain = 79.008 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 2288.059 ; gain = 82.391 Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 2f8cb658a +Phase 2.2 Pre Route Cleanup | Checksum: 21c06563c -Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2289.805 ; gain = 79.008 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 2288.059 ; gain = 82.391 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing -Phase 2.3 Update Timing | Checksum: 201a59748 +Phase 2.3 Update Timing | Checksum: 30afab1eb -Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 2307.527 ; gain = 96.730 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.230 | TNS=0.000 | WHS=-0.144 | THS=-28.052| +Time (s): cpu = 00:00:02 ; elapsed = 00:00:18 . Memory (MB): peak = 2305.797 ; gain = 100.129 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.232 | TNS=0.000 | WHS=-0.150 | THS=-18.367| Router Utilization Summary @@ -535,93 +534,93 @@ Router Utilization Summary Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. - Number of Failed Nets = 21997 + Number of Failed Nets = 22010 (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 21997 + Number of Unrouted Nets = 22010 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 2 Router Initialization | Checksum: 276df3972 +Phase 2 Router Initialization | Checksum: 3338dbc90 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2345.027 ; gain = 134.230 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.363 ; gain = 141.695 Phase 3 Initial Routing Phase 3.1 Global Routing -Phase 3.1 Global Routing | Checksum: 276df3972 +Phase 3.1 Global Routing | Checksum: 3338dbc90 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2345.027 ; gain = 134.230 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.363 ; gain = 141.695 Phase 3.2 Initial Net Routing -Phase 3.2 Initial Net Routing | Checksum: 1646cdf4d +Phase 3.2 Initial Net Routing | Checksum: 18b5441e3 -Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 2349.422 ; gain = 138.625 -Phase 3 Initial Routing | Checksum: 1646cdf4d +Time (s): cpu = 00:00:04 ; elapsed = 00:00:21 . Memory (MB): peak = 2348.094 ; gain = 142.426 +Phase 3 Initial Routing | Checksum: 18b5441e3 -Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 2349.422 ; gain = 138.625 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:21 . Memory (MB): peak = 2348.094 ; gain = 142.426 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 3178 - Number of Nodes with overlaps = 255 - Number of Nodes with overlaps = 41 + Number of Nodes with overlaps = 3428 + Number of Nodes with overlaps = 278 + Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 12 - Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.679 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.537 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 3741328e8 +Phase 4.1 Global Iteration 0 | Checksum: 2a3342fb1 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:31 . Memory (MB): peak = 2352.559 ; gain = 141.762 -Phase 4 Rip-up And Reroute | Checksum: 3741328e8 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.875 ; gain = 147.207 +Phase 4 Rip-up And Reroute | Checksum: 2a3342fb1 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:31 . Memory (MB): peak = 2352.559 ; gain = 141.762 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.875 ; gain = 147.207 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing -Phase 5.1.1 Update Timing | Checksum: 2b9958991 +Phase 5.1.1 Update Timing | Checksum: 294396ac7 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.679 | TNS=0.000 | WHS=N/A | THS=N/A | +Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.879 ; gain = 147.211 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.537 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 5.1 Delay CleanUp | Checksum: 2b9958991 +Phase 5.1 Delay CleanUp | Checksum: 294396ac7 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.879 ; gain = 147.211 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 2b9958991 +Phase 5.2 Clock Skew Optimization | Checksum: 294396ac7 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762 -Phase 5 Delay and Skew Optimization | Checksum: 2b9958991 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:34 . Memory (MB): peak = 2352.879 ; gain = 147.211 +Phase 5 Delay and Skew Optimization | Checksum: 294396ac7 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:34 . Memory (MB): peak = 2352.879 ; gain = 147.211 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 2903d569b +Phase 6.1.1 Update Timing | Checksum: 26ed22ad4 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.679 | TNS=0.000 | WHS=0.070 | THS=0.000 | +Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.537 | TNS=0.000 | WHS=0.055 | THS=0.000 | -Phase 6.1 Hold Fix Iter | Checksum: 2ecebe266 +Phase 6.1 Hold Fix Iter | Checksum: 26dd53850 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762 -Phase 6 Post Hold Fix | Checksum: 2ecebe266 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211 +Phase 6 Post Hold Fix | Checksum: 26dd53850 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 16.0809 % - Global Horizontal Routing Utilization = 14.8794 % + Global Vertical Routing Utilization = 15.1075 % + Global Horizontal Routing Utilization = 15.2186 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -631,44 +630,44 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 7 Route finalize | Checksum: 2ecebe266 +Phase 7 Route finalize | Checksum: 26dd53850 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 2ecebe266 +Phase 8 Verifying routed nets | Checksum: 26dd53850 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2354.578 ; gain = 143.781 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.930 ; gain = 149.262 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 2aa639e35 +Phase 9 Depositing Routes | Checksum: 1e498ff47 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:34 . Memory (MB): peak = 2354.578 ; gain = 143.781 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.930 ; gain = 149.262 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=2.679 | TNS=0.000 | WHS=0.070 | THS=0.000 | +INFO: [Route 35-57] Estimated Timing Summary | WNS=3.537 | TNS=0.000 | WHS=0.055 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 2aa639e35 +Phase 10 Post Router Timing | Checksum: 1e498ff47 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.578 ; gain = 143.781 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:36 . Memory (MB): peak = 2354.930 ; gain = 149.262 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing -Phase 11 Post-Route Event Processing | Checksum: 6f450aed +Phase 11 Post-Route Event Processing | Checksum: 118a89fd7 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.578 ; gain = 143.781 -Ending Routing Task | Checksum: 6f450aed +Time (s): cpu = 00:00:07 ; elapsed = 00:00:37 . Memory (MB): peak = 2354.930 ; gain = 149.262 +Ending Routing Task | Checksum: 118a89fd7 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.578 ; gain = 143.781 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:37 . Memory (MB): peak = 2354.930 ; gain = 149.262 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 90 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:36 . Memory (MB): peak = 2354.578 ; gain = 175.285 +route_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:38 . Memory (MB): peak = 2354.930 ; gain = 177.746 INFO: [runtcl-4] Executing : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx Command: report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. @@ -681,7 +680,7 @@ INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt. report_methodology completed successfully -report_methodology: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2435.902 ; gain = 81.324 +report_methodology: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2436.516 ; gain = 81.586 INFO: [runtcl-4] Executing : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx Command: report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. @@ -701,16 +700,16 @@ INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU_bus_sk INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 2496.238 ; gain = 3.922 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2497.543 ; gain = 1.305 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2497.543 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2498.938 ; gain = 4.973 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2499.391 ; gain = 0.453 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2499.391 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.221 . Memory (MB): peak = 2497.543 ; gain = 0.000 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 2497.543 ; gain = 0.000 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2497.543 ; gain = 0.000 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2497.543 ; gain = 5.227 +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.230 . Memory (MB): peak = 2499.391 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 2499.391 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2499.391 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2499.391 ; gain = 5.426 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_routed.dcp' has been generated. Command: write_bitstream -force CPU.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' @@ -754,5 +753,5 @@ INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT dev INFO: [Common 17-83] Releasing license: Implementation 14 Infos, 13 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2966.875 ; gain = 469.332 -INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 14:30:07 2024... +write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2964.719 ; gain = 465.328 +INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 23:41:35 2024... diff --git a/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt index 1ff2a07..5aff5a0 100644 --- a/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 14:29:52 2024 +| Date : Sat Jul 13 23:41:19 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_bus_skew -warn_on_violation -file CPU_bus_skew_routed.rpt -pb CPU_bus_skew_routed.pb -rpx CPU_bus_skew_routed.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt index 6064672..efb197d 100644 --- a/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 14:29:52 2024 +| Date : Sat Jul 13 23:41:19 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_clock_utilization -file CPU_clock_utilization_routed.rpt | Design : CPU @@ -78,12 +78,12 @@ Table of Contents +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1517 | 1200 | 460 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3911 | 1500 | 1072 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | -| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2799 | 1200 | 937 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3610 | 1500 | 1055 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | -| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4277 | 1800 | 774 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 2018 | 950 | 601 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | +| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3068 | 1200 | 988 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4193 | 1500 | 1239 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2689 | 1200 | 887 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3944 | 1500 | 1126 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3420 | 1800 | 711 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 818 | 950 | 246 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts @@ -118,9 +118,9 @@ All Modules +----+-------+-------+-----------------------+ | | X0 | X1 | HORIZONTAL PROG DELAY | +----+-------+-------+-----------------------+ -| Y2 | 4277 | 2018 | 0 | -| Y1 | 2799 | 3610 | 0 | -| Y0 | 1517 | 3911 | 0 | +| Y2 | 3420 | 818 | 0 | +| Y1 | 2689 | 3944 | 0 | +| Y0 | 3068 | 4193 | 0 | +----+-------+-------+-----------------------+ @@ -153,7 +153,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 1517 | 0 | 1517 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 3068 | 0 | 3068 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -166,7 +166,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+ -| g0 | n/a | BUFG/O | None | 3911 | 0 | 3911 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 4193 | 0 | 4193 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | | g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | pll/inst/clkfbout_buf_phase_locked_loop | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered @@ -180,7 +180,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 2799 | 0 | 2799 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 2689 | 0 | 2689 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -193,7 +193,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 3610 | 0 | 3610 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 3944 | 0 | 3944 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -206,7 +206,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 4277 | 0 | 4277 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +| g0 | n/a | BUFG/O | None | 3420 | 0 | 3420 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads @@ -216,11 +216,11 @@ All Modules 13. Clock Region Cell Placement per Global Clock: Region X1Y2 ------------------------------------------------------------- -+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ -| g0 | n/a | BUFG/O | None | 2018 | 0 | 2018 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | -+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ ++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-------------------+ +| g0 | n/a | BUFG/O | None | 818 | 0 | 818 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | ++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts diff --git a/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt b/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt index e3759f5..421c6d5 100644 --- a/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 14:28:53 2024 +| Date : Sat Jul 13 23:40:17 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_control_sets -verbose -file CPU_control_sets_placed.rpt | Design : CPU @@ -60,10 +60,10 @@ Table of Contents +--------------+-----------------------+------------------------+-----------------+--------------+ | No | No | No | 0 | 0 | | No | No | Yes | 0 | 0 | -| No | Yes | No | 712 | 272 | +| No | Yes | No | 712 | 202 | | Yes | No | No | 0 | 0 | | Yes | No | Yes | 0 | 0 | -| Yes | Yes | No | 17420 | 7020 | +| Yes | Yes | No | 17420 | 6840 | +--------------+-----------------------+------------------------+-----------------+--------------+ @@ -73,553 +73,553 @@ Table of Contents +--------------------+------------------------------------------------------------+------------------------------+------------------+----------------+--------------+ | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | +--------------------+------------------------------------------------------------+------------------------------+------------------+----------------+--------------+ -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_10[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_28[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_47[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | execution/alu/E[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[25][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[12][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[3][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[5][31]_i_1_n_0 | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[14][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[10][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/p_0_in | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[9][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[27][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[2][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[11][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[4][31]_i_1_n_0 | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[7][31]_i_1_n_0 | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[26][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[17][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[22][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[24][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[31][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[13][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[16][31]_i_1_n_0 | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[18][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[21][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[28][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[30][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[8][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[19][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[23][31]_i_1_n_0 | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | instruction_decode/register_file/registers[29][31]_i_1_n_0 | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | write_back/E[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[1]_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[3]_1[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_22[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_8[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_11[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_9[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_17[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_18[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_24[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_27[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_13[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_30[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_19[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_14[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_28[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_6[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_7[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_8[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_21[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_25[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_38[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_32[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_3[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_10[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_23[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_4[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_16[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_23[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_1[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_16[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_11[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_17[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_25[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_12[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_26[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_15[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_22[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_15[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_19[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_20[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_21[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_29[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_14[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_3[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_0[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_24[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_7[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_9[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_33[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_20[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_34[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_36[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_13[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_35[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_37[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_4[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_6[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_18[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_5[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_31[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_12[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/E[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_0[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_1[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_2[0] | data_memory/reset | 7 | 32 | 4.57 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_19[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_23[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__14_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_22[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_25[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_26[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_27[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_4[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_28[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_4[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_5[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_0[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_0[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_2[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_5[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__26_1[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__9_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_1[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_54[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_13[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_0[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_14[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_15[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_21[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_5[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_0[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_2[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_4[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_0[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_10[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_24[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_11[0] | data_memory/reset | 7 | 32 | 4.57 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_6[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_16[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_2[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_20[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_2[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_0[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_17[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_0[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_4[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_3[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__17_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_18[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_4[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_2[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_0[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_4[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__30_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_0[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_4[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_6[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_1[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_1[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_5[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_1[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_1[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_5[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_5[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_7[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_4[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_4[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_5[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_0[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_5[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_1[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_3[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_4[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_1[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_1[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_3[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__29_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__30_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__27_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_3[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_1[0] | data_memory/reset | 20 | 32 | 1.60 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_3[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_2[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_3[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_8[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_28[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_4[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_7[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_23[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_9[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_10[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_11[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_11[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_12[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_22[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_13[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_14[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_14[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_24[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_30[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_29[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_5[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_7[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_18[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_2[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_19[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_16[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_17[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_15[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_13[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_2[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_31[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_4[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_27[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_5[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_8[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_6[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_25[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_10[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_12[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_20[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_0[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_26[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_6[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_21[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_24[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_25[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_25[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_4[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_20[0] | data_memory/reset | 15 | 32 | 2.13 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_8[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_26[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_17[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_27[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_30[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_28[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_22[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_10[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_12[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_38[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_28[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_15[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_21[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_31[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_5[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_20[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_22[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_34[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_27[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_41[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_6[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_11[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_33[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_18[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_20[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_19[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_29[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_32[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_23[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_16[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_24[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_17[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_10[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_39[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_14[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_1[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_7[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_15[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_0[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_16[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_11[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_35[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_26[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_36[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_40[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_9[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_21[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_13[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_9[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_14[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_13[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_37[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_2[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_18[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_23[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_42[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_43[0] | data_memory/reset | 20 | 32 | 1.60 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_29[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_4[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_9[0] | data_memory/reset | 7 | 32 | 4.57 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_0[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_10[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_8[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_29[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_27[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_3[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_8[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_6[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_1[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_17[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_3[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_16[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_30[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_0[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_13[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_23[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_11[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_10[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_7[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_3[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_12[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_32[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_18[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_14[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_31[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_30[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_31[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_5[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_15[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_33[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_11[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_20[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_4[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_24[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_25[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_34[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_7[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_35[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_6[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_5[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_28[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_12[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_13[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_32[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_36[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_37[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_38[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_39[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_4[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_2[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_22[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_40[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_41[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_51[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_48[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_6[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_7[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_44[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_3[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_2[0] | data_memory/reset | 20 | 32 | 1.60 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_45[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_4[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_49[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_5[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_8[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_1[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_8[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_4[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | instruction_decode/register_file/p_0_in | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[10][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[24][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[2][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[12][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[30][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[21][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[25][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[31][31]_i_1_n_0 | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[23][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[29][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[13][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[26][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[4][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[8][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[11][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[16][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[19][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[17][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[5][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[28][31]_i_1_n_0 | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[27][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[3][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[9][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[14][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[18][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[22][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | instruction_decode/register_file/registers[7][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | execution/alu/E[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_5[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_24[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_27[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_52[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_43[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_3[0] | data_memory/reset | 9 | 32 | 3.56 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_9[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_52[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_37[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_4[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_23[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_25[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_38[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_39[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_42[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_45[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_8[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_7[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_22[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_34[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_46[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_7[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_5[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_9[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_0[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_50[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_47[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_6[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_10[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_1[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_11[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_12[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_13[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_0[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_25[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_8[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_30[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_10[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_26[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_11[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_9[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_10[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_13[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_0[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_34[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_14[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_15[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_14[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_2[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_22[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_3[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_12[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_7[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_2[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_25[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_15[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_20[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_32[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_36[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_4[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_21[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_16[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_5[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_11[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_17[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_5[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_17[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_29[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_2[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_33[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_23[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_18[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_28[0] | data_memory/reset | 8 | 32 | 4.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_19[0] | data_memory/reset | 10 | 32 | 3.20 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_8[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_12[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_16[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_13[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_48[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_9[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_50[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_36[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_35[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_0[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_8[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_28[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_29[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_30[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_40[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_58[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_6[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_5[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_31[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_19[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_49[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_4[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_26[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_44[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_47[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_6[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_51[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_32[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_33[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_41[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_12[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_13[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_11[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_11[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_14[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_0[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_19[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_20[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_26[0] | data_memory/reset | 14 | 32 | 2.29 | | pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_6[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_6[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_4[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_31[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_9[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_18[0] | data_memory/reset | 9 | 32 | 3.56 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_24[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_1[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_35[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_12[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_10[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_18[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_21[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_15[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_22[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_8[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_13[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_9[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_2[0] | data_memory/reset | 12 | 32 | 2.67 | | pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_7[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_22[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_20[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_23[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_27[0] | data_memory/reset | 6 | 32 | 5.33 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_24[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_5[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_60[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_42[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_43[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_8[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_37[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_38[0] | data_memory/reset | 19 | 32 | 1.68 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_62[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_29[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_52[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_34[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_46[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_55[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_57[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_40[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_59[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_63[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_51[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_7[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_31[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_45[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_53[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_33[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_48[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_49[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_32[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_3[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_6[0] | data_memory/reset | 18 | 32 | 1.78 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_61[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_4[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_30[0] | data_memory/reset | 12 | 32 | 2.67 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_36[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_58[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_50[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_9[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_10[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_16[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_17[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_23[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_24[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_28[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_30[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_30[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_31[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_27[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_32[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_33[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_25[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_29[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_5[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_3[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_57[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_4[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_33[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_35[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_19[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_42[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_44[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_27[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_6[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_56[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_52[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_34[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_21[0] | data_memory/reset | 13 | 32 | 2.46 | | pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_44[0] | data_memory/reset | 15 | 32 | 2.13 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_56[0] | data_memory/reset | 11 | 32 | 2.91 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_35[0] | data_memory/reset | 16 | 32 | 2.00 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_27[0] | data_memory/reset | 17 | 32 | 1.88 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_39[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_41[0] | data_memory/reset | 14 | 32 | 2.29 | -| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_3[0] | data_memory/reset | 19 | 44 | 2.32 | -| pll/inst/clk_out1 | | execution/alu/IFID_PC_plus_4 | 30 | 67 | 2.23 | -| pll/inst/clk_out1 | | execution/alu/SR[0] | 61 | 160 | 2.62 | -| pll/inst/clk_out1 | | data_memory/reset | 181 | 485 | 2.68 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_27[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_30[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_7[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_23[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_10[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_35[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_29[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_36[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_22[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_37[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_13[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_38[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_39[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_25[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_31[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_46[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_14[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_47[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_15[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_20[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_48[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_54[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_11[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_40[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_5[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_24[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_32[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_5[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_53[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_55[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_36[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_16[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_17[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_45[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_41[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_49[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_50[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_2[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_34[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_28[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_43[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_51[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_63[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_9[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_8[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_60[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_7[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_62[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_6[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_59[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_61[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | write_back/E[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[1]_3[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[3]_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_13[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_24[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_5[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_7[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_11[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_16[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_40[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_5[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_30[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_6[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_6[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_11[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_23[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_12[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_32[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_41[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_15[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_12[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_29[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_11[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_13[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_14[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_15[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_26[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_16[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_8[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_14[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_20[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_9[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_13[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_9[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_10[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_17[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_25[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_6[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_10[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_31[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_17[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_9[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_22[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_27[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_28[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_8[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_10[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_12[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/E[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_26[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_19[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_21[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_2[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_4[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_0[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_0[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_0[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_11[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_0[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_0[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_4[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_12[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_6[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_14[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_0[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_17[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_18[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__9_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_5[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_10[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__14_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__17_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_2[0] | data_memory/reset | 17 | 32 | 1.88 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__26_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_13[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_16[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_3[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_15[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_2[0] | data_memory/reset | 7 | 32 | 4.57 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_22[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_1[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_0[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_20[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_23[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_24[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_25[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__27_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__30_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_4[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__29_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__30_2[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_28[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_9[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_27[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_2[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_2[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_4[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_5[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_3[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_2[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_4[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_5[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_8[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_3[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_4[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_1[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_6[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_3[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_5[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_1[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_5[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_3[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_2[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_19[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_23[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_1[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_11[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_5[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_20[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_12[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_10[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_26[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_9[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_4[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_2[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_1[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_10[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_30[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_13[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_8[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_25[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_18[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_15[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_24[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_0[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_11[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_3[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_9[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_27[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_6[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_0[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_11[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_12[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_13[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_14[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_14[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_17[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_19[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_22[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_29[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_0[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_16[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_28[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_6[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_12[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_31[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_3[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_4[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_5[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_1[0] | data_memory/reset | 19 | 32 | 1.68 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_10[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_15[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_16[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_17[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_18[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_2[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_1[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_13[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_20[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_7[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_8[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_21[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_14[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_7[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_14[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_17[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_23[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_29[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_3[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_25[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_32[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_22[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_34[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_20[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_9[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_25[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_27[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_30[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_4[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_21[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_5[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_7[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_28[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_8[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_0[0] | data_memory/reset | 18 | 32 | 1.78 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_38[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_35[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_3[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_23[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_1[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_5[0] | data_memory/reset | 10 | 32 | 3.20 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_11[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_24[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_37[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_6[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_22[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_8[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_11[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_10[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_12[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_36[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_33[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_13[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_15[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_14[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_13[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_16[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_17[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_1[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_19[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_18[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_2[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_6[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_20[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_9[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_31[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_24[0] | data_memory/reset | 16 | 32 | 2.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_4[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_12[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_15[0] | data_memory/reset | 8 | 32 | 4.00 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_10[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_16[0] | data_memory/reset | 9 | 32 | 3.56 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_21[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_32[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_33[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_35[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_24[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_31[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_36[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_37[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_25[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_26[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_29[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_34[0] | data_memory/reset | 14 | 32 | 2.29 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_21[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_23[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_28[0] | data_memory/reset | 11 | 32 | 2.91 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_22[0] | data_memory/reset | 13 | 32 | 2.46 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_38[0] | data_memory/reset | 15 | 32 | 2.13 | +| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_39[0] | data_memory/reset | 12 | 32 | 2.67 | +| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_3[0] | data_memory/reset | 15 | 44 | 2.93 | +| pll/inst/clk_out1 | | execution/alu/IFID_PC_plus_4 | 20 | 67 | 3.35 | +| pll/inst/clk_out1 | | execution/alu/SR[0] | 41 | 160 | 3.90 | +| pll/inst/clk_out1 | | data_memory/reset | 141 | 485 | 3.44 | +--------------------+------------------------------------------------------------+------------------------------+------------------+----------------+--------------+ diff --git a/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt b/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt index 98b3b84..b39c5a2 100644 --- a/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 14:28:18 2024 +| Date : Sat Jul 13 23:39:42 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt index 3b0184c..9971a5c 100644 --- a/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 14:29:40 2024 +| Date : Sat Jul 13 23:41:07 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt b/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt index a8dac69..0399a2d 100644 --- a/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 14:28:53 2024 +| Date : Sat Jul 13 23:40:16 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_io -file CPU_io_placed.rpt | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt index 0c74031..ddca496 100644 --- a/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 14:29:46 2024 +| Date : Sat Jul 13 23:41:13 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx | Design : CPU diff --git a/PipelineProcessor.runs/impl_1/CPU_opt.dcp b/PipelineProcessor.runs/impl_1/CPU_opt.dcp index f0fb8c0..bf4e1f3 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_opt.dcp and b/PipelineProcessor.runs/impl_1/CPU_opt.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_physopt.dcp b/PipelineProcessor.runs/impl_1/CPU_physopt.dcp index 6c4e89d..812ab7a 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_physopt.dcp and b/PipelineProcessor.runs/impl_1/CPU_physopt.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_placed.dcp b/PipelineProcessor.runs/impl_1/CPU_placed.dcp index ed25cb2..46e9daa 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_placed.dcp and b/PipelineProcessor.runs/impl_1/CPU_placed.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt index 65103f3..2422188 100644 --- a/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 14:29:51 2024 +| Date : Sat Jul 13 23:41:18 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx | Design : CPU @@ -30,10 +30,10 @@ Table of Contents ---------- +--------------------------+--------------+ -| Total On-Chip Power (W) | 0.189 | +| Total On-Chip Power (W) | 0.188 | | Design Power Budget (W) | Unspecified* | | Power Budget Margin (W) | NA | -| Dynamic (W) | 0.120 | +| Dynamic (W) | 0.119 | | Device Static (W) | 0.069 | | Effective TJA (C/W) | 2.8 | | Max Ambient (C) | 84.5 | @@ -52,19 +52,19 @@ Table of Contents +----------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +----------------+-----------+----------+-----------+-----------------+ -| Clocks | 0.016 | 5 | --- | --- | -| Slice Logic | 0.003 | 30286 | --- | --- | -| LUT as Logic | 0.003 | 8337 | 20800 | 40.08 | +| Clocks | 0.015 | 5 | --- | --- | +| Slice Logic | 0.003 | 30293 | --- | --- | +| LUT as Logic | 0.003 | 8344 | 20800 | 40.12 | | CARRY4 | <0.001 | 39 | 8150 | 0.48 | | Register | <0.001 | 18132 | 41600 | 43.59 | -| F7/F8 Muxes | <0.001 | 3461 | 32600 | 10.62 | +| F7/F8 Muxes | <0.001 | 3465 | 32600 | 10.63 | | Others | 0.000 | 12 | --- | --- | -| Signals | 0.002 | 21997 | --- | --- | +| Signals | 0.002 | 22010 | --- | --- | | PLL | 0.099 | 1 | 5 | 20.00 | | DSPs | <0.001 | 3 | 90 | 3.33 | | I/O | <0.001 | 15 | 250 | 6.00 | | Static Power | 0.069 | | | | -| Total | 0.189 | | | | +| Total | 0.188 | | | | +----------------+-----------+----------+-----------+-----------------+ @@ -74,7 +74,7 @@ Table of Contents +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ -| Vccint | 1.000 | 0.040 | 0.030 | 0.010 | NA | Unspecified | NA | +| Vccint | 1.000 | 0.038 | 0.029 | 0.010 | NA | Unspecified | NA | | Vccaux | 1.800 | 0.063 | 0.050 | 0.013 | NA | Unspecified | NA | | Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | @@ -145,10 +145,9 @@ Table of Contents +----------------------+-----------+ | Name | Power (W) | +----------------------+-----------+ -| CPU | 0.120 | -| data_memory | 0.014 | +| CPU | 0.119 | +| data_memory | 0.013 | | instruction_decode | 0.002 | -| register_file | 0.001 | | instruction_fetch | 0.001 | | pll | 0.100 | | inst | 0.100 | diff --git a/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb b/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb index 403d16c..bf66feb 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb and b/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_route_status.pb b/PipelineProcessor.runs/impl_1/CPU_route_status.pb index e8db5e4..ef01ef4 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_route_status.pb and b/PipelineProcessor.runs/impl_1/CPU_route_status.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_route_status.rpt b/PipelineProcessor.runs/impl_1/CPU_route_status.rpt index 3f1e04d..913823b 100644 --- a/PipelineProcessor.runs/impl_1/CPU_route_status.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_route_status.rpt @@ -1,11 +1,11 @@ Design Route Status : # nets : ------------------------------------------- : ----------- : - # of logical nets.......................... : 30511 : - # of nets not needing routing.......... : 8507 : - # of internally routed nets........ : 8507 : - # of routable nets..................... : 22004 : - # of fully routed nets............. : 22004 : + # of logical nets.......................... : 30518 : + # of nets not needing routing.......... : 8501 : + # of internally routed nets........ : 8501 : + # of routable nets..................... : 22017 : + # of fully routed nets............. : 22017 : # of nets with routing errors.......... : 0 : ------------------------------------------- : ----------- : diff --git a/PipelineProcessor.runs/impl_1/CPU_routed.dcp b/PipelineProcessor.runs/impl_1/CPU_routed.dcp index 21d8f9f..8a2948b 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_routed.dcp and b/PipelineProcessor.runs/impl_1/CPU_routed.dcp differ diff --git a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb index cf643ee..9db88e4 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb and b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt index 7bbd449..4f4daf3 100644 --- a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 14:29:52 2024 +| Date : Sat Jul 13 23:41:19 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -report_unconstrained -file CPU_timing_summary_routed.rpt -pb CPU_timing_summary_routed.pb -rpx CPU_timing_summary_routed.rpx -warn_on_violation | Design : CPU @@ -142,7 +142,7 @@ Table of Contents WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 2.679 0.000 0 35779 0.070 0.000 0 35779 3.000 0.000 0 18138 + 3.567 0.000 0 35779 0.055 0.000 0 35779 3.000 0.000 0 18138 All user specified timing constraints are met. @@ -168,7 +168,7 @@ hardware_clk {0.000 5.000} 10.000 100.000 Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- hardware_clk 3.000 0.000 0 1 - clk_out1_phase_locked_loop 2.679 0.000 0 35779 0.070 0.000 0 35779 9.500 0.000 0 18134 + clk_out1_phase_locked_loop 3.567 0.000 0 35779 0.055 0.000 0 35779 9.500 0.000 0 18134 clkfbout_phase_locked_loop 17.845 0.000 0 3 @@ -248,386 +248,27 @@ High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 5.000 From Clock: clk_out1_phase_locked_loop To Clock: clk_out1_phase_locked_loop -Setup : 0 Failing Endpoints, Worst Slack 2.679ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.070ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 3.567ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.055ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 9.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 2.679ns (required time - arrival time) - Source: write_back/WB_memory_read_data_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[24]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 17.177ns (logic 7.918ns (46.097%) route 9.259ns (53.903%)) - Logic Levels: 12 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.420ns - Clock Pessimism Removal (CPR): -0.505ns - Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 - SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q - net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] - SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O - net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] - SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O - net (fo=2, routed) 0.905 3.857 execution/result0__0_3 - SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O - net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] - DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) - 4.036 8.665 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 - DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 10.185 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 - SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 - SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3]) - 0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X12Y18 CARRY4 (Prop_carry4_CI_O[0]) - 0.219 12.085 r execution/alu/result0_inferred__11/i__carry__1/O[0] - net (fo=1, routed) 0.803 12.888 execution/alu/result0_inferred__11/i__carry__1_n_7 - SLICE_X8Y21 LUT4 (Prop_lut4_I3_O) 0.295 13.183 r execution/alu/MEM_ALU_result[24]_i_13/O - net (fo=1, routed) 0.646 13.829 execution/alu/MEM_ALU_result[24]_i_13_n_0 - SLICE_X5Y21 LUT6 (Prop_lut6_I5_O) 0.124 13.953 r execution/alu/MEM_ALU_result[24]_i_4/O - net (fo=1, routed) 0.680 14.633 execution/alu/MEM_ALU_result[24]_i_4_n_0 - SLICE_X8Y21 LUT6 (Prop_lut6_I3_O) 0.124 14.757 r execution/alu/MEM_ALU_result[24]_i_1/O - net (fo=1, routed) 0.000 14.757 memory_access/prev_ALU_result[24] - SLICE_X8Y21 FDRE r memory_access/MEM_ALU_result_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 20.000 20.000 r - R4 0.000 20.000 r hardware_clk (IN) - net (fo=0) 0.000 20.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.438 17.967 memory_access/clk_out1 - SLICE_X8Y21 FDRE r memory_access/MEM_ALU_result_reg[24]/C - clock pessimism -0.505 17.462 - clock uncertainty -0.108 17.354 - SLICE_X8Y21 FDRE (Setup_fdre_C_D) 0.081 17.435 memory_access/MEM_ALU_result_reg[24] - ------------------------------------------------------------------- - required time 17.435 - arrival time -14.757 - ------------------------------------------------------------------- - slack 2.679 - -Slack (MET) : 3.013ns (required time - arrival time) - Source: write_back/WB_memory_read_data_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[23]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.858ns (logic 7.909ns (46.917%) route 8.949ns (53.083%)) - Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) - Clock Path Skew: -0.051ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.966ns = ( 18.034 - 20.000 ) - Source Clock Delay (SCD): -2.420ns - Clock Pessimism Removal (CPR): -0.505ns - Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 - SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q - net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] - SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O - net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] - SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O - net (fo=2, routed) 0.905 3.857 execution/result0__0_3 - SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O - net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] - DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) - 4.036 8.665 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 - DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 10.185 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 - SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 - SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X12Y17 CARRY4 (Prop_carry4_CI_O[3]) - 0.315 12.064 r execution/alu/result0_inferred__11/i__carry__0/O[3] - net (fo=1, routed) 0.818 12.882 execution/alu/result0_inferred__11/i__carry__0_n_4 - SLICE_X7Y17 LUT4 (Prop_lut4_I3_O) 0.307 13.189 r execution/alu/MEM_ALU_result[23]_i_11/O - net (fo=1, routed) 0.701 13.891 execution/alu/MEM_ALU_result[23]_i_11_n_0 - SLICE_X3Y21 LUT6 (Prop_lut6_I5_O) 0.124 14.015 r execution/alu/MEM_ALU_result[23]_i_4/O - net (fo=1, routed) 0.299 14.313 execution/alu/MEM_ALU_result[23]_i_4_n_0 - SLICE_X7Y21 LUT6 (Prop_lut6_I3_O) 0.124 14.437 r execution/alu/MEM_ALU_result[23]_i_1/O - net (fo=1, routed) 0.000 14.437 memory_access/prev_ALU_result[23] - SLICE_X7Y21 FDRE r memory_access/MEM_ALU_result_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 20.000 20.000 r - R4 0.000 20.000 r hardware_clk (IN) - net (fo=0) 0.000 20.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.505 18.034 memory_access/clk_out1 - SLICE_X7Y21 FDRE r memory_access/MEM_ALU_result_reg[23]/C - clock pessimism -0.505 17.529 - clock uncertainty -0.108 17.421 - SLICE_X7Y21 FDRE (Setup_fdre_C_D) 0.029 17.450 memory_access/MEM_ALU_result_reg[23] - ------------------------------------------------------------------- - required time 17.450 - arrival time -14.437 - ------------------------------------------------------------------- - slack 3.013 - -Slack (MET) : 3.041ns (required time - arrival time) - Source: write_back/WB_memory_read_data_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[28]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.830ns (logic 8.035ns (47.741%) route 8.795ns (52.259%)) - Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=2) - Clock Path Skew: -0.050ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.965ns = ( 18.035 - 20.000 ) - Source Clock Delay (SCD): -2.420ns - Clock Pessimism Removal (CPR): -0.505ns - Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 - SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q - net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] - SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O - net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] - SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O - net (fo=2, routed) 0.905 3.857 execution/result0__0_3 - SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O - net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] - DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) - 4.036 8.665 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 - DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 10.185 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 - SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 - SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3]) - 0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X12Y18 CARRY4 (Prop_carry4_CI_CO[3]) - 0.117 11.983 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.983 execution/alu/result0_inferred__11/i__carry__1_n_0 - SLICE_X12Y19 CARRY4 (Prop_carry4_CI_O[0]) - 0.219 12.202 r execution/alu/result0_inferred__11/i__carry__2/O[0] - net (fo=1, routed) 0.835 13.037 execution/alu/result0_inferred__11/i__carry__2_n_7 - SLICE_X6Y19 LUT4 (Prop_lut4_I3_O) 0.295 13.332 r execution/alu/MEM_ALU_result[28]_i_12/O - net (fo=1, routed) 0.427 13.759 execution/alu/MEM_ALU_result[28]_i_12_n_0 - SLICE_X5Y20 LUT5 (Prop_lut5_I4_O) 0.124 13.883 r execution/alu/MEM_ALU_result[28]_i_4/O - net (fo=1, routed) 0.403 14.286 execution/alu/MEM_ALU_result[28]_i_4_n_0 - SLICE_X5Y20 LUT6 (Prop_lut6_I3_O) 0.124 14.410 r execution/alu/MEM_ALU_result[28]_i_1/O - net (fo=1, routed) 0.000 14.410 memory_access/prev_ALU_result[28] - SLICE_X5Y20 FDRE r memory_access/MEM_ALU_result_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 20.000 20.000 r - R4 0.000 20.000 r hardware_clk (IN) - net (fo=0) 0.000 20.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.506 18.035 memory_access/clk_out1 - SLICE_X5Y20 FDRE r memory_access/MEM_ALU_result_reg[28]/C - clock pessimism -0.505 17.530 - clock uncertainty -0.108 17.422 - SLICE_X5Y20 FDRE (Setup_fdre_C_D) 0.029 17.451 memory_access/MEM_ALU_result_reg[28] - ------------------------------------------------------------------- - required time 17.451 - arrival time -14.410 - ------------------------------------------------------------------- - slack 3.041 - -Slack (MET) : 3.055ns (required time - arrival time) - Source: write_back/WB_memory_read_data_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[29]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.817ns (logic 8.150ns (48.463%) route 8.667ns (51.537%)) - Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=2) - Clock Path Skew: -0.050ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.965ns = ( 18.035 - 20.000 ) - Source Clock Delay (SCD): -2.420ns - Clock Pessimism Removal (CPR): -0.505ns - Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 - SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q - net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] - SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O - net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] - SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O - net (fo=2, routed) 0.905 3.857 execution/result0__0_3 - SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O - net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] - DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) - 4.036 8.665 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 - DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 10.185 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 - SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 - SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3]) - 0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X12Y18 CARRY4 (Prop_carry4_CI_CO[3]) - 0.117 11.983 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.983 execution/alu/result0_inferred__11/i__carry__1_n_0 - SLICE_X12Y19 CARRY4 (Prop_carry4_CI_O[1]) - 0.323 12.306 r execution/alu/result0_inferred__11/i__carry__2/O[1] - net (fo=1, routed) 0.600 12.905 execution/alu/result0_inferred__11/i__carry__2_n_6 - SLICE_X6Y19 LUT4 (Prop_lut4_I3_O) 0.306 13.211 r execution/alu/MEM_ALU_result[29]_i_10/O - net (fo=1, routed) 0.453 13.664 execution/alu/MEM_ALU_result[29]_i_10_n_0 - SLICE_X6Y21 LUT5 (Prop_lut5_I4_O) 0.124 13.788 r execution/alu/MEM_ALU_result[29]_i_4/O - net (fo=1, routed) 0.484 14.273 execution/alu/MEM_ALU_result[29]_i_4_n_0 - SLICE_X7Y20 LUT6 (Prop_lut6_I3_O) 0.124 14.397 r execution/alu/MEM_ALU_result[29]_i_1/O - net (fo=1, routed) 0.000 14.397 memory_access/prev_ALU_result[29] - SLICE_X7Y20 FDRE r memory_access/MEM_ALU_result_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 20.000 20.000 r - R4 0.000 20.000 r hardware_clk (IN) - net (fo=0) 0.000 20.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.506 18.035 memory_access/clk_out1 - SLICE_X7Y20 FDRE r memory_access/MEM_ALU_result_reg[29]/C - clock pessimism -0.505 17.530 - clock uncertainty -0.108 17.422 - SLICE_X7Y20 FDRE (Setup_fdre_C_D) 0.029 17.451 memory_access/MEM_ALU_result_reg[29] - ------------------------------------------------------------------- - required time 17.451 - arrival time -14.397 - ------------------------------------------------------------------- - slack 3.055 - -Slack (MET) : 3.160ns (required time - arrival time) - Source: write_back/WB_memory_read_data_reg[1]/C +Slack (MET) : 3.567ns (required time - arrival time) + Source: write_back/WB_WB_source_reg/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[30]_rep/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.600ns (logic 7.937ns (47.813%) route 8.663ns (52.187%)) + Data Path Delay: 16.219ns (logic 8.344ns (51.446%) route 7.875ns (48.554%)) Logic Levels: 12 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=2) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.032ns = ( 17.968 - 20.000 ) - Source Clock Delay (SCD): -2.420ns + Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.956ns = ( 18.044 - 20.000 ) + Source Clock Delay (SCD): -2.421ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -646,42 +287,42 @@ Slack (MET) : 3.160ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 - SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C + net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 + SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q - net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] - SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O - net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] - SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O - net (fo=2, routed) 0.905 3.857 execution/result0__0_3 - SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O - net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] - DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) - 4.036 8.665 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 - DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 10.185 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 - SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 - SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3]) - 0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X12Y18 CARRY4 (Prop_carry4_CI_CO[3]) - 0.117 11.983 r execution/alu/result0_inferred__11/i__carry__1/CO[3] - net (fo=1, routed) 0.000 11.983 execution/alu/result0_inferred__11/i__carry__1_n_0 - SLICE_X12Y19 CARRY4 (Prop_carry4_CI_O[2]) - 0.239 12.222 r execution/alu/result0_inferred__11/i__carry__2/O[2] - net (fo=1, routed) 0.671 12.892 execution/alu/result0_inferred__11/i__carry__2_n_5 - SLICE_X10Y21 LUT4 (Prop_lut4_I3_O) 0.301 13.193 r execution/alu/MEM_ALU_result[30]_i_3/O - net (fo=2, routed) 0.294 13.487 execution/alu/MEM_ALU_result[30]_i_3_n_0 - SLICE_X10Y21 LUT6 (Prop_lut6_I2_O) 0.124 13.611 r execution/alu/MEM_ALU_result[30]_rep_i_1/O - net (fo=1, routed) 0.568 14.180 memory_access/MEM_ALU_result_reg[30]_rep_29 - SLICE_X10Y21 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/D + SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q + net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source + SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O + net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] + SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O + net (fo=2, routed) 0.560 2.844 execution/result0__0_4 + SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O + net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) + 4.240 8.261 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.781 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.363 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.363 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y37 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.477 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.477 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X11Y38 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 11.716 r execution/alu/result0_inferred__11/i__carry__2/O[2] + net (fo=1, routed) 0.667 12.383 execution/alu/result0_inferred__11/i__carry__2_n_5 + SLICE_X5Y38 LUT4 (Prop_lut4_I3_O) 0.302 12.685 r execution/alu/MEM_ALU_result[30]_i_3/O + net (fo=2, routed) 0.506 13.191 execution/alu/MEM_ALU_result[30]_i_3_n_0 + SLICE_X4Y38 LUT6 (Prop_lut6_I2_O) 0.124 13.315 r execution/alu/MEM_ALU_result[30]_rep_i_1/O + net (fo=1, routed) 0.483 13.798 memory_access/MEM_ALU_result_reg[30]_rep_29 + SLICE_X5Y40 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -694,30 +335,116 @@ Slack (MET) : 3.160ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.439 17.968 memory_access/clk_out1 - SLICE_X10Y21 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/C - clock pessimism -0.505 17.463 - clock uncertainty -0.108 17.355 - SLICE_X10Y21 FDRE (Setup_fdre_C_D) -0.016 17.339 memory_access/MEM_ALU_result_reg[30]_rep + net (fo=18132, routed) 1.515 18.044 memory_access/clk_out1 + SLICE_X5Y40 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/C + clock pessimism -0.505 17.539 + clock uncertainty -0.108 17.431 + SLICE_X5Y40 FDRE (Setup_fdre_C_D) -0.067 17.364 memory_access/MEM_ALU_result_reg[30]_rep ------------------------------------------------------------------- - required time 17.339 - arrival time -14.180 + required time 17.364 + arrival time -13.798 ------------------------------------------------------------------- - slack 3.160 + slack 3.567 -Slack (MET) : 3.264ns (required time - arrival time) - Source: write_back/WB_memory_read_data_reg[1]/C +Slack (MET) : 3.609ns (required time - arrival time) + Source: write_back/WB_WB_source_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: memory_access/MEM_ALU_result_reg[23]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 16.276ns (logic 8.318ns (51.107%) route 7.958ns (48.893%)) + Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) + Clock Path Skew: -0.039ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.955ns = ( 18.045 - 20.000 ) + Source Clock Delay (SCD): -2.421ns + Clock Pessimism Removal (CPR): -0.505ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 + SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q + net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source + SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O + net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] + SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O + net (fo=2, routed) 0.560 2.844 execution/result0__0_4 + SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O + net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) + 4.240 8.261 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.781 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 11.562 r execution/alu/result0_inferred__11/i__carry__0/O[3] + net (fo=1, routed) 0.559 12.121 execution/alu/result0_inferred__11/i__carry__0_n_4 + SLICE_X6Y36 LUT4 (Prop_lut4_I3_O) 0.306 12.427 r execution/alu/MEM_ALU_result[23]_i_11/O + net (fo=1, routed) 0.722 13.150 execution/alu/MEM_ALU_result[23]_i_11_n_0 + SLICE_X3Y40 LUT6 (Prop_lut6_I5_O) 0.124 13.274 r execution/alu/MEM_ALU_result[23]_i_4/O + net (fo=1, routed) 0.456 13.730 execution/alu/MEM_ALU_result[23]_i_4_n_0 + SLICE_X5Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.854 r execution/alu/MEM_ALU_result[23]_i_1/O + net (fo=1, routed) 0.000 13.854 memory_access/prev_ALU_result[23] + SLICE_X5Y42 FDRE r memory_access/MEM_ALU_result_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 20.000 20.000 r + R4 0.000 20.000 r hardware_clk (IN) + net (fo=0) 0.000 20.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.516 18.045 memory_access/clk_out1 + SLICE_X5Y42 FDRE r memory_access/MEM_ALU_result_reg[23]/C + clock pessimism -0.505 17.540 + clock uncertainty -0.108 17.432 + SLICE_X5Y42 FDRE (Setup_fdre_C_D) 0.031 17.463 memory_access/MEM_ALU_result_reg[23] + ------------------------------------------------------------------- + required time 17.463 + arrival time -13.854 + ------------------------------------------------------------------- + slack 3.609 + +Slack (MET) : 3.610ns (required time - arrival time) + Source: write_back/WB_WB_source_reg/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[25]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.608ns (logic 8.033ns (48.367%) route 8.575ns (51.633%)) + Data Path Delay: 16.271ns (logic 8.450ns (51.933%) route 7.821ns (48.067%)) Logic Levels: 12 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) - Clock Path Skew: -0.051ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.966ns = ( 18.034 - 20.000 ) - Source Clock Delay (SCD): -2.420ns + Clock Path Skew: -0.041ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.957ns = ( 18.043 - 20.000 ) + Source Clock Delay (SCD): -2.421ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -736,41 +463,41 @@ Slack (MET) : 3.264ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 - SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C + net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 + SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q - net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] - SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O - net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] - SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O - net (fo=2, routed) 0.905 3.857 execution/result0__0_3 - SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O - net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] - DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) - 4.036 8.665 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 - DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 10.185 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 - SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 - SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3]) - 0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3] - net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0 - SLICE_X12Y18 CARRY4 (Prop_carry4_CI_O[1]) - 0.323 12.189 r execution/alu/result0_inferred__11/i__carry__1/O[1] - net (fo=1, routed) 0.725 12.914 execution/alu/result0_inferred__11/i__carry__1_n_6 - SLICE_X7Y20 LUT4 (Prop_lut4_I3_O) 0.306 13.220 r execution/alu/MEM_ALU_result[25]_i_11/O - net (fo=1, routed) 0.436 13.656 execution/alu/MEM_ALU_result[25]_i_11_n_0 - SLICE_X4Y21 LUT6 (Prop_lut6_I5_O) 0.124 13.780 r execution/alu/MEM_ALU_result[25]_i_4/O - net (fo=1, routed) 0.284 14.064 execution/alu/MEM_ALU_result[25]_i_4_n_0 - SLICE_X7Y21 LUT6 (Prop_lut6_I3_O) 0.124 14.188 r execution/alu/MEM_ALU_result[25]_i_1/O - net (fo=1, routed) 0.000 14.188 memory_access/prev_ALU_result[25] - SLICE_X7Y21 FDRE r memory_access/MEM_ALU_result_reg[25]/D + SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q + net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source + SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O + net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] + SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O + net (fo=2, routed) 0.560 2.844 execution/result0__0_4 + SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O + net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) + 4.240 8.261 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.781 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.363 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.363 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y37 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 11.697 r execution/alu/result0_inferred__11/i__carry__1/O[1] + net (fo=1, routed) 0.683 12.380 execution/alu/result0_inferred__11/i__carry__1_n_6 + SLICE_X5Y37 LUT4 (Prop_lut4_I3_O) 0.303 12.683 r execution/alu/MEM_ALU_result[25]_i_11/O + net (fo=1, routed) 0.469 13.153 execution/alu/MEM_ALU_result[25]_i_11_n_0 + SLICE_X2Y39 LUT6 (Prop_lut6_I5_O) 0.124 13.277 r execution/alu/MEM_ALU_result[25]_i_4/O + net (fo=1, routed) 0.449 13.726 execution/alu/MEM_ALU_result[25]_i_4_n_0 + SLICE_X4Y38 LUT6 (Prop_lut6_I3_O) 0.124 13.850 r execution/alu/MEM_ALU_result[25]_i_1/O + net (fo=1, routed) 0.000 13.850 memory_access/prev_ALU_result[25] + SLICE_X4Y38 FDRE r memory_access/MEM_ALU_result_reg[25]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -783,30 +510,30 @@ Slack (MET) : 3.264ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.505 18.034 memory_access/clk_out1 - SLICE_X7Y21 FDRE r memory_access/MEM_ALU_result_reg[25]/C - clock pessimism -0.505 17.529 - clock uncertainty -0.108 17.421 - SLICE_X7Y21 FDRE (Setup_fdre_C_D) 0.031 17.452 memory_access/MEM_ALU_result_reg[25] + net (fo=18132, routed) 1.514 18.043 memory_access/clk_out1 + SLICE_X4Y38 FDRE r memory_access/MEM_ALU_result_reg[25]/C + clock pessimism -0.505 17.538 + clock uncertainty -0.108 17.430 + SLICE_X4Y38 FDRE (Setup_fdre_C_D) 0.029 17.459 memory_access/MEM_ALU_result_reg[25] ------------------------------------------------------------------- - required time 17.452 - arrival time -14.188 + required time 17.459 + arrival time -13.850 ------------------------------------------------------------------- - slack 3.264 + slack 3.610 -Slack (MET) : 3.380ns (required time - arrival time) - Source: write_back/WB_memory_read_data_reg[1]/C +Slack (MET) : 3.670ns (required time - arrival time) + Source: write_back/WB_WB_source_reg/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[22]/D + Destination: memory_access/MEM_ALU_result_reg[29]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.542ns (logic 7.827ns (47.315%) route 8.715ns (52.685%)) - Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) - Clock Path Skew: -0.048ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.963ns = ( 18.037 - 20.000 ) - Source Clock Delay (SCD): -2.420ns + Data Path Delay: 16.213ns (logic 8.564ns (52.823%) route 7.649ns (47.177%)) + Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=2) + Clock Path Skew: -0.041ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.957ns = ( 18.043 - 20.000 ) + Source Clock Delay (SCD): -2.421ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -825,38 +552,44 @@ Slack (MET) : 3.380ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 - SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C + net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 + SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q - net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] - SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O - net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] - SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O - net (fo=2, routed) 0.905 3.857 execution/result0__0_3 - SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O - net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] - DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) - 4.036 8.665 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 - DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 10.185 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 - SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 - SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X12Y17 CARRY4 (Prop_carry4_CI_O[2]) - 0.239 11.988 r execution/alu/result0_inferred__11/i__carry__0/O[2] - net (fo=1, routed) 0.579 12.567 execution/alu/result0_inferred__11/i__carry__0_n_5 - SLICE_X7Y17 LUT4 (Prop_lut4_I3_O) 0.301 12.868 r execution/alu/MEM_ALU_result[22]_i_12/O - net (fo=1, routed) 0.565 13.433 execution/alu/MEM_ALU_result[22]_i_12_n_0 - SLICE_X1Y18 LUT6 (Prop_lut6_I5_O) 0.124 13.557 r execution/alu/MEM_ALU_result[22]_i_4/O - net (fo=1, routed) 0.441 13.998 execution/alu/MEM_ALU_result[22]_i_4_n_0 - SLICE_X2Y20 LUT6 (Prop_lut6_I3_O) 0.124 14.122 r execution/alu/MEM_ALU_result[22]_i_1/O - net (fo=1, routed) 0.000 14.122 memory_access/prev_ALU_result[22] - SLICE_X2Y20 FDRE r memory_access/MEM_ALU_result_reg[22]/D + SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q + net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source + SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O + net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] + SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O + net (fo=2, routed) 0.560 2.844 execution/result0__0_4 + SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O + net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) + 4.240 8.261 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.781 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.363 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.363 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y37 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.477 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.477 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X11Y38 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 11.811 r execution/alu/result0_inferred__11/i__carry__2/O[1] + net (fo=1, routed) 0.671 12.482 execution/alu/result0_inferred__11/i__carry__2_n_6 + SLICE_X5Y38 LUT4 (Prop_lut4_I3_O) 0.303 12.785 r execution/alu/MEM_ALU_result[29]_i_10/O + net (fo=1, routed) 0.438 13.222 execution/alu/MEM_ALU_result[29]_i_10_n_0 + SLICE_X3Y39 LUT5 (Prop_lut5_I4_O) 0.124 13.346 r execution/alu/MEM_ALU_result[29]_i_4/O + net (fo=1, routed) 0.321 13.667 execution/alu/MEM_ALU_result[29]_i_4_n_0 + SLICE_X4Y38 LUT6 (Prop_lut6_I3_O) 0.124 13.791 r execution/alu/MEM_ALU_result[29]_i_1/O + net (fo=1, routed) 0.000 13.791 memory_access/prev_ALU_result[29] + SLICE_X4Y38 FDRE r memory_access/MEM_ALU_result_reg[29]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -869,30 +602,209 @@ Slack (MET) : 3.380ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.508 18.037 memory_access/clk_out1 - SLICE_X2Y20 FDRE r memory_access/MEM_ALU_result_reg[22]/C - clock pessimism -0.505 17.532 - clock uncertainty -0.108 17.424 - SLICE_X2Y20 FDRE (Setup_fdre_C_D) 0.077 17.501 memory_access/MEM_ALU_result_reg[22] + net (fo=18132, routed) 1.514 18.043 memory_access/clk_out1 + SLICE_X4Y38 FDRE r memory_access/MEM_ALU_result_reg[29]/C + clock pessimism -0.505 17.538 + clock uncertainty -0.108 17.430 + SLICE_X4Y38 FDRE (Setup_fdre_C_D) 0.031 17.461 memory_access/MEM_ALU_result_reg[29] ------------------------------------------------------------------- - required time 17.501 - arrival time -14.122 + required time 17.461 + arrival time -13.791 ------------------------------------------------------------------- - slack 3.380 + slack 3.670 -Slack (MET) : 3.438ns (required time - arrival time) - Source: write_back/WB_memory_read_data_reg[1]/C +Slack (MET) : 3.737ns (required time - arrival time) + Source: write_back/WB_WB_source_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: memory_access/MEM_ALU_result_reg[31]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 16.148ns (logic 8.546ns (52.923%) route 7.602ns (47.077%)) + Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT5=1 LUT6=3) + Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.956ns = ( 18.044 - 20.000 ) + Source Clock Delay (SCD): -2.421ns + Clock Pessimism Removal (CPR): -0.505ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 + SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q + net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source + SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O + net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] + SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O + net (fo=2, routed) 0.560 2.844 execution/result0__0_4 + SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O + net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) + 4.240 8.261 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.781 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.363 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.363 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y37 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.477 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.477 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X11Y38 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 11.790 r execution/alu/result0_inferred__11/i__carry__2/O[3] + net (fo=1, routed) 0.570 12.361 execution/alu/result0_inferred__11/i__carry__2_n_4 + SLICE_X6Y39 LUT5 (Prop_lut5_I0_O) 0.306 12.667 r execution/alu/MEM_ALU_result[31]_i_16/O + net (fo=1, routed) 0.409 13.076 execution/alu/MEM_ALU_result[31]_i_16_n_0 + SLICE_X4Y39 LUT6 (Prop_lut6_I2_O) 0.124 13.200 r execution/alu/MEM_ALU_result[31]_i_5/O + net (fo=1, routed) 0.403 13.603 execution/alu/MEM_ALU_result[31]_i_5_n_0 + SLICE_X5Y40 LUT6 (Prop_lut6_I3_O) 0.124 13.727 r execution/alu/MEM_ALU_result[31]_i_1/O + net (fo=1, routed) 0.000 13.727 memory_access/prev_ALU_result[31] + SLICE_X5Y40 FDRE r memory_access/MEM_ALU_result_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 20.000 20.000 r + R4 0.000 20.000 r hardware_clk (IN) + net (fo=0) 0.000 20.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.515 18.044 memory_access/clk_out1 + SLICE_X5Y40 FDRE r memory_access/MEM_ALU_result_reg[31]/C + clock pessimism -0.505 17.539 + clock uncertainty -0.108 17.431 + SLICE_X5Y40 FDRE (Setup_fdre_C_D) 0.032 17.463 memory_access/MEM_ALU_result_reg[31] + ------------------------------------------------------------------- + required time 17.463 + arrival time -13.727 + ------------------------------------------------------------------- + slack 3.737 + +Slack (MET) : 3.792ns (required time - arrival time) + Source: write_back/WB_WB_source_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: memory_access/MEM_ALU_result_reg[27]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 16.142ns (logic 8.308ns (51.469%) route 7.834ns (48.531%)) + Logic Levels: 11 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=2 LUT6=3) + Clock Path Skew: -0.036ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.952ns = ( 18.048 - 20.000 ) + Source Clock Delay (SCD): -2.421ns + Clock Pessimism Removal (CPR): -0.505ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 + SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q + net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source + SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O + net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] + SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O + net (fo=2, routed) 0.560 2.844 execution/result0__0_4 + SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O + net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) + 4.240 8.261 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.781 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.363 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.363 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y37 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 11.676 r execution/alu/result0_inferred__11/i__carry__1/O[3] + net (fo=1, routed) 1.057 12.733 execution/alu/result0_inferred__11/i__carry__1_n_4 + SLICE_X2Y40 LUT6 (Prop_lut6_I3_O) 0.306 13.039 r execution/alu/MEM_ALU_result[27]_i_4/O + net (fo=1, routed) 0.557 13.596 execution/alu/MEM_ALU_result[27]_i_4_n_0 + SLICE_X2Y43 LUT6 (Prop_lut6_I3_O) 0.124 13.720 r execution/alu/MEM_ALU_result[27]_i_1/O + net (fo=1, routed) 0.000 13.720 memory_access/prev_ALU_result[27] + SLICE_X2Y43 FDRE r memory_access/MEM_ALU_result_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 20.000 20.000 r + R4 0.000 20.000 r hardware_clk (IN) + net (fo=0) 0.000 20.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.519 18.048 memory_access/clk_out1 + SLICE_X2Y43 FDRE r memory_access/MEM_ALU_result_reg[27]/C + clock pessimism -0.505 17.543 + clock uncertainty -0.108 17.435 + SLICE_X2Y43 FDRE (Setup_fdre_C_D) 0.077 17.512 memory_access/MEM_ALU_result_reg[27] + ------------------------------------------------------------------- + required time 17.512 + arrival time -13.720 + ------------------------------------------------------------------- + slack 3.792 + +Slack (MET) : 3.795ns (required time - arrival time) + Source: write_back/WB_WB_source_reg/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: memory_access/MEM_ALU_result_reg[21]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.488ns (logic 7.916ns (48.011%) route 8.572ns (51.989%)) + Data Path Delay: 16.135ns (logic 8.336ns (51.663%) route 7.799ns (48.337%)) Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) - Clock Path Skew: -0.048ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.963ns = ( 18.037 - 20.000 ) - Source Clock Delay (SCD): -2.420ns + Clock Path Skew: -0.039ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.955ns = ( 18.045 - 20.000 ) + Source Clock Delay (SCD): -2.421ns Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -911,38 +823,38 @@ Slack (MET) : 3.438ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 - SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C + net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 + SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q - net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] - SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O - net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] - SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O - net (fo=2, routed) 0.905 3.857 execution/result0__0_3 - SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O - net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] - DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47]) - 4.036 8.665 r execution/alu/result0__0/PCOUT[47] - net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106 - DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) - 1.518 10.185 r execution/alu/result0__1/P[0] - net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105 - SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O - net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0 - SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3] - net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0 - SLICE_X12Y17 CARRY4 (Prop_carry4_CI_O[1]) - 0.323 12.072 r execution/alu/result0_inferred__11/i__carry__0/O[1] - net (fo=1, routed) 0.697 12.769 execution/alu/result0_inferred__11/i__carry__0_n_6 - SLICE_X5Y17 LUT4 (Prop_lut4_I1_O) 0.306 13.075 r execution/alu/MEM_ALU_result[21]_i_12/O - net (fo=1, routed) 0.449 13.524 execution/alu/MEM_ALU_result[21]_i_12_n_0 - SLICE_X1Y19 LUT6 (Prop_lut6_I5_O) 0.124 13.648 r execution/alu/MEM_ALU_result[21]_i_4/O - net (fo=1, routed) 0.295 13.943 execution/alu/MEM_ALU_result[21]_i_4_n_0 - SLICE_X2Y19 LUT6 (Prop_lut6_I3_O) 0.124 14.067 r execution/alu/MEM_ALU_result[21]_i_1/O - net (fo=1, routed) 0.000 14.067 memory_access/prev_ALU_result[21] - SLICE_X2Y19 FDRE r memory_access/MEM_ALU_result_reg[21]/D + SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q + net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source + SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O + net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] + SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O + net (fo=2, routed) 0.560 2.844 execution/result0__0_4 + SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O + net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) + 4.240 8.261 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.781 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[1]) + 0.334 11.583 r execution/alu/result0_inferred__11/i__carry__0/O[1] + net (fo=1, routed) 0.691 12.274 execution/alu/result0_inferred__11/i__carry__0_n_6 + SLICE_X3Y37 LUT4 (Prop_lut4_I1_O) 0.303 12.577 r execution/alu/MEM_ALU_result[21]_i_12/O + net (fo=1, routed) 0.433 13.010 execution/alu/MEM_ALU_result[21]_i_12_n_0 + SLICE_X0Y38 LUT6 (Prop_lut6_I5_O) 0.124 13.134 r execution/alu/MEM_ALU_result[21]_i_4/O + net (fo=1, routed) 0.456 13.590 execution/alu/MEM_ALU_result[21]_i_4_n_0 + SLICE_X2Y38 LUT6 (Prop_lut6_I3_O) 0.124 13.714 r execution/alu/MEM_ALU_result[21]_i_1/O + net (fo=1, routed) 0.000 13.714 memory_access/prev_ALU_result[21] + SLICE_X2Y38 FDRE r memory_access/MEM_ALU_result_reg[21]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -955,106 +867,31 @@ Slack (MET) : 3.438ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.508 18.037 memory_access/clk_out1 - SLICE_X2Y19 FDRE r memory_access/MEM_ALU_result_reg[21]/C - clock pessimism -0.505 17.532 - clock uncertainty -0.108 17.424 - SLICE_X2Y19 FDRE (Setup_fdre_C_D) 0.081 17.505 memory_access/MEM_ALU_result_reg[21] - ------------------------------------------------------------------- - required time 17.505 - arrival time -14.067 - ------------------------------------------------------------------- - slack 3.438 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: write_back/WB_memory_read_data_reg[1]/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[3]_rep__18/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.324ns (logic 5.041ns (30.880%) route 11.283ns (69.120%)) - Logic Levels: 7 (DSP48E1=1 LUT3=2 LUT6=4) - Clock Path Skew: -0.040ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.034ns = ( 17.966 - 20.000 ) - Source Clock Delay (SCD): -2.420ns - Clock Pessimism Removal (CPR): -0.427ns - Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 - SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q - net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] - SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O - net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] - SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O - net (fo=2, routed) 0.905 3.857 execution/result0__0_3 - SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O - net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] - DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_P[3]) - 3.841 8.470 r execution/alu/result0__0/P[3] - net (fo=1, routed) 0.752 9.223 execution/alu/result0__0_n_102 - SLICE_X10Y16 LUT6 (Prop_lut6_I1_O) 0.124 9.347 r execution/alu/MEM_ALU_result[3]_i_10/O - net (fo=1, routed) 0.452 9.799 execution/alu/MEM_ALU_result[3]_i_10_n_0 - SLICE_X9Y18 LUT6 (Prop_lut6_I5_O) 0.124 9.923 r execution/alu/MEM_ALU_result[3]_i_4/O - net (fo=34, routed) 3.289 13.212 execution/alu/MEM_ALU_result[3]_i_4_n_0 - SLICE_X43Y99 LUT6 (Prop_lut6_I3_O) 0.124 13.336 r execution/alu/MEM_ALU_result[3]_rep_i_1__18/O - net (fo=1, routed) 0.568 13.904 memory_access/MEM_ALU_result_reg[3]_rep__18_6 - SLICE_X43Y99 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__18/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 20.000 20.000 r - R4 0.000 20.000 r hardware_clk (IN) - net (fo=0) 0.000 20.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.438 17.966 memory_access/clk_out1 - SLICE_X43Y99 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__18/C - clock pessimism -0.427 17.540 + net (fo=18132, routed) 1.516 18.045 memory_access/clk_out1 + SLICE_X2Y38 FDRE r memory_access/MEM_ALU_result_reg[21]/C + clock pessimism -0.505 17.540 clock uncertainty -0.108 17.432 - SLICE_X43Y99 FDRE (Setup_fdre_C_D) -0.062 17.370 memory_access/MEM_ALU_result_reg[3]_rep__18 + SLICE_X2Y38 FDRE (Setup_fdre_C_D) 0.077 17.509 memory_access/MEM_ALU_result_reg[21] ------------------------------------------------------------------- - required time 17.370 - arrival time -13.904 + required time 17.509 + arrival time -13.714 ------------------------------------------------------------------- - slack 3.466 + slack 3.795 -Slack (MET) : 3.484ns (required time - arrival time) - Source: write_back/WB_memory_read_data_reg[1]/C +Slack (MET) : 3.828ns (required time - arrival time) + Source: write_back/WB_WB_source_reg/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: memory_access/MEM_ALU_result_reg[3]_rep__25/D + Destination: memory_access/MEM_ALU_result_reg[28]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 16.404ns (logic 5.041ns (30.729%) route 11.363ns (69.271%)) - Logic Levels: 7 (DSP48E1=1 LUT3=2 LUT6=4) - Clock Path Skew: 0.063ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.859ns = ( 18.141 - 20.000 ) - Source Clock Delay (SCD): -2.420ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 16.055ns (logic 8.448ns (52.618%) route 7.607ns (47.382%)) + Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=2) + Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.956ns = ( 18.044 - 20.000 ) + Source Clock Delay (SCD): -2.421ns + Clock Pessimism Removal (CPR): -0.505ns Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.203ns @@ -1072,27 +909,44 @@ Slack (MET) : 3.484ns (required time - arrival time) -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1 - SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C + net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 + SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q - net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1] - SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O - net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0] - SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O - net (fo=2, routed) 0.905 3.857 execution/result0__0_3 - SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O - net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1] - DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_P[3]) - 3.841 8.470 r execution/alu/result0__0/P[3] - net (fo=1, routed) 0.752 9.223 execution/alu/result0__0_n_102 - SLICE_X10Y16 LUT6 (Prop_lut6_I1_O) 0.124 9.347 r execution/alu/MEM_ALU_result[3]_i_10/O - net (fo=1, routed) 0.452 9.799 execution/alu/MEM_ALU_result[3]_i_10_n_0 - SLICE_X9Y18 LUT6 (Prop_lut6_I5_O) 0.124 9.923 r execution/alu/MEM_ALU_result[3]_i_4/O - net (fo=34, routed) 3.324 13.247 execution/alu/MEM_ALU_result[3]_i_4_n_0 - SLICE_X48Y104 LUT6 (Prop_lut6_I3_O) 0.124 13.371 r execution/alu/MEM_ALU_result[3]_rep_i_1__25/O - net (fo=1, routed) 0.613 13.984 memory_access/MEM_ALU_result_reg[3]_rep__25_2 - SLICE_X48Y104 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__25/D + SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q + net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source + SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O + net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] + SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O + net (fo=2, routed) 0.560 2.844 execution/result0__0_4 + SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O + net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) + 4.240 8.261 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.781 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.363 r execution/alu/result0_inferred__11/i__carry__0/CO[3] + net (fo=1, routed) 0.000 11.363 execution/alu/result0_inferred__11/i__carry__0_n_0 + SLICE_X11Y37 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 11.477 r execution/alu/result0_inferred__11/i__carry__1/CO[3] + net (fo=1, routed) 0.000 11.477 execution/alu/result0_inferred__11/i__carry__1_n_0 + SLICE_X11Y38 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 11.699 r execution/alu/result0_inferred__11/i__carry__2/O[0] + net (fo=1, routed) 0.661 12.360 execution/alu/result0_inferred__11/i__carry__2_n_7 + SLICE_X7Y39 LUT4 (Prop_lut4_I3_O) 0.299 12.659 r execution/alu/MEM_ALU_result[28]_i_12/O + net (fo=1, routed) 0.436 13.095 execution/alu/MEM_ALU_result[28]_i_12_n_0 + SLICE_X4Y40 LUT5 (Prop_lut5_I4_O) 0.124 13.219 r execution/alu/MEM_ALU_result[28]_i_4/O + net (fo=1, routed) 0.291 13.510 execution/alu/MEM_ALU_result[28]_i_4_n_0 + SLICE_X5Y40 LUT6 (Prop_lut6_I3_O) 0.124 13.634 r execution/alu/MEM_ALU_result[28]_i_1/O + net (fo=1, routed) 0.000 13.634 memory_access/prev_ALU_result[28] + SLICE_X5Y40 FDRE r memory_access/MEM_ALU_result_reg[28]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1105,16 +959,188 @@ Slack (MET) : 3.484ns (required time - arrival time) -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.612 18.141 memory_access/clk_out1 - SLICE_X48Y104 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__25/C - clock pessimism -0.498 17.643 - clock uncertainty -0.108 17.535 - SLICE_X48Y104 FDRE (Setup_fdre_C_D) -0.067 17.468 memory_access/MEM_ALU_result_reg[3]_rep__25 + net (fo=18132, routed) 1.515 18.044 memory_access/clk_out1 + SLICE_X5Y40 FDRE r memory_access/MEM_ALU_result_reg[28]/C + clock pessimism -0.505 17.539 + clock uncertainty -0.108 17.431 + SLICE_X5Y40 FDRE (Setup_fdre_C_D) 0.031 17.462 memory_access/MEM_ALU_result_reg[28] ------------------------------------------------------------------- - required time 17.468 - arrival time -13.984 + required time 17.462 + arrival time -13.634 ------------------------------------------------------------------- - slack 3.484 + slack 3.828 + +Slack (MET) : 3.929ns (required time - arrival time) + Source: write_back/WB_WB_source_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: memory_access/MEM_ALU_result_reg[20]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 15.952ns (logic 8.220ns (51.530%) route 7.732ns (48.470%)) + Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) + Clock Path Skew: -0.043ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.959ns = ( 18.041 - 20.000 ) + Source Clock Delay (SCD): -2.421ns + Clock Pessimism Removal (CPR): -0.505ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 + SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q + net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source + SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O + net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] + SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O + net (fo=2, routed) 0.560 2.844 execution/result0__0_4 + SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O + net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) + 4.240 8.261 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.781 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[0]) + 0.222 11.471 r execution/alu/result0_inferred__11/i__carry__0/O[0] + net (fo=1, routed) 0.653 12.124 execution/alu/result0_inferred__11/i__carry__0_n_7 + SLICE_X5Y36 LUT4 (Prop_lut4_I3_O) 0.299 12.423 r execution/alu/MEM_ALU_result[20]_i_12/O + net (fo=1, routed) 0.567 12.990 execution/alu/MEM_ALU_result[20]_i_12_n_0 + SLICE_X3Y34 LUT6 (Prop_lut6_I5_O) 0.124 13.114 r execution/alu/MEM_ALU_result[20]_i_4/O + net (fo=1, routed) 0.292 13.407 execution/alu/MEM_ALU_result[20]_i_4_n_0 + SLICE_X3Y33 LUT6 (Prop_lut6_I3_O) 0.124 13.531 r execution/alu/MEM_ALU_result[20]_i_1/O + net (fo=1, routed) 0.000 13.531 memory_access/prev_ALU_result[20] + SLICE_X3Y33 FDRE r memory_access/MEM_ALU_result_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 20.000 20.000 r + R4 0.000 20.000 r hardware_clk (IN) + net (fo=0) 0.000 20.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.512 18.041 memory_access/clk_out1 + SLICE_X3Y33 FDRE r memory_access/MEM_ALU_result_reg[20]/C + clock pessimism -0.505 17.536 + clock uncertainty -0.108 17.428 + SLICE_X3Y33 FDRE (Setup_fdre_C_D) 0.031 17.459 memory_access/MEM_ALU_result_reg[20] + ------------------------------------------------------------------- + required time 17.459 + arrival time -13.531 + ------------------------------------------------------------------- + slack 3.929 + +Slack (MET) : 3.938ns (required time - arrival time) + Source: write_back/WB_WB_source_reg/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: memory_access/MEM_ALU_result_reg[22]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 15.943ns (logic 8.240ns (51.684%) route 7.703ns (48.316%)) + Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3) + Clock Path Skew: -0.041ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.957ns = ( 18.043 - 20.000 ) + Source Clock Delay (SCD): -2.421ns + Clock Pessimism Removal (CPR): -0.505ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.555 -2.421 write_back/clk_out1 + SLICE_X14Y59 FDRE r write_back/WB_WB_source_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X14Y59 FDRE (Prop_fdre_C_Q) 0.478 -1.943 r write_back/WB_WB_source_reg/Q + net (fo=300, routed) 1.797 -0.146 write_back/WB_WB_source + SLICE_X40Y69 LUT3 (Prop_lut3_I1_O) 0.301 0.155 r write_back/registers[1][2]_i_2/O + net (fo=35, routed) 2.005 2.160 memory_access/WB_register_write_data[1] + SLICE_X15Y45 LUT6 (Prop_lut6_I2_O) 0.124 2.284 f memory_access/result0__0_i_21/O + net (fo=2, routed) 0.560 2.844 execution/result0__0_4 + SLICE_X12Y44 LUT3 (Prop_lut3_I2_O) 0.116 2.960 r execution/result0__0_i_15/O + net (fo=148, routed) 1.061 4.021 execution/alu/ALU_in1[2] + DSP48_X0Y13 DSP48E1 (Prop_dsp48e1_A[2]_PCOUT[47]) + 4.240 8.261 r execution/alu/result0__0/PCOUT[47] + net (fo=1, routed) 0.002 8.263 execution/alu/result0__0_n_106 + DSP48_X0Y14 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 9.781 r execution/alu/result0__1/P[0] + net (fo=2, routed) 0.794 10.575 execution/alu/result0__1_n_105 + SLICE_X11Y35 LUT2 (Prop_lut2_I0_O) 0.124 10.699 r execution/alu/i__carry_i_3__0/O + net (fo=1, routed) 0.000 10.699 execution/alu/i__carry_i_3__0_n_0 + SLICE_X11Y35 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 11.249 r execution/alu/result0_inferred__11/i__carry/CO[3] + net (fo=1, routed) 0.000 11.249 execution/alu/result0_inferred__11/i__carry_n_0 + SLICE_X11Y36 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 11.488 r execution/alu/result0_inferred__11/i__carry__0/O[2] + net (fo=1, routed) 0.709 12.197 execution/alu/result0_inferred__11/i__carry__0_n_5 + SLICE_X2Y36 LUT4 (Prop_lut4_I3_O) 0.302 12.499 r execution/alu/MEM_ALU_result[22]_i_12/O + net (fo=1, routed) 0.291 12.790 execution/alu/MEM_ALU_result[22]_i_12_n_0 + SLICE_X0Y36 LUT6 (Prop_lut6_I5_O) 0.124 12.914 r execution/alu/MEM_ALU_result[22]_i_4/O + net (fo=1, routed) 0.484 13.398 execution/alu/MEM_ALU_result[22]_i_4_n_0 + SLICE_X1Y36 LUT6 (Prop_lut6_I3_O) 0.124 13.522 r execution/alu/MEM_ALU_result[22]_i_1/O + net (fo=1, routed) 0.000 13.522 memory_access/prev_ALU_result[22] + SLICE_X1Y36 FDRE r memory_access/MEM_ALU_result_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 20.000 20.000 r + R4 0.000 20.000 r hardware_clk (IN) + net (fo=0) 0.000 20.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.514 18.043 memory_access/clk_out1 + SLICE_X1Y36 FDRE r memory_access/MEM_ALU_result_reg[22]/C + clock pessimism -0.505 17.538 + clock uncertainty -0.108 17.430 + SLICE_X1Y36 FDRE (Setup_fdre_C_D) 0.029 17.459 memory_access/MEM_ALU_result_reg[22] + ------------------------------------------------------------------- + required time 17.459 + arrival time -13.522 + ------------------------------------------------------------------- + slack 3.938 @@ -1122,19 +1148,19 @@ Slack (MET) : 3.484ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.070ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[20]_rep__5/C +Slack (MET) : 0.055ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[19]_rep__5/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435472][20]/D + Destination: data_memory/memory_data_reg[268435459][19]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.411ns (logic 0.141ns (34.345%) route 0.270ns (65.655%)) + Data Path Delay: 0.396ns (logic 0.141ns (35.573%) route 0.255ns (64.427%)) Logic Levels: 0 - Clock Path Skew: 0.269ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.294ns - Source Clock Delay (SCD): -0.524ns + Clock Path Skew: 0.271ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.293ns + Source Clock Delay (SCD): -0.525ns Clock Pessimism Removal (CPR): -0.039ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1149,12 +1175,12 @@ Slack (MET) : 0.070ns (arrival time - required time) -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.563 -0.524 memory_access/clk_out1 - SLICE_X41Y46 FDRE r memory_access/MEM_memory_write_data_reg[20]_rep__5/C + net (fo=18132, routed) 0.562 -0.525 memory_access/clk_out1 + SLICE_X37Y51 FDRE r memory_access/MEM_memory_write_data_reg[19]_rep__5/C ------------------------------------------------------------------- ------------------- - SLICE_X41Y46 FDRE (Prop_fdre_C_Q) 0.141 -0.383 r memory_access/MEM_memory_write_data_reg[20]_rep__5/Q - net (fo=64, routed) 0.270 -0.114 data_memory/memory_data_reg[268435457][31]_0[20] - SLICE_X43Y51 FDRE r data_memory/memory_data_reg[268435472][20]/D + SLICE_X37Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.384 r memory_access/MEM_memory_write_data_reg[19]_rep__5/Q + net (fo=64, routed) 0.255 -0.129 data_memory/memory_data_reg[268435457][31]_0[19] + SLICE_X37Y47 FDRE r data_memory/memory_data_reg[268435459][19]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1167,30 +1193,30 @@ Slack (MET) : 0.070ns (arrival time - required time) -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.832 -0.294 data_memory/clk_out1 - SLICE_X43Y51 FDRE r data_memory/memory_data_reg[268435472][20]/C - clock pessimism 0.039 -0.255 - SLICE_X43Y51 FDRE (Hold_fdre_C_D) 0.072 -0.183 data_memory/memory_data_reg[268435472][20] + net (fo=18132, routed) 0.833 -0.293 data_memory/clk_out1 + SLICE_X37Y47 FDRE r data_memory/memory_data_reg[268435459][19]/C + clock pessimism 0.039 -0.254 + SLICE_X37Y47 FDRE (Hold_fdre_C_D) 0.070 -0.184 data_memory/memory_data_reg[268435459][19] ------------------------------------------------------------------- - required time 0.183 - arrival time -0.114 + required time 0.184 + arrival time -0.129 ------------------------------------------------------------------- - slack 0.070 + slack 0.055 -Slack (MET) : 0.079ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[25]/C +Slack (MET) : 0.056ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[30]_rep__4/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435951][25]/D + Destination: data_memory/memory_data_reg[268435544][30]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.313ns (logic 0.141ns (45.059%) route 0.172ns (54.941%)) + Data Path Delay: 0.397ns (logic 0.141ns (35.524%) route 0.256ns (64.476%)) Logic Levels: 0 - Clock Path Skew: 0.182ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.291ns - Source Clock Delay (SCD): -0.440ns - Clock Pessimism Removal (CPR): -0.034ns + Clock Path Skew: 0.271ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.293ns + Source Clock Delay (SCD): -0.525ns + Clock Pessimism Removal (CPR): -0.039ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1204,12 +1230,12 @@ Slack (MET) : 0.079ns (arrival time - required time) -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.647 -0.440 memory_access/clk_out1 - SLICE_X15Y100 FDRE r memory_access/MEM_memory_write_data_reg[25]/C + net (fo=18132, routed) 0.562 -0.525 memory_access/clk_out1 + SLICE_X32Y52 FDRE r memory_access/MEM_memory_write_data_reg[30]_rep__4/C ------------------------------------------------------------------- ------------------- - SLICE_X15Y100 FDRE (Prop_fdre_C_Q) 0.141 -0.299 r memory_access/MEM_memory_write_data_reg[25]/Q - net (fo=64, routed) 0.172 -0.127 data_memory/memory_data_reg[268435905][31]_0[25] - SLICE_X14Y98 FDRE r data_memory/memory_data_reg[268435951][25]/D + SLICE_X32Y52 FDRE (Prop_fdre_C_Q) 0.141 -0.384 r memory_access/MEM_memory_write_data_reg[30]_rep__4/Q + net (fo=64, routed) 0.256 -0.128 data_memory/memory_data_reg[268435521][31]_0[30] + SLICE_X32Y49 FDRE r data_memory/memory_data_reg[268435544][30]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1222,30 +1248,30 @@ Slack (MET) : 0.079ns (arrival time - required time) -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.834 -0.291 data_memory/clk_out1 - SLICE_X14Y98 FDRE r data_memory/memory_data_reg[268435951][25]/C - clock pessimism 0.034 -0.257 - SLICE_X14Y98 FDRE (Hold_fdre_C_D) 0.052 -0.205 data_memory/memory_data_reg[268435951][25] + net (fo=18132, routed) 0.833 -0.293 data_memory/clk_out1 + SLICE_X32Y49 FDRE r data_memory/memory_data_reg[268435544][30]/C + clock pessimism 0.039 -0.254 + SLICE_X32Y49 FDRE (Hold_fdre_C_D) 0.070 -0.184 data_memory/memory_data_reg[268435544][30] ------------------------------------------------------------------- - required time 0.205 - arrival time -0.127 + required time 0.184 + arrival time -0.128 ------------------------------------------------------------------- - slack 0.079 + slack 0.056 -Slack (MET) : 0.080ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[0]_rep__4/C +Slack (MET) : 0.058ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[10]_rep__5/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435548][0]/D + Destination: data_memory/memory_data_reg[268435511][10]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.413ns (logic 0.164ns (39.691%) route 0.249ns (60.309%)) + Data Path Delay: 0.399ns (logic 0.141ns (35.326%) route 0.258ns (64.674%)) Logic Levels: 0 - Clock Path Skew: 0.263ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.299ns - Source Clock Delay (SCD): -0.528ns - Clock Pessimism Removal (CPR): -0.034ns + Clock Path Skew: 0.271ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.293ns + Source Clock Delay (SCD): -0.525ns + Clock Pessimism Removal (CPR): -0.039ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1259,12 +1285,12 @@ Slack (MET) : 0.080ns (arrival time - required time) -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.559 -0.528 memory_access/clk_out1 - SLICE_X38Y36 FDRE r memory_access/MEM_memory_write_data_reg[0]_rep__4/C + net (fo=18132, routed) 0.562 -0.525 memory_access/clk_out1 + SLICE_X32Y52 FDRE r memory_access/MEM_memory_write_data_reg[10]_rep__5/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y36 FDRE (Prop_fdre_C_Q) 0.164 -0.364 r memory_access/MEM_memory_write_data_reg[0]_rep__4/Q - net (fo=64, routed) 0.249 -0.115 data_memory/memory_data_reg[268435521][31]_0[0] - SLICE_X35Y37 FDRE r data_memory/memory_data_reg[268435548][0]/D + SLICE_X32Y52 FDRE (Prop_fdre_C_Q) 0.141 -0.384 r memory_access/MEM_memory_write_data_reg[10]_rep__5/Q + net (fo=65, routed) 0.258 -0.126 data_memory/memory_data_reg[268435457][31]_0[10] + SLICE_X39Y48 FDRE r data_memory/memory_data_reg[268435511][10]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1277,29 +1303,194 @@ Slack (MET) : 0.080ns (arrival time - required time) -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.827 -0.299 data_memory/clk_out1 - SLICE_X35Y37 FDRE r data_memory/memory_data_reg[268435548][0]/C - clock pessimism 0.034 -0.265 - SLICE_X35Y37 FDRE (Hold_fdre_C_D) 0.070 -0.195 data_memory/memory_data_reg[268435548][0] + net (fo=18132, routed) 0.833 -0.293 data_memory/clk_out1 + SLICE_X39Y48 FDRE r data_memory/memory_data_reg[268435511][10]/C + clock pessimism 0.039 -0.254 + SLICE_X39Y48 FDRE (Hold_fdre_C_D) 0.070 -0.184 data_memory/memory_data_reg[268435511][10] + ------------------------------------------------------------------- + required time 0.184 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.058 + +Slack (MET) : 0.068ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[10]_rep__5/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435507][10]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.397ns (logic 0.141ns (35.476%) route 0.256ns (64.524%)) + Logic Levels: 0 + Clock Path Skew: 0.271ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.293ns + Source Clock Delay (SCD): -0.525ns + Clock Pessimism Removal (CPR): -0.039ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.562 -0.525 memory_access/clk_out1 + SLICE_X32Y52 FDRE r memory_access/MEM_memory_write_data_reg[10]_rep__5/C + ------------------------------------------------------------------- ------------------- + SLICE_X32Y52 FDRE (Prop_fdre_C_Q) 0.141 -0.384 r memory_access/MEM_memory_write_data_reg[10]_rep__5/Q + net (fo=65, routed) 0.256 -0.128 data_memory/memory_data_reg[268435457][31]_0[10] + SLICE_X38Y49 FDRE r data_memory/memory_data_reg[268435507][10]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.833 -0.293 data_memory/clk_out1 + SLICE_X38Y49 FDRE r data_memory/memory_data_reg[268435507][10]/C + clock pessimism 0.039 -0.254 + SLICE_X38Y49 FDRE (Hold_fdre_C_D) 0.059 -0.195 data_memory/memory_data_reg[268435507][10] ------------------------------------------------------------------- required time 0.195 - arrival time -0.115 + arrival time -0.128 + ------------------------------------------------------------------- + slack 0.068 + +Slack (MET) : 0.076ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[17]_rep__3/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435591][17]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.402ns (logic 0.141ns (35.079%) route 0.261ns (64.921%)) + Logic Levels: 0 + Clock Path Skew: 0.256ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.309ns + Source Clock Delay (SCD): -0.531ns + Clock Pessimism Removal (CPR): -0.034ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.556 -0.531 memory_access/clk_out1 + SLICE_X33Y31 FDRE r memory_access/MEM_memory_write_data_reg[17]_rep__3/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.390 r memory_access/MEM_memory_write_data_reg[17]_rep__3/Q + net (fo=64, routed) 0.261 -0.129 data_memory/memory_data_reg[268435585][31]_0[17] + SLICE_X39Y26 FDRE r data_memory/memory_data_reg[268435591][17]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.817 -0.309 data_memory/clk_out1 + SLICE_X39Y26 FDRE r data_memory/memory_data_reg[268435591][17]/C + clock pessimism 0.034 -0.275 + SLICE_X39Y26 FDRE (Hold_fdre_C_D) 0.070 -0.205 data_memory/memory_data_reg[268435591][17] + ------------------------------------------------------------------- + required time 0.205 + arrival time -0.129 + ------------------------------------------------------------------- + slack 0.076 + +Slack (MET) : 0.080ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[30]_rep__5/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: data_memory/memory_data_reg[268435463][30]/D + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_phase_locked_loop + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) + Data Path Delay: 0.418ns (logic 0.141ns (33.733%) route 0.277ns (66.267%)) + Logic Levels: 0 + Clock Path Skew: 0.272ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.292ns + Source Clock Delay (SCD): -0.525ns + Clock Pessimism Removal (CPR): -0.039ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.562 -0.525 memory_access/clk_out1 + SLICE_X28Y52 FDRE r memory_access/MEM_memory_write_data_reg[30]_rep__5/C + ------------------------------------------------------------------- ------------------- + SLICE_X28Y52 FDRE (Prop_fdre_C_Q) 0.141 -0.384 r memory_access/MEM_memory_write_data_reg[30]_rep__5/Q + net (fo=64, routed) 0.277 -0.107 data_memory/memory_data_reg[268435457][31]_0[30] + SLICE_X28Y47 FDRE r data_memory/memory_data_reg[268435463][30]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.834 -0.292 data_memory/clk_out1 + SLICE_X28Y47 FDRE r data_memory/memory_data_reg[268435463][30]/C + clock pessimism 0.039 -0.253 + SLICE_X28Y47 FDRE (Hold_fdre_C_D) 0.066 -0.187 data_memory/memory_data_reg[268435463][30] + ------------------------------------------------------------------- + required time 0.187 + arrival time -0.107 ------------------------------------------------------------------- slack 0.080 -Slack (MET) : 0.086ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[31]_rep__4/C +Slack (MET) : 0.082ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[13]_rep__0/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435541][31]/D + Destination: data_memory/memory_data_reg[268435833][13]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.414ns (logic 0.164ns (39.608%) route 0.250ns (60.392%)) + Data Path Delay: 0.420ns (logic 0.141ns (33.608%) route 0.279ns (66.392%)) Logic Levels: 0 - Clock Path Skew: 0.262ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.300ns - Source Clock Delay (SCD): -0.528ns + Clock Path Skew: 0.268ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.296ns + Source Clock Delay (SCD): -0.530ns Clock Pessimism Removal (CPR): -0.034ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1314,12 +1505,12 @@ Slack (MET) : 0.086ns (arrival time - required time) -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.559 -0.528 memory_access/clk_out1 - SLICE_X38Y36 FDRE r memory_access/MEM_memory_write_data_reg[31]_rep__4/C + net (fo=18132, routed) 0.557 -0.530 memory_access/clk_out1 + SLICE_X35Y87 FDRE r memory_access/MEM_memory_write_data_reg[13]_rep__0/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y36 FDRE (Prop_fdre_C_Q) 0.164 -0.364 r memory_access/MEM_memory_write_data_reg[31]_rep__4/Q - net (fo=64, routed) 0.250 -0.114 data_memory/memory_data_reg[268435521][31]_0[31] - SLICE_X35Y36 FDRE r data_memory/memory_data_reg[268435541][31]/D + SLICE_X35Y87 FDRE (Prop_fdre_C_Q) 0.141 -0.389 r memory_access/MEM_memory_write_data_reg[13]_rep__0/Q + net (fo=64, routed) 0.279 -0.111 data_memory/memory_data_reg[268435777][31]_0[13] + SLICE_X37Y94 FDRE r data_memory/memory_data_reg[268435833][13]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1332,29 +1523,29 @@ Slack (MET) : 0.086ns (arrival time - required time) -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.826 -0.300 data_memory/clk_out1 - SLICE_X35Y36 FDRE r data_memory/memory_data_reg[268435541][31]/C - clock pessimism 0.034 -0.266 - SLICE_X35Y36 FDRE (Hold_fdre_C_D) 0.066 -0.200 data_memory/memory_data_reg[268435541][31] + net (fo=18132, routed) 0.829 -0.296 data_memory/clk_out1 + SLICE_X37Y94 FDRE r data_memory/memory_data_reg[268435833][13]/C + clock pessimism 0.034 -0.262 + SLICE_X37Y94 FDRE (Hold_fdre_C_D) 0.070 -0.192 data_memory/memory_data_reg[268435833][13] ------------------------------------------------------------------- - required time 0.200 - arrival time -0.114 + required time 0.192 + arrival time -0.111 ------------------------------------------------------------------- - slack 0.086 + slack 0.082 -Slack (MET) : 0.092ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[31]_rep__4/C +Slack (MET) : 0.082ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[17]_rep__2/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435548][31]/D + Destination: data_memory/memory_data_reg[268435674][17]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.425ns (logic 0.164ns (38.560%) route 0.261ns (61.440%)) + Data Path Delay: 0.412ns (logic 0.141ns (34.215%) route 0.271ns (65.785%)) Logic Levels: 0 - Clock Path Skew: 0.263ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.299ns - Source Clock Delay (SCD): -0.528ns + Clock Path Skew: 0.260ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.531ns Clock Pessimism Removal (CPR): -0.034ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1369,12 +1560,12 @@ Slack (MET) : 0.092ns (arrival time - required time) -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.559 -0.528 memory_access/clk_out1 - SLICE_X38Y36 FDRE r memory_access/MEM_memory_write_data_reg[31]_rep__4/C + net (fo=18132, routed) 0.556 -0.531 memory_access/clk_out1 + SLICE_X33Y31 FDRE r memory_access/MEM_memory_write_data_reg[17]_rep__2/C ------------------------------------------------------------------- ------------------- - SLICE_X38Y36 FDRE (Prop_fdre_C_Q) 0.164 -0.364 r memory_access/MEM_memory_write_data_reg[31]_rep__4/Q - net (fo=64, routed) 0.261 -0.103 data_memory/memory_data_reg[268435521][31]_0[31] - SLICE_X35Y37 FDRE r data_memory/memory_data_reg[268435548][31]/D + SLICE_X33Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.390 r memory_access/MEM_memory_write_data_reg[17]_rep__2/Q + net (fo=64, routed) 0.271 -0.119 data_memory/memory_data_reg[268435649][31]_0[17] + SLICE_X41Y28 FDRE r data_memory/memory_data_reg[268435674][17]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1387,86 +1578,29 @@ Slack (MET) : 0.092ns (arrival time - required time) -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.827 -0.299 data_memory/clk_out1 - SLICE_X35Y37 FDRE r data_memory/memory_data_reg[268435548][31]/C - clock pessimism 0.034 -0.265 - SLICE_X35Y37 FDRE (Hold_fdre_C_D) 0.070 -0.195 data_memory/memory_data_reg[268435548][31] + net (fo=18132, routed) 0.821 -0.305 data_memory/clk_out1 + SLICE_X41Y28 FDRE r data_memory/memory_data_reg[268435674][17]/C + clock pessimism 0.034 -0.271 + SLICE_X41Y28 FDRE (Hold_fdre_C_D) 0.070 -0.201 data_memory/memory_data_reg[268435674][17] ------------------------------------------------------------------- - required time 0.195 - arrival time -0.103 + required time 0.201 + arrival time -0.119 ------------------------------------------------------------------- - slack 0.092 + slack 0.082 -Slack (MET) : 0.093ns (arrival time - required time) - Source: instruction_decode/IFID_PC_plus_4_reg[21]/C +Slack (MET) : 0.088ns (arrival time - required time) + Source: instruction_fetch/PC_reg[26]/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: instruction_decode/register_file/registers_reg[10][21]/D + Destination: instruction_decode/IFID_PC_plus_4_reg[26]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.447ns (logic 0.186ns (41.615%) route 0.261ns (58.385%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.262ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.301ns - Source Clock Delay (SCD): -0.529ns - Clock Pessimism Removal (CPR): -0.034ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.558 -0.529 instruction_decode/clk_out1 - SLICE_X28Y16 FDRE r instruction_decode/IFID_PC_plus_4_reg[21]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y16 FDRE (Prop_fdre_C_Q) 0.141 -0.388 r instruction_decode/IFID_PC_plus_4_reg[21]/Q - net (fo=39, routed) 0.261 -0.127 write_back/registers_reg[3][31][21] - SLICE_X39Y16 LUT6 (Prop_lut6_I3_O) 0.045 -0.082 r write_back/registers[10][21]_i_1/O - net (fo=1, routed) 0.000 -0.082 instruction_decode/register_file/registers_reg[10][31]_0[21] - SLICE_X39Y16 FDRE r instruction_decode/register_file/registers_reg[10][21]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.825 -0.301 instruction_decode/register_file/clk_out1 - SLICE_X39Y16 FDRE r instruction_decode/register_file/registers_reg[10][21]/C - clock pessimism 0.034 -0.267 - SLICE_X39Y16 FDRE (Hold_fdre_C_D) 0.092 -0.175 instruction_decode/register_file/registers_reg[10][21] - ------------------------------------------------------------------- - required time 0.175 - arrival time -0.082 - ------------------------------------------------------------------- - slack 0.093 - -Slack (MET) : 0.093ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[6]_rep__0/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435776][6]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.128ns (33.753%) route 0.251ns (66.247%)) - Logic Levels: 0 - Clock Path Skew: 0.269ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.294ns - Source Clock Delay (SCD): -0.524ns + Data Path Delay: 0.458ns (logic 0.274ns (59.790%) route 0.184ns (40.210%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.268ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.291ns + Source Clock Delay (SCD): -0.520ns Clock Pessimism Removal (CPR): -0.039ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1481,12 +1615,15 @@ Slack (MET) : 0.093ns (arrival time - required time) -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.563 -0.524 memory_access/clk_out1 - SLICE_X31Y44 FDRE r memory_access/MEM_memory_write_data_reg[6]_rep__0/C + net (fo=18132, routed) 0.567 -0.520 instruction_fetch/clk_out1 + SLICE_X8Y49 FDRE r instruction_fetch/PC_reg[26]/C ------------------------------------------------------------------- ------------------- - SLICE_X31Y44 FDRE (Prop_fdre_C_Q) 0.128 -0.396 r memory_access/MEM_memory_write_data_reg[6]_rep__0/Q - net (fo=64, routed) 0.251 -0.145 data_memory/memory_data_reg[268435777][31]_0[6] - SLICE_X28Y51 FDRE r data_memory/memory_data_reg[268435776][6]/D + SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.356 r instruction_fetch/PC_reg[26]/Q + net (fo=2, routed) 0.184 -0.172 instruction_fetch/PC[26] + SLICE_X9Y50 CARRY4 (Prop_carry4_S[1]_O[1]) + 0.110 -0.062 r instruction_fetch/adder_out_carry__5/O[1] + net (fo=2, routed) 0.000 -0.062 instruction_decode/D[26] + SLICE_X9Y50 FDRE r instruction_decode/IFID_PC_plus_4_reg[26]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1499,139 +1636,29 @@ Slack (MET) : 0.093ns (arrival time - required time) -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.832 -0.294 data_memory/clk_out1 - SLICE_X28Y51 FDRE r data_memory/memory_data_reg[268435776][6]/C - clock pessimism 0.039 -0.255 - SLICE_X28Y51 FDRE (Hold_fdre_C_D) 0.017 -0.238 data_memory/memory_data_reg[268435776][6] + net (fo=18132, routed) 0.834 -0.291 instruction_decode/clk_out1 + SLICE_X9Y50 FDRE r instruction_decode/IFID_PC_plus_4_reg[26]/C + clock pessimism 0.039 -0.252 + SLICE_X9Y50 FDRE (Hold_fdre_C_D) 0.102 -0.150 instruction_decode/IFID_PC_plus_4_reg[26] ------------------------------------------------------------------- - required time 0.238 - arrival time -0.145 + required time 0.150 + arrival time -0.062 ------------------------------------------------------------------- - slack 0.093 + slack 0.088 -Slack (MET) : 0.094ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[7]_rep__2/C +Slack (MET) : 0.089ns (arrival time - required time) + Source: memory_access/MEM_memory_write_data_reg[9]_rep__1/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435711][7]/D + Destination: data_memory/memory_data_reg[268435738][9]/D (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: clk_out1_phase_locked_loop Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.373ns (logic 0.128ns (34.278%) route 0.245ns (65.722%)) + Data Path Delay: 0.512ns (logic 0.141ns (27.552%) route 0.371ns (72.448%)) Logic Levels: 0 - Clock Path Skew: 0.261ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.222ns - Source Clock Delay (SCD): -0.453ns - Clock Pessimism Removal (CPR): -0.030ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.634 -0.453 memory_access/clk_out1 - SLICE_X32Y129 FDRE r memory_access/MEM_memory_write_data_reg[7]_rep__2/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y129 FDRE (Prop_fdre_C_Q) 0.128 -0.325 r memory_access/MEM_memory_write_data_reg[7]_rep__2/Q - net (fo=64, routed) 0.245 -0.079 data_memory/memory_data_reg[268435649][31]_0[7] - SLICE_X37Y128 FDRE r data_memory/memory_data_reg[268435711][7]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.904 -0.222 data_memory/clk_out1 - SLICE_X37Y128 FDRE r data_memory/memory_data_reg[268435711][7]/C - clock pessimism 0.030 -0.192 - SLICE_X37Y128 FDRE (Hold_fdre_C_D) 0.019 -0.173 data_memory/memory_data_reg[268435711][7] - ------------------------------------------------------------------- - required time 0.173 - arrival time -0.079 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.097ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[7]_rep__2/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435708][7]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.376ns (logic 0.128ns (34.010%) route 0.248ns (65.990%)) - Logic Levels: 0 - Clock Path Skew: 0.261ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.222ns - Source Clock Delay (SCD): -0.453ns - Clock Pessimism Removal (CPR): -0.030ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.634 -0.453 memory_access/clk_out1 - SLICE_X32Y129 FDRE r memory_access/MEM_memory_write_data_reg[7]_rep__2/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y129 FDRE (Prop_fdre_C_Q) 0.128 -0.325 r memory_access/MEM_memory_write_data_reg[7]_rep__2/Q - net (fo=64, routed) 0.248 -0.076 data_memory/memory_data_reg[268435649][31]_0[7] - SLICE_X36Y128 FDRE r data_memory/memory_data_reg[268435708][7]/D - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.904 -0.222 data_memory/clk_out1 - SLICE_X36Y128 FDRE r data_memory/memory_data_reg[268435708][7]/C - clock pessimism 0.030 -0.192 - SLICE_X36Y128 FDRE (Hold_fdre_C_D) 0.019 -0.173 data_memory/memory_data_reg[268435708][7] - ------------------------------------------------------------------- - required time 0.173 - arrival time -0.076 - ------------------------------------------------------------------- - slack 0.097 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: memory_access/MEM_memory_write_data_reg[5]_rep__1/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: data_memory/memory_data_reg[268435761][5]/D - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: clk_out1_phase_locked_loop - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns) - Data Path Delay: 0.433ns (logic 0.141ns (32.546%) route 0.292ns (67.454%)) - Logic Levels: 0 - Clock Path Skew: 0.255ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.533ns + Clock Path Skew: 0.352ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.206ns + Source Clock Delay (SCD): -0.524ns Clock Pessimism Removal (CPR): -0.034ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1646,12 +1673,12 @@ Slack (MET) : 0.108ns (arrival time - required time) -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.554 -0.533 memory_access/clk_out1 - SLICE_X36Y81 FDRE r memory_access/MEM_memory_write_data_reg[5]_rep__1/C + net (fo=18132, routed) 0.563 -0.524 memory_access/clk_out1 + SLICE_X49Y90 FDRE r memory_access/MEM_memory_write_data_reg[9]_rep__1/C ------------------------------------------------------------------- ------------------- - SLICE_X36Y81 FDRE (Prop_fdre_C_Q) 0.141 -0.392 r memory_access/MEM_memory_write_data_reg[5]_rep__1/Q - net (fo=64, routed) 0.292 -0.100 data_memory/memory_data_reg[268435713][31]_0[5] - SLICE_X32Y75 FDRE r data_memory/memory_data_reg[268435761][5]/D + SLICE_X49Y90 FDRE (Prop_fdre_C_Q) 0.141 -0.383 r memory_access/MEM_memory_write_data_reg[9]_rep__1/Q + net (fo=64, routed) 0.371 -0.012 data_memory/memory_data_reg[268435713][31]_0[9] + SLICE_X55Y100 FDRE r data_memory/memory_data_reg[268435738][9]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -1664,15 +1691,15 @@ Slack (MET) : 0.108ns (arrival time - required time) -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.813 -0.312 data_memory/clk_out1 - SLICE_X32Y75 FDRE r data_memory/memory_data_reg[268435761][5]/C - clock pessimism 0.034 -0.278 - SLICE_X32Y75 FDRE (Hold_fdre_C_D) 0.070 -0.208 data_memory/memory_data_reg[268435761][5] + net (fo=18132, routed) 0.920 -0.206 data_memory/clk_out1 + SLICE_X55Y100 FDRE r data_memory/memory_data_reg[268435738][9]/C + clock pessimism 0.034 -0.172 + SLICE_X55Y100 FDRE (Hold_fdre_C_D) 0.070 -0.102 data_memory/memory_data_reg[268435738][9] ------------------------------------------------------------------- - required time 0.208 - arrival time -0.100 + required time 0.102 + arrival time -0.012 ------------------------------------------------------------------- - slack 0.108 + slack 0.089 @@ -1688,35 +1715,35 @@ Sources: { pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y0 pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 20.000 18.751 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKOUT0 -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X32Y31 data_memory/memory_data_reg[268435456][14]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X32Y31 data_memory/memory_data_reg[268435456][15]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X48Y54 data_memory/memory_data_reg[268435456][16]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y47 data_memory/memory_data_reg[268435456][0]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X59Y56 data_memory/memory_data_reg[268435456][10]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X55Y55 data_memory/memory_data_reg[268435456][11]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X43Y28 data_memory/memory_data_reg[268435456][12]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X30Y29 data_memory/memory_data_reg[268435456][13]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X2Y33 data_memory/memory_data_reg[268435456][14]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X46Y38 data_memory/memory_data_reg[268435456][15]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X2Y33 data_memory/memory_data_reg[268435456][16]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 20.000 140.000 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKOUT0 -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C -Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C -Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C -High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C -High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X14Y47 data_memory/memory_data_reg[268435456][0]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X14Y47 data_memory/memory_data_reg[268435456][0]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y56 data_memory/memory_data_reg[268435456][10]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y56 data_memory/memory_data_reg[268435456][10]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X55Y55 data_memory/memory_data_reg[268435456][11]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X55Y55 data_memory/memory_data_reg[268435456][11]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y28 data_memory/memory_data_reg[268435456][12]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y28 data_memory/memory_data_reg[268435456][12]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X30Y29 data_memory/memory_data_reg[268435456][13]/C +Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X30Y29 data_memory/memory_data_reg[268435456][13]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X14Y47 data_memory/memory_data_reg[268435456][0]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X14Y47 data_memory/memory_data_reg[268435456][0]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y56 data_memory/memory_data_reg[268435456][10]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y56 data_memory/memory_data_reg[268435456][10]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X55Y55 data_memory/memory_data_reg[268435456][11]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X55Y55 data_memory/memory_data_reg[268435456][11]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y28 data_memory/memory_data_reg[268435456][12]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y28 data_memory/memory_data_reg[268435456][12]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X30Y29 data_memory/memory_data_reg[268435456][13]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X30Y29 data_memory/memory_data_reg[268435456][13]/C @@ -1758,222 +1785,6 @@ Min Delay 12 Endpoints Max Delay Paths -------------------------------------------------------------------------------------- -Slack: inf - Source: data_memory/memory_data_reg[268435460][0]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[0] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 6.786ns (logic 3.997ns (58.900%) route 2.789ns (41.100%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.566 -2.410 data_memory/clk_out1 - SLICE_X45Y42 FDRE r data_memory/memory_data_reg[268435460][0]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X45Y42 FDRE (Prop_fdre_C_Q) 0.456 -1.954 r data_memory/memory_data_reg[268435460][0]_lopt_replica/Q - net (fo=1, routed) 2.789 0.835 lopt - N2 OBUF (Prop_obuf_I_O) 3.541 4.376 r bcd_control_OBUF[0]_inst/O - net (fo=0) 0.000 4.376 bcd_control[0] - N2 r bcd_control[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][11]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[11] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 6.606ns (logic 3.992ns (60.431%) route 2.614ns (39.569%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.637 -2.339 data_memory/clk_out1 - SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][11]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.456 -1.883 r data_memory/memory_data_reg[268435460][11]_lopt_replica/Q - net (fo=1, routed) 2.614 0.731 lopt_2 - M2 OBUF (Prop_obuf_I_O) 3.536 4.267 r bcd_control_OBUF[11]_inst/O - net (fo=0) 0.000 4.267 bcd_control[11] - M2 r bcd_control[11] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][8]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[8] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 6.536ns (logic 4.160ns (63.646%) route 2.376ns (36.354%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.551 -2.425 data_memory/clk_out1 - SLICE_X51Y24 FDRE r data_memory/memory_data_reg[268435460][8]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X51Y24 FDRE (Prop_fdre_C_Q) 0.419 -2.006 r data_memory/memory_data_reg[268435460][8]_lopt_replica/Q - net (fo=1, routed) 2.376 0.370 lopt_10 - Y3 OBUF (Prop_obuf_I_O) 3.741 4.111 r bcd_control_OBUF[8]_inst/O - net (fo=0) 0.000 4.111 bcd_control[8] - Y3 r bcd_control[8] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][9]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[9] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 6.422ns (logic 4.016ns (62.541%) route 2.406ns (37.459%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.637 -2.339 data_memory/clk_out1 - SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.456 -1.883 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q - net (fo=1, routed) 2.406 0.523 lopt_11 - R1 OBUF (Prop_obuf_I_O) 3.560 4.083 r bcd_control_OBUF[9]_inst/O - net (fo=0) 0.000 4.083 bcd_control[9] - R1 r bcd_control[9] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][5]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[5] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 6.274ns (logic 4.014ns (63.978%) route 2.260ns (36.022%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.637 -2.339 data_memory/clk_out1 - SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.456 -1.883 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q - net (fo=1, routed) 2.260 0.377 lopt_7 - P1 OBUF (Prop_obuf_I_O) 3.558 3.935 r bcd_control_OBUF[5]_inst/O - net (fo=0) 0.000 3.935 bcd_control[5] - P1 r bcd_control[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][3]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[3] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 6.329ns (logic 4.012ns (63.387%) route 2.317ns (36.613%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.551 -2.425 data_memory/clk_out1 - SLICE_X51Y24 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X51Y24 FDRE (Prop_fdre_C_Q) 0.456 -1.969 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q - net (fo=1, routed) 2.317 0.348 lopt_5 - U5 OBUF (Prop_obuf_I_O) 3.556 3.904 r bcd_control_OBUF[3]_inst/O - net (fo=0) 0.000 3.904 bcd_control[3] - U5 r bcd_control[3] (OUT) - ------------------------------------------------------------------- ------------------- - Slack: inf Source: data_memory/memory_data_reg[268435460][1]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -1981,7 +1792,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 6.098ns (logic 3.991ns (65.436%) route 2.108ns (34.564%)) + Data Path Delay: 7.325ns (logic 4.053ns (55.326%) route 3.272ns (44.674%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2000,16 +1811,52 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.637 -2.339 data_memory/clk_out1 - SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][1]_lopt_replica/C + net (fo=18132, routed) 1.569 -2.407 data_memory/clk_out1 + SLICE_X14Y43 FDRE r data_memory/memory_data_reg[268435460][1]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.456 -1.883 r data_memory/memory_data_reg[268435460][1]_lopt_replica/Q - net (fo=1, routed) 2.108 0.225 lopt_3 - P5 OBUF (Prop_obuf_I_O) 3.535 3.759 r bcd_control_OBUF[1]_inst/O - net (fo=0) 0.000 3.759 bcd_control[1] + SLICE_X14Y43 FDRE (Prop_fdre_C_Q) 0.518 -1.889 r data_memory/memory_data_reg[268435460][1]_lopt_replica/Q + net (fo=1, routed) 3.272 1.383 lopt_3 + P5 OBUF (Prop_obuf_I_O) 3.535 4.918 r bcd_control_OBUF[1]_inst/O + net (fo=0) 0.000 4.918 bcd_control[1] P5 r bcd_control[1] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: data_memory/memory_data_reg[268435460][2]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 6.876ns (logic 4.045ns (58.829%) route 2.831ns (41.171%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.553 -2.423 data_memory/clk_out1 + SLICE_X46Y28 FDRE r data_memory/memory_data_reg[268435460][2]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X46Y28 FDRE (Prop_fdre_C_Q) 0.518 -1.905 r data_memory/memory_data_reg[268435460][2]_lopt_replica/Q + net (fo=1, routed) 2.831 0.926 lopt_4 + V5 OBUF (Prop_obuf_I_O) 3.527 4.453 r bcd_control_OBUF[2]_inst/O + net (fo=0) 0.000 4.453 bcd_control[2] + V5 r bcd_control[2] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: data_memory/memory_data_reg[268435460][6]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -2017,7 +1864,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 6.088ns (logic 4.010ns (65.856%) route 2.079ns (34.144%)) + Data Path Delay: 6.494ns (logic 4.010ns (61.739%) route 2.485ns (38.261%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2036,24 +1883,24 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.635 -2.341 data_memory/clk_out1 - SLICE_X65Y38 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C + net (fo=18132, routed) 1.639 -2.337 data_memory/clk_out1 + SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y38 FDRE (Prop_fdre_C_Q) 0.456 -1.885 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q - net (fo=1, routed) 2.079 0.194 lopt_8 - W4 OBUF (Prop_obuf_I_O) 3.554 3.747 r bcd_control_OBUF[6]_inst/O - net (fo=0) 0.000 3.747 bcd_control[6] + SLICE_X65Y49 FDRE (Prop_fdre_C_Q) 0.456 -1.881 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q + net (fo=1, routed) 2.485 0.604 lopt_8 + W4 OBUF (Prop_obuf_I_O) 3.554 4.157 r bcd_control_OBUF[6]_inst/O + net (fo=0) 0.000 4.157 bcd_control[6] W4 r bcd_control[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: data_memory/memory_data_reg[268435460][10]_lopt_replica/C + Source: data_memory/memory_data_reg[268435460][0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[10] + Destination: bcd_control[0] (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 6.059ns (logic 4.000ns (66.015%) route 2.059ns (33.985%)) + Data Path Delay: 6.309ns (logic 3.997ns (63.348%) route 2.313ns (36.652%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2072,14 +1919,194 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.638 -2.338 data_memory/clk_out1 - SLICE_X65Y46 FDRE r data_memory/memory_data_reg[268435460][10]_lopt_replica/C + net (fo=18132, routed) 1.572 -2.404 data_memory/clk_out1 + SLICE_X53Y49 FDRE r data_memory/memory_data_reg[268435460][0]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y46 FDRE (Prop_fdre_C_Q) 0.456 -1.882 r data_memory/memory_data_reg[268435460][10]_lopt_replica/Q - net (fo=1, routed) 2.059 0.177 lopt_1 - P2 OBUF (Prop_obuf_I_O) 3.544 3.721 r bcd_control_OBUF[10]_inst/O - net (fo=0) 0.000 3.721 bcd_control[10] - P2 r bcd_control[10] (OUT) + SLICE_X53Y49 FDRE (Prop_fdre_C_Q) 0.456 -1.948 r data_memory/memory_data_reg[268435460][0]_lopt_replica/Q + net (fo=1, routed) 2.313 0.365 lopt + N2 OBUF (Prop_obuf_I_O) 3.541 3.906 r bcd_control_OBUF[0]_inst/O + net (fo=0) 0.000 3.906 bcd_control[0] + N2 r bcd_control[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][9]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[9] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 6.009ns (logic 4.152ns (69.110%) route 1.856ns (30.890%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.625 -2.351 data_memory/clk_out1 + SLICE_X65Y57 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y57 FDRE (Prop_fdre_C_Q) 0.419 -1.932 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q + net (fo=1, routed) 1.856 -0.076 lopt_11 + R1 OBUF (Prop_obuf_I_O) 3.733 3.657 r bcd_control_OBUF[9]_inst/O + net (fo=0) 0.000 3.657 bcd_control[9] + R1 r bcd_control[9] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][11]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[11] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 5.990ns (logic 3.992ns (66.644%) route 1.998ns (33.356%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.625 -2.351 data_memory/clk_out1 + SLICE_X65Y57 FDRE r data_memory/memory_data_reg[268435460][11]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y57 FDRE (Prop_fdre_C_Q) 0.456 -1.895 r data_memory/memory_data_reg[268435460][11]_lopt_replica/Q + net (fo=1, routed) 1.998 0.103 lopt_2 + M2 OBUF (Prop_obuf_I_O) 3.536 3.639 r bcd_control_OBUF[11]_inst/O + net (fo=0) 0.000 3.639 bcd_control[11] + M2 r bcd_control[11] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][5]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[5] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 5.957ns (logic 4.149ns (69.644%) route 1.808ns (30.356%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.625 -2.351 data_memory/clk_out1 + SLICE_X65Y57 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y57 FDRE (Prop_fdre_C_Q) 0.419 -1.932 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q + net (fo=1, routed) 1.808 -0.124 lopt_7 + P1 OBUF (Prop_obuf_I_O) 3.730 3.606 r bcd_control_OBUF[5]_inst/O + net (fo=0) 0.000 3.606 bcd_control[5] + P1 r bcd_control[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][7]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[7] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 5.910ns (logic 4.006ns (67.792%) route 1.903ns (32.208%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.636 -2.340 data_memory/clk_out1 + SLICE_X65Y40 FDRE r data_memory/memory_data_reg[268435460][7]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y40 FDRE (Prop_fdre_C_Q) 0.456 -1.884 r data_memory/memory_data_reg[268435460][7]_lopt_replica/Q + net (fo=1, routed) 1.903 0.020 lopt_9 + V3 OBUF (Prop_obuf_I_O) 3.550 3.570 r bcd_control_OBUF[7]_inst/O + net (fo=0) 0.000 3.570 bcd_control[7] + V3 r bcd_control[7] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][3]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[3] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 5.912ns (logic 4.012ns (67.860%) route 1.900ns (32.140%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 1.624 -2.352 data_memory/clk_out1 + SLICE_X65Y28 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y28 FDRE (Prop_fdre_C_Q) 0.456 -1.896 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q + net (fo=1, routed) 1.900 0.004 lopt_5 + U5 OBUF (Prop_obuf_I_O) 3.556 3.560 r bcd_control_OBUF[3]_inst/O + net (fo=0) 0.000 3.560 bcd_control[3] + U5 r bcd_control[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -2089,7 +2116,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 5.732ns (logic 4.011ns (69.973%) route 1.721ns (30.027%)) + Data Path Delay: 5.903ns (logic 4.011ns (67.953%) route 1.892ns (32.047%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2108,13 +2135,13 @@ Slack: inf -8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.630 -2.346 data_memory/clk_out1 - SLICE_X65Y16 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C + net (fo=18132, routed) 1.624 -2.352 data_memory/clk_out1 + SLICE_X65Y28 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y16 FDRE (Prop_fdre_C_Q) 0.456 -1.890 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q - net (fo=1, routed) 1.721 -0.169 lopt_6 - T5 OBUF (Prop_obuf_I_O) 3.555 3.386 r bcd_control_OBUF[4]_inst/O - net (fo=0) 0.000 3.386 bcd_control[4] + SLICE_X65Y28 FDRE (Prop_fdre_C_Q) 0.456 -1.896 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q + net (fo=1, routed) 1.892 -0.004 lopt_6 + T5 OBUF (Prop_obuf_I_O) 3.555 3.551 r bcd_control_OBUF[4]_inst/O + net (fo=0) 0.000 3.551 bcd_control[4] T5 r bcd_control[4] (OUT) ------------------------------------------------------------------- ------------------- @@ -2125,13 +2152,13 @@ Slack: inf Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf - Source: data_memory/memory_data_reg[268435460][2]_lopt_replica/C + Source: data_memory/memory_data_reg[268435460][10]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[2] + Destination: bcd_control[10] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 1.697ns (logic 1.369ns (80.669%) route 0.328ns (19.331%)) + Data Path Delay: 1.714ns (logic 1.386ns (80.858%) route 0.328ns (19.142%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2150,14 +2177,50 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.590 -0.497 data_memory/clk_out1 - SLICE_X65Y16 FDRE r data_memory/memory_data_reg[268435460][2]_lopt_replica/C + net (fo=18132, routed) 0.592 -0.495 data_memory/clk_out1 + SLICE_X65Y57 FDRE r data_memory/memory_data_reg[268435460][10]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y16 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r data_memory/memory_data_reg[268435460][2]_lopt_replica/Q - net (fo=1, routed) 0.328 -0.028 lopt_4 - V5 OBUF (Prop_obuf_I_O) 1.228 1.200 r bcd_control_OBUF[2]_inst/O - net (fo=0) 0.000 1.200 bcd_control[2] - V5 r bcd_control[2] (OUT) + SLICE_X65Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r data_memory/memory_data_reg[268435460][10]_lopt_replica/Q + net (fo=1, routed) 0.328 -0.026 lopt_1 + P2 OBUF (Prop_obuf_I_O) 1.245 1.219 r bcd_control_OBUF[10]_inst/O + net (fo=0) 0.000 1.219 bcd_control[10] + P2 r bcd_control[10] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][8]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[8] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.809ns (logic 1.450ns (80.180%) route 0.358ns (19.820%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.585 -0.502 data_memory/clk_out1 + SLICE_X65Y28 FDRE r data_memory/memory_data_reg[268435460][8]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y28 FDRE (Prop_fdre_C_Q) 0.128 -0.374 r data_memory/memory_data_reg[268435460][8]_lopt_replica/Q + net (fo=1, routed) 0.358 -0.016 lopt_10 + Y3 OBUF (Prop_obuf_I_O) 1.322 1.306 r bcd_control_OBUF[8]_inst/O + net (fo=0) 0.000 1.306 bcd_control[8] + Y3 r bcd_control[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -2167,151 +2230,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 1.727ns (logic 1.392ns (80.615%) route 0.335ns (19.385%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.593 -0.494 data_memory/clk_out1 - SLICE_X65Y38 FDRE r data_memory/memory_data_reg[268435460][7]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][7]_lopt_replica/Q - net (fo=1, routed) 0.335 -0.018 lopt_9 - V3 OBUF (Prop_obuf_I_O) 1.251 1.233 r bcd_control_OBUF[7]_inst/O - net (fo=0) 0.000 1.233 bcd_control[7] - V3 r bcd_control[7] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][4]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[4] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.760ns (logic 1.397ns (79.361%) route 0.363ns (20.639%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.590 -0.497 data_memory/clk_out1 - SLICE_X65Y16 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y16 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q - net (fo=1, routed) 0.363 0.007 lopt_6 - T5 OBUF (Prop_obuf_I_O) 1.256 1.263 r bcd_control_OBUF[4]_inst/O - net (fo=0) 0.000 1.263 bcd_control[4] - T5 r bcd_control[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][10]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[10] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.885ns (logic 1.386ns (73.515%) route 0.499ns (26.485%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.595 -0.492 data_memory/clk_out1 - SLICE_X65Y46 FDRE r data_memory/memory_data_reg[268435460][10]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y46 FDRE (Prop_fdre_C_Q) 0.141 -0.351 r data_memory/memory_data_reg[268435460][10]_lopt_replica/Q - net (fo=1, routed) 0.499 0.148 lopt_1 - P2 OBUF (Prop_obuf_I_O) 1.245 1.393 r bcd_control_OBUF[10]_inst/O - net (fo=0) 0.000 1.393 bcd_control[10] - P2 r bcd_control[10] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][6]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[6] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.887ns (logic 1.395ns (73.937%) route 0.492ns (26.063%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.593 -0.494 data_memory/clk_out1 - SLICE_X65Y38 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q - net (fo=1, routed) 0.492 0.139 lopt_8 - W4 OBUF (Prop_obuf_I_O) 1.254 1.393 r bcd_control_OBUF[6]_inst/O - net (fo=0) 0.000 1.393 bcd_control[6] - W4 r bcd_control[6] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: data_memory/memory_data_reg[268435460][1]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: bcd_control[1] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 1.902ns (logic 1.376ns (72.357%) route 0.526ns (27.643%)) + Data Path Delay: 1.808ns (logic 1.392ns (77.015%) route 0.415ns (22.985%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2331,13 +2250,13 @@ Slack: inf net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O net (fo=18132, routed) 0.594 -0.493 data_memory/clk_out1 - SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][1]_lopt_replica/C + SLICE_X65Y40 FDRE r data_memory/memory_data_reg[268435460][7]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][1]_lopt_replica/Q - net (fo=1, routed) 0.526 0.174 lopt_3 - P5 OBUF (Prop_obuf_I_O) 1.235 1.409 r bcd_control_OBUF[1]_inst/O - net (fo=0) 0.000 1.409 bcd_control[1] - P5 r bcd_control[1] (OUT) + SLICE_X65Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][7]_lopt_replica/Q + net (fo=1, routed) 0.415 0.063 lopt_9 + V3 OBUF (Prop_obuf_I_O) 1.251 1.314 r bcd_control_OBUF[7]_inst/O + net (fo=0) 0.000 1.314 bcd_control[7] + V3 r bcd_control[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -2347,7 +2266,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 1.987ns (logic 1.400ns (70.452%) route 0.587ns (29.548%)) + Data Path Delay: 1.830ns (logic 1.440ns (78.666%) route 0.390ns (21.334%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2366,16 +2285,52 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.594 -0.493 data_memory/clk_out1 - SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C + net (fo=18132, routed) 0.592 -0.495 data_memory/clk_out1 + SLICE_X65Y57 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q - net (fo=1, routed) 0.587 0.235 lopt_7 - P1 OBUF (Prop_obuf_I_O) 1.259 1.493 r bcd_control_OBUF[5]_inst/O - net (fo=0) 0.000 1.493 bcd_control[5] + SLICE_X65Y57 FDRE (Prop_fdre_C_Q) 0.128 -0.367 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q + net (fo=1, routed) 0.390 0.023 lopt_7 + P1 OBUF (Prop_obuf_I_O) 1.312 1.335 r bcd_control_OBUF[5]_inst/O + net (fo=0) 0.000 1.335 bcd_control[5] P1 r bcd_control[5] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: data_memory/memory_data_reg[268435460][4]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[4] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.846ns (logic 1.397ns (75.646%) route 0.450ns (24.354%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.585 -0.502 data_memory/clk_out1 + SLICE_X65Y28 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y28 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q + net (fo=1, routed) 0.450 0.088 lopt_6 + T5 OBUF (Prop_obuf_I_O) 1.256 1.344 r bcd_control_OBUF[4]_inst/O + net (fo=0) 0.000 1.344 bcd_control[4] + T5 r bcd_control[4] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: data_memory/memory_data_reg[268435460][3]_lopt_replica/C (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -2383,7 +2338,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.034ns (logic 1.397ns (68.715%) route 0.636ns (31.285%)) + Data Path Delay: 1.846ns (logic 1.397ns (75.680%) route 0.449ns (24.320%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2402,13 +2357,13 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.553 -0.534 data_memory/clk_out1 - SLICE_X51Y24 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C + net (fo=18132, routed) 0.585 -0.502 data_memory/clk_out1 + SLICE_X65Y28 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X51Y24 FDRE (Prop_fdre_C_Q) 0.141 -0.393 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q - net (fo=1, routed) 0.636 0.243 lopt_5 - U5 OBUF (Prop_obuf_I_O) 1.256 1.499 r bcd_control_OBUF[3]_inst/O - net (fo=0) 0.000 1.499 bcd_control[3] + SLICE_X65Y28 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q + net (fo=1, routed) 0.449 0.088 lopt_5 + U5 OBUF (Prop_obuf_I_O) 1.256 1.344 r bcd_control_OBUF[3]_inst/O + net (fo=0) 0.000 1.344 bcd_control[3] U5 r bcd_control[3] (OUT) ------------------------------------------------------------------- ------------------- @@ -2419,7 +2374,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.044ns (logic 1.402ns (68.602%) route 0.642ns (31.398%)) + Data Path Delay: 1.853ns (logic 1.442ns (77.818%) route 0.411ns (22.182%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2438,13 +2393,13 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.594 -0.493 data_memory/clk_out1 - SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C + net (fo=18132, routed) 0.592 -0.495 data_memory/clk_out1 + SLICE_X65Y57 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q - net (fo=1, routed) 0.642 0.289 lopt_11 - R1 OBUF (Prop_obuf_I_O) 1.261 1.551 r bcd_control_OBUF[9]_inst/O - net (fo=0) 0.000 1.551 bcd_control[9] + SLICE_X65Y57 FDRE (Prop_fdre_C_Q) 0.128 -0.367 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q + net (fo=1, routed) 0.411 0.044 lopt_11 + R1 OBUF (Prop_obuf_I_O) 1.314 1.358 r bcd_control_OBUF[9]_inst/O + net (fo=0) 0.000 1.358 bcd_control[9] R1 r bcd_control[9] (OUT) ------------------------------------------------------------------- ------------------- @@ -2455,7 +2410,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.108ns (logic 1.378ns (65.371%) route 0.730ns (34.629%)) + Data Path Delay: 1.860ns (logic 1.378ns (74.081%) route 0.482ns (25.919%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -2474,16 +2429,88 @@ Slack: inf -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.594 -0.493 data_memory/clk_out1 - SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][11]_lopt_replica/C + net (fo=18132, routed) 0.592 -0.495 data_memory/clk_out1 + SLICE_X65Y57 FDRE r data_memory/memory_data_reg[268435460][11]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][11]_lopt_replica/Q - net (fo=1, routed) 0.730 0.378 lopt_2 - M2 OBUF (Prop_obuf_I_O) 1.237 1.615 r bcd_control_OBUF[11]_inst/O - net (fo=0) 0.000 1.615 bcd_control[11] + SLICE_X65Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r data_memory/memory_data_reg[268435460][11]_lopt_replica/Q + net (fo=1, routed) 0.482 0.128 lopt_2 + M2 OBUF (Prop_obuf_I_O) 1.237 1.365 r bcd_control_OBUF[11]_inst/O + net (fo=0) 0.000 1.365 bcd_control[11] M2 r bcd_control[11] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: data_memory/memory_data_reg[268435460][0]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.033ns (logic 1.383ns (68.006%) route 0.651ns (31.994%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.567 -0.520 data_memory/clk_out1 + SLICE_X53Y49 FDRE r data_memory/memory_data_reg[268435460][0]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.379 r data_memory/memory_data_reg[268435460][0]_lopt_replica/Q + net (fo=1, routed) 0.651 0.271 lopt + N2 OBUF (Prop_obuf_I_O) 1.242 1.513 r bcd_control_OBUF[0]_inst/O + net (fo=0) 0.000 1.513 bcd_control[0] + N2 r bcd_control[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: data_memory/memory_data_reg[268435460][6]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: bcd_control[6] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.071ns (logic 1.395ns (67.368%) route 0.676ns (32.632%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.596 -0.491 data_memory/clk_out1 + SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.350 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q + net (fo=1, routed) 0.676 0.326 lopt_8 + W4 OBUF (Prop_obuf_I_O) 1.254 1.580 r bcd_control_OBUF[6]_inst/O + net (fo=0) 0.000 1.580 bcd_control[6] + W4 r bcd_control[6] (OUT) + ------------------------------------------------------------------- ------------------- + @@ -2585,14 +2612,14 @@ Max Delay Paths Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435704][15]/R + Destination: data_memory/memory_data_reg[268435868][14]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.011ns (logic 1.650ns (10.304%) route 14.362ns (89.696%)) + Data Path Delay: 16.057ns (logic 1.650ns (10.274%) route 14.408ns (89.726%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.858ns + Clock Path Skew: -1.791ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2605,10 +2632,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 9.503 16.011 data_memory/reset - SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][15]/R + net (fo=2, routed) 4.841 6.367 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.491 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.567 16.057 data_memory/reset + SLICE_X3Y138 FDRE r data_memory/memory_data_reg[268435868][14]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2621,20 +2648,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1 - SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][15]/C + net (fo=18132, routed) 1.680 -1.791 data_memory/clk_out1 + SLICE_X3Y138 FDRE r data_memory/memory_data_reg[268435868][14]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435704][20]/R + Destination: data_memory/memory_data_reg[268435868][5]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.011ns (logic 1.650ns (10.304%) route 14.362ns (89.696%)) + Data Path Delay: 16.057ns (logic 1.650ns (10.274%) route 14.408ns (89.726%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.858ns + Clock Path Skew: -1.791ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2647,10 +2674,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 9.503 16.011 data_memory/reset - SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][20]/R + net (fo=2, routed) 4.841 6.367 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.491 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.567 16.057 data_memory/reset + SLICE_X3Y138 FDRE r data_memory/memory_data_reg[268435868][5]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2663,20 +2690,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1 - SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][20]/C + net (fo=18132, routed) 1.680 -1.791 data_memory/clk_out1 + SLICE_X3Y138 FDRE r data_memory/memory_data_reg[268435868][5]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435704][26]/R + Destination: data_memory/memory_data_reg[268435845][3]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.011ns (logic 1.650ns (10.304%) route 14.362ns (89.696%)) + Data Path Delay: 16.034ns (logic 1.650ns (10.289%) route 14.384ns (89.711%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.858ns + Clock Path Skew: -1.790ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.790ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2689,10 +2716,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 9.503 16.011 data_memory/reset - SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][26]/R + net (fo=2, routed) 4.841 6.367 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.491 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.543 16.034 data_memory/reset + SLICE_X3Y139 FDRE r data_memory/memory_data_reg[268435845][3]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2705,20 +2732,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1 - SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][26]/C + net (fo=18132, routed) 1.681 -1.790 data_memory/clk_out1 + SLICE_X3Y139 FDRE r data_memory/memory_data_reg[268435845][3]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435653][20]/R + Destination: data_memory/memory_data_reg[268435852][1]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.011ns (logic 1.650ns (10.304%) route 14.361ns (89.696%)) + Data Path Delay: 15.948ns (logic 1.650ns (10.345%) route 14.298ns (89.655%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.857ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.857ns + Clock Path Skew: -1.791ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2731,10 +2758,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 9.503 16.011 data_memory/reset - SLICE_X16Y144 FDRE r data_memory/memory_data_reg[268435653][20]/R + net (fo=2, routed) 4.841 6.367 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.491 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.457 15.948 data_memory/reset + SLICE_X5Y139 FDRE r data_memory/memory_data_reg[268435852][1]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2747,20 +2774,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.614 -1.857 data_memory/clk_out1 - SLICE_X16Y144 FDRE r data_memory/memory_data_reg[268435653][20]/C + net (fo=18132, routed) 1.680 -1.791 data_memory/clk_out1 + SLICE_X5Y139 FDRE r data_memory/memory_data_reg[268435852][1]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435680][23]/R + Destination: data_memory/memory_data_reg[268435852][3]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.010ns (logic 1.650ns (10.304%) route 14.360ns (89.696%)) + Data Path Delay: 15.948ns (logic 1.650ns (10.345%) route 14.298ns (89.655%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.859ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.859ns + Clock Path Skew: -1.791ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2773,10 +2800,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 9.502 16.010 data_memory/reset - SLICE_X11Y138 FDRE r data_memory/memory_data_reg[268435680][23]/R + net (fo=2, routed) 4.841 6.367 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.491 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.457 15.948 data_memory/reset + SLICE_X5Y139 FDRE r data_memory/memory_data_reg[268435852][3]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2789,20 +2816,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.612 -1.859 data_memory/clk_out1 - SLICE_X11Y138 FDRE r data_memory/memory_data_reg[268435680][23]/C + net (fo=18132, routed) 1.680 -1.791 data_memory/clk_out1 + SLICE_X5Y139 FDRE r data_memory/memory_data_reg[268435852][3]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435680][25]/R + Destination: data_memory/memory_data_reg[268435841][3]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.010ns (logic 1.650ns (10.304%) route 14.360ns (89.696%)) + Data Path Delay: 15.919ns (logic 1.650ns (10.363%) route 14.269ns (89.637%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.859ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.859ns + Clock Path Skew: -1.792ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2815,10 +2842,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 9.502 16.010 data_memory/reset - SLICE_X11Y138 FDRE r data_memory/memory_data_reg[268435680][25]/R + net (fo=2, routed) 4.841 6.367 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.491 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.428 15.919 data_memory/reset + SLICE_X2Y137 FDRE r data_memory/memory_data_reg[268435841][3]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2831,20 +2858,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.612 -1.859 data_memory/clk_out1 - SLICE_X11Y138 FDRE r data_memory/memory_data_reg[268435680][25]/C + net (fo=18132, routed) 1.679 -1.792 data_memory/clk_out1 + SLICE_X2Y137 FDRE r data_memory/memory_data_reg[268435841][3]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435685][23]/R + Destination: data_memory/memory_data_reg[268435871][11]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.010ns (logic 1.650ns (10.304%) route 14.360ns (89.696%)) + Data Path Delay: 15.919ns (logic 1.650ns (10.363%) route 14.269ns (89.637%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.859ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.859ns + Clock Path Skew: -1.792ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2857,10 +2884,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 9.502 16.010 data_memory/reset - SLICE_X10Y138 FDRE r data_memory/memory_data_reg[268435685][23]/R + net (fo=2, routed) 4.841 6.367 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.491 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.428 15.919 data_memory/reset + SLICE_X3Y137 FDRE r data_memory/memory_data_reg[268435871][11]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2873,20 +2900,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.612 -1.859 data_memory/clk_out1 - SLICE_X10Y138 FDRE r data_memory/memory_data_reg[268435685][23]/C + net (fo=18132, routed) 1.679 -1.792 data_memory/clk_out1 + SLICE_X3Y137 FDRE r data_memory/memory_data_reg[268435871][11]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435685][25]/R + Destination: data_memory/memory_data_reg[268435871][14]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.010ns (logic 1.650ns (10.304%) route 14.360ns (89.696%)) + Data Path Delay: 15.919ns (logic 1.650ns (10.363%) route 14.269ns (89.637%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.859ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.859ns + Clock Path Skew: -1.792ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2899,10 +2926,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 9.502 16.010 data_memory/reset - SLICE_X10Y138 FDRE r data_memory/memory_data_reg[268435685][25]/R + net (fo=2, routed) 4.841 6.367 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.491 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.428 15.919 data_memory/reset + SLICE_X3Y137 FDRE r data_memory/memory_data_reg[268435871][14]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2915,20 +2942,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.612 -1.859 data_memory/clk_out1 - SLICE_X10Y138 FDRE r data_memory/memory_data_reg[268435685][25]/C + net (fo=18132, routed) 1.679 -1.792 data_memory/clk_out1 + SLICE_X3Y137 FDRE r data_memory/memory_data_reg[268435871][14]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435705][15]/R + Destination: data_memory/memory_data_reg[268435871][5]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.007ns (logic 1.650ns (10.306%) route 14.357ns (89.694%)) + Data Path Delay: 15.919ns (logic 1.650ns (10.363%) route 14.269ns (89.637%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.858ns + Clock Path Skew: -1.792ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2941,10 +2968,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 9.499 16.007 data_memory/reset - SLICE_X23Y143 FDRE r data_memory/memory_data_reg[268435705][15]/R + net (fo=2, routed) 4.841 6.367 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.491 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.428 15.919 data_memory/reset + SLICE_X3Y137 FDRE r data_memory/memory_data_reg[268435871][5]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2957,20 +2984,20 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1 - SLICE_X23Y143 FDRE r data_memory/memory_data_reg[268435705][15]/C + net (fo=18132, routed) 1.679 -1.792 data_memory/clk_out1 + SLICE_X3Y137 FDRE r data_memory/memory_data_reg[268435871][5]/C Slack: inf Source: hardware_reset (input port) - Destination: data_memory/memory_data_reg[268435705][20]/R + Destination: data_memory/memory_data_reg[268435854][3]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 16.007ns (logic 1.650ns (10.306%) route 14.357ns (89.694%)) + Data Path Delay: 15.907ns (logic 1.650ns (10.371%) route 14.258ns (89.629%)) Logic Levels: 2 (IBUF=1 LUT2=1) - Clock Path Skew: -1.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.858ns + Clock Path Skew: -1.791ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -2983,10 +3010,10 @@ Slack: inf B22 0.000 0.000 r hardware_reset (IN) net (fo=0) 0.000 0.000 hardware_reset B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O - net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0 - SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 9.499 16.007 data_memory/reset - SLICE_X23Y143 FDRE r data_memory/memory_data_reg[268435705][20]/R + net (fo=2, routed) 4.841 6.367 data_memory/memory_data_reg[268435457][0]_0 + SLICE_X65Y47 LUT2 (Prop_lut2_I0_O) 0.124 6.491 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 9.417 15.907 data_memory/reset + SLICE_X4Y140 FDRE r data_memory/memory_data_reg[268435854][3]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -2999,8 +3026,8 @@ Slack: inf -7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1 - SLICE_X23Y143 FDRE r data_memory/memory_data_reg[268435705][20]/C + net (fo=18132, routed) 1.680 -1.791 data_memory/clk_out1 + SLICE_X4Y140 FDRE r data_memory/memory_data_reg[268435854][3]/C @@ -3011,11 +3038,11 @@ Min Delay Paths Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435474][6]/R + Destination: data_memory/memory_data_reg[268435486][4]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.947ns (logic 0.045ns (4.750%) route 0.902ns (95.250%)) + Data Path Delay: 1.085ns (logic 0.045ns (4.146%) route 1.040ns (95.854%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3025,10 +3052,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.377 0.377 data_memory/locked - SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 0.525 0.947 data_memory/reset - SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435474][6]/R + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.647 1.085 data_memory/reset + SLICE_X59Y47 FDRE r data_memory/memory_data_reg[268435486][4]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3041,17 +3068,17 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435474][6]/C + net (fo=18132, routed) 0.865 -0.261 data_memory/clk_out1 + SLICE_X59Y47 FDRE r data_memory/memory_data_reg[268435486][4]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435475][6]/R + Destination: data_memory/memory_data_reg[268435528][10]/R (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.947ns (logic 0.045ns (4.750%) route 0.902ns (95.250%)) + Data Path Delay: 1.090ns (logic 0.045ns (4.129%) route 1.045ns (95.871%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3061,10 +3088,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.377 0.377 data_memory/locked - SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 0.525 0.947 data_memory/reset - SLICE_X64Y49 FDRE r data_memory/memory_data_reg[268435475][6]/R + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.651 1.090 data_memory/reset + SLICE_X58Y47 FDRE r data_memory/memory_data_reg[268435528][10]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3077,17 +3104,269 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X64Y49 FDRE r data_memory/memory_data_reg[268435475][6]/C + net (fo=18132, routed) 0.865 -0.261 data_memory/clk_out1 + SLICE_X58Y47 FDRE r data_memory/memory_data_reg[268435528][10]/C Slack: inf Source: pll/inst/plle2_adv_inst/LOCKED (internal pin) - Destination: data_memory/memory_data_reg[268435485][6]/S + Destination: data_memory/memory_data_reg[268435528][4]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.090ns (logic 0.045ns (4.129%) route 1.045ns (95.871%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.651 1.090 data_memory/reset + SLICE_X58Y47 FDRE r data_memory/memory_data_reg[268435528][4]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.865 -0.261 data_memory/clk_out1 + SLICE_X58Y47 FDRE r data_memory/memory_data_reg[268435528][4]/C + +Slack: inf + Source: pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: data_memory/memory_data_reg[268435528][7]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.090ns (logic 0.045ns (4.129%) route 1.045ns (95.871%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.651 1.090 data_memory/reset + SLICE_X58Y47 FDRE r data_memory/memory_data_reg[268435528][7]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.865 -0.261 data_memory/clk_out1 + SLICE_X58Y47 FDRE r data_memory/memory_data_reg[268435528][7]/C + +Slack: inf + Source: pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: data_memory/memory_data_reg[268435528][9]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.090ns (logic 0.045ns (4.129%) route 1.045ns (95.871%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.651 1.090 data_memory/reset + SLICE_X58Y47 FDRE r data_memory/memory_data_reg[268435528][9]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.865 -0.261 data_memory/clk_out1 + SLICE_X58Y47 FDRE r data_memory/memory_data_reg[268435528][9]/C + +Slack: inf + Source: pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: data_memory/memory_data_reg[268435475][4]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.119ns (logic 0.045ns (4.022%) route 1.074ns (95.978%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.680 1.119 data_memory/reset + SLICE_X65Y45 FDRE r data_memory/memory_data_reg[268435475][4]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.866 -0.260 data_memory/clk_out1 + SLICE_X65Y45 FDRE r data_memory/memory_data_reg[268435475][4]/C + +Slack: inf + Source: pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: data_memory/memory_data_reg[268435529][10]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.119ns (logic 0.045ns (4.022%) route 1.074ns (95.978%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.680 1.119 data_memory/reset + SLICE_X64Y45 FDRE r data_memory/memory_data_reg[268435529][10]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.866 -0.260 data_memory/clk_out1 + SLICE_X64Y45 FDRE r data_memory/memory_data_reg[268435529][10]/C + +Slack: inf + Source: pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: data_memory/memory_data_reg[268435529][7]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.119ns (logic 0.045ns (4.022%) route 1.074ns (95.978%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.680 1.119 data_memory/reset + SLICE_X64Y45 FDRE r data_memory/memory_data_reg[268435529][7]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.866 -0.260 data_memory/clk_out1 + SLICE_X64Y45 FDRE r data_memory/memory_data_reg[268435529][7]/C + +Slack: inf + Source: pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: data_memory/memory_data_reg[268435520][10]/R + (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.167ns (logic 0.045ns (3.857%) route 1.122ns (96.143%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.203ns + Phase Error (PE): 0.156ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.728 1.167 data_memory/reset + SLICE_X60Y46 FDRE r data_memory/memory_data_reg[268435520][10]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_phase_locked_loop rise edge) + 0.000 0.000 r + R4 0.000 0.000 r hardware_clk (IN) + net (fo=0) 0.000 0.000 pll/inst/clk_in1 + R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop + PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O + net (fo=18132, routed) 0.864 -0.262 data_memory/clk_out1 + SLICE_X60Y46 FDRE r data_memory/memory_data_reg[268435520][10]/C + +Slack: inf + Source: pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: data_memory/memory_data_reg[268435520][4]/S (rising edge-triggered cell FDSE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.980ns (logic 0.045ns (4.590%) route 0.935ns (95.410%)) + Data Path Delay: 1.167ns (logic 0.045ns (3.857%) route 1.122ns (96.143%)) Logic Levels: 1 (LUT2=1) Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -3097,10 +3376,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.377 0.377 data_memory/locked - SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 0.558 0.980 data_memory/reset - SLICE_X63Y49 FDSE r data_memory/memory_data_reg[268435485][6]/S + net (fo=2, routed) 0.394 0.394 data_memory/locked + SLICE_X65Y47 LUT2 (Prop_lut2_I1_O) 0.045 0.439 r data_memory/memory_data[268435967][31]_i_1/O + net (fo=17907, routed) 0.728 1.167 data_memory/reset + SLICE_X60Y46 FDSE r data_memory/memory_data_reg[268435520][4]/S ------------------------------------------------------------------- ------------------- (clock clk_out1_phase_locked_loop rise edge) @@ -3113,260 +3392,8 @@ Slack: inf -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X63Y49 FDSE r data_memory/memory_data_reg[268435485][6]/C - -Slack: inf - Source: pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: data_memory/memory_data_reg[268435524][21]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%)) - Logic Levels: 1 (LUT2=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.377 0.377 data_memory/locked - SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 0.562 0.985 data_memory/reset - SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][21]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][21]/C - -Slack: inf - Source: pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: data_memory/memory_data_reg[268435524][23]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%)) - Logic Levels: 1 (LUT2=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.377 0.377 data_memory/locked - SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 0.562 0.985 data_memory/reset - SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][23]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][23]/C - -Slack: inf - Source: pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: data_memory/memory_data_reg[268435524][28]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%)) - Logic Levels: 1 (LUT2=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.377 0.377 data_memory/locked - SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 0.562 0.985 data_memory/reset - SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][28]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][28]/C - -Slack: inf - Source: pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: data_memory/memory_data_reg[268435524][29]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%)) - Logic Levels: 1 (LUT2=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.377 0.377 data_memory/locked - SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 0.562 0.985 data_memory/reset - SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][29]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][29]/C - -Slack: inf - Source: pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: data_memory/memory_data_reg[268435524][6]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%)) - Logic Levels: 1 (LUT2=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.377 0.377 data_memory/locked - SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 0.562 0.985 data_memory/reset - SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][6]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1 - SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][6]/C - -Slack: inf - Source: pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: data_memory/memory_data_reg[268435478][6]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.011ns (logic 0.045ns (4.451%) route 0.966ns (95.549%)) - Logic Levels: 1 (LUT2=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.377 0.377 data_memory/locked - SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 0.589 1.011 data_memory/reset - SLICE_X65Y51 FDRE r data_memory/memory_data_reg[268435478][6]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.864 -0.261 data_memory/clk_out1 - SLICE_X65Y51 FDRE r data_memory/memory_data_reg[268435478][6]/C - -Slack: inf - Source: pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: data_memory/memory_data_reg[268435480][6]/R - (rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.011ns (logic 0.045ns (4.451%) route 0.966ns (95.549%)) - Logic Levels: 1 (LUT2=1) - Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.203ns - Phase Error (PE): 0.156ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED - net (fo=2, routed) 0.377 0.377 data_memory/locked - SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O - net (fo=17907, routed) 0.589 1.011 data_memory/reset - SLICE_X64Y51 FDRE r data_memory/memory_data_reg[268435480][6]/R - ------------------------------------------------------------------- ------------------- - - (clock clk_out1_phase_locked_loop rise edge) - 0.000 0.000 r - R4 0.000 0.000 r hardware_clk (IN) - net (fo=0) 0.000 0.000 pll/inst/clk_in1 - R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop - PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop - BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O - net (fo=18132, routed) 0.864 -0.261 data_memory/clk_out1 - SLICE_X64Y51 FDRE r data_memory/memory_data_reg[268435480][6]/C + net (fo=18132, routed) 0.864 -0.262 data_memory/clk_out1 + SLICE_X60Y46 FDSE r data_memory/memory_data_reg[268435520][4]/C diff --git a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb index 64ad7a4..ae865f0 100644 Binary files a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb and b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb differ diff --git a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt index 7680db3..0f3fec7 100644 --- a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt +++ b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 14:28:53 2024 +| Date : Sat Jul 13 23:40:17 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb | Design : CPU @@ -32,13 +32,13 @@ Table of Contents +-------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------------+-------+-------+------------+-----------+-------+ -| Slice LUTs | 8337 | 0 | 0 | 20800 | 40.08 | -| LUT as Logic | 8337 | 0 | 0 | 20800 | 40.08 | +| Slice LUTs | 8344 | 0 | 0 | 20800 | 40.12 | +| LUT as Logic | 8344 | 0 | 0 | 20800 | 40.12 | | LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | | Slice Registers | 18132 | 0 | 0 | 41600 | 43.59 | | Register as Flip Flop | 18132 | 0 | 0 | 41600 | 43.59 | | Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | -| F7 Muxes | 2373 | 0 | 0 | 16300 | 14.56 | +| F7 Muxes | 2377 | 0 | 0 | 16300 | 14.58 | | F8 Muxes | 1088 | 0 | 0 | 8150 | 13.35 | +-------------------------+-------+-------+------------+-----------+-------+ * Warning! LUT value is adjusted to account for LUT combining. @@ -69,21 +69,21 @@ Table of Contents +--------------------------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +--------------------------------------------+-------+-------+------------+-----------+-------+ -| Slice | 7477 | 0 | 0 | 8150 | 91.74 | -| SLICEL | 5277 | 0 | | | | -| SLICEM | 2200 | 0 | | | | -| LUT as Logic | 8337 | 0 | 0 | 20800 | 40.08 | +| Slice | 7058 | 0 | 0 | 8150 | 86.60 | +| SLICEL | 4944 | 0 | | | | +| SLICEM | 2114 | 0 | | | | +| LUT as Logic | 8344 | 0 | 0 | 20800 | 40.12 | | using O5 output only | 0 | | | | | -| using O6 output only | 8032 | | | | | -| using O5 and O6 | 305 | | | | | +| using O6 output only | 8043 | | | | | +| using O5 and O6 | 301 | | | | | | LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | | LUT as Distributed RAM | 0 | 0 | | | | | LUT as Shift Register | 0 | 0 | | | | | Slice Registers | 18132 | 0 | 0 | 41600 | 43.59 | -| Register driven from within the Slice | 1478 | | | | | -| Register driven from outside the Slice | 16654 | | | | | -| LUT in front of the register is unused | 14681 | | | | | -| LUT in front of the register is used | 1973 | | | | | +| Register driven from within the Slice | 1461 | | | | | +| Register driven from outside the Slice | 16671 | | | | | +| LUT in front of the register is unused | 14188 | | | | | +| LUT in front of the register is used | 2483 | | | | | | Unique Control Sets | 547 | | 0 | 8150 | 6.71 | +--------------------------------------------+-------+-------+------------+-----------+-------+ * * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. @@ -181,14 +181,14 @@ Table of Contents | Ref Name | Used | Functional Category | +-----------+-------+---------------------+ | FDRE | 17764 | Flop & Latch | -| LUT6 | 7147 | LUT | -| MUXF7 | 2373 | MuxFx | +| LUT6 | 7154 | LUT | +| MUXF7 | 2377 | MuxFx | | MUXF8 | 1088 | MuxFx | -| LUT5 | 831 | LUT | +| LUT5 | 825 | LUT | | FDSE | 368 | Flop & Latch | -| LUT4 | 279 | LUT | -| LUT3 | 229 | LUT | -| LUT2 | 155 | LUT | +| LUT4 | 281 | LUT | +| LUT3 | 230 | LUT | +| LUT2 | 154 | LUT | | CARRY4 | 39 | CarryLogic | | OBUF | 13 | IO | | DSP48E1 | 3 | Block Arithmetic | diff --git a/PipelineProcessor.runs/impl_1/clockInfo.txt b/PipelineProcessor.runs/impl_1/clockInfo.txt index 9b4b1e8..7332a57 100644 --- a/PipelineProcessor.runs/impl_1/clockInfo.txt +++ b/PipelineProcessor.runs/impl_1/clockInfo.txt @@ -1,6 +1,6 @@ ------------------------------------- | Tool Version : Vivado v.2023.2 -| Date : Sat Jul 13 14:28:25 2024 +| Date : Sat Jul 13 23:39:48 2024 | Host : Viviana | Design : design_1 | Device : xc7a35t-fgg484-1-- diff --git a/PipelineProcessor.runs/impl_1/init_design.pb b/PipelineProcessor.runs/impl_1/init_design.pb index 3ed00e2..6d9f538 100644 Binary files a/PipelineProcessor.runs/impl_1/init_design.pb and b/PipelineProcessor.runs/impl_1/init_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/opt_design.pb b/PipelineProcessor.runs/impl_1/opt_design.pb index 64b06e0..0f94a63 100644 Binary files a/PipelineProcessor.runs/impl_1/opt_design.pb and b/PipelineProcessor.runs/impl_1/opt_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/phys_opt_design.pb b/PipelineProcessor.runs/impl_1/phys_opt_design.pb index 9393ab6..44cc91b 100644 Binary files a/PipelineProcessor.runs/impl_1/phys_opt_design.pb and b/PipelineProcessor.runs/impl_1/phys_opt_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/place_design.pb b/PipelineProcessor.runs/impl_1/place_design.pb index fd3e7a2..94126a3 100644 Binary files a/PipelineProcessor.runs/impl_1/place_design.pb and b/PipelineProcessor.runs/impl_1/place_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/route_design.pb b/PipelineProcessor.runs/impl_1/route_design.pb index 89b309a..d0fa912 100644 Binary files a/PipelineProcessor.runs/impl_1/route_design.pb and b/PipelineProcessor.runs/impl_1/route_design.pb differ diff --git a/PipelineProcessor.runs/impl_1/vivado.jou b/PipelineProcessor.runs/impl_1/vivado.jou index 0d49340..1e08ae5 100644 --- a/PipelineProcessor.runs/impl_1/vivado.jou +++ b/PipelineProcessor.runs/impl_1/vivado.jou @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Sat Jul 13 14:27:36 2024 -# Process ID: 19592 +# Start of session at: Sat Jul 13 23:39:15 2024 +# Process ID: 27020 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1 # Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi diff --git a/PipelineProcessor.runs/impl_1/vivado.pb b/PipelineProcessor.runs/impl_1/vivado.pb index 376a80f..61c3db1 100644 Binary files a/PipelineProcessor.runs/impl_1/vivado.pb and b/PipelineProcessor.runs/impl_1/vivado.pb differ diff --git a/PipelineProcessor.runs/impl_1/write_bitstream.pb b/PipelineProcessor.runs/impl_1/write_bitstream.pb index e4d2da7..736867d 100644 Binary files a/PipelineProcessor.runs/impl_1/write_bitstream.pb and b/PipelineProcessor.runs/impl_1/write_bitstream.pb differ diff --git a/PipelineProcessor.runs/synth_1/CPU.dcp b/PipelineProcessor.runs/synth_1/CPU.dcp index 2400e10..f3baa75 100644 Binary files a/PipelineProcessor.runs/synth_1/CPU.dcp and b/PipelineProcessor.runs/synth_1/CPU.dcp differ diff --git a/PipelineProcessor.runs/synth_1/CPU.tcl b/PipelineProcessor.runs/synth_1/CPU.tcl index 7e5818d..1fb0494 100644 --- a/PipelineProcessor.runs/synth_1/CPU.tcl +++ b/PipelineProcessor.runs/synth_1/CPU.tcl @@ -71,7 +71,6 @@ proc create_report { reportName command } { } OPTRACE "synth_1" START { ROLLUP_AUTO } set_param chipscope.maxJobs 5 -set_param xicom.use_bs_reader 1 OPTRACE "Creating in-memory project" START { } create_project -in_memory -part xc7a35tfgg484-1 diff --git a/PipelineProcessor.runs/synth_1/CPU.vds b/PipelineProcessor.runs/synth_1/CPU.vds index ddec603..fd00d79 100644 --- a/PipelineProcessor.runs/synth_1/CPU.vds +++ b/PipelineProcessor.runs/synth_1/CPU.vds @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Sat Jul 13 14:22:20 2024 -# Process ID: 3472 +# Start of session at: Sat Jul 13 23:37:30 2024 +# Process ID: 27796 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1 # Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds @@ -12,7 +12,7 @@ # Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB #----------------------------------------------------------- source CPU.tcl -notrace -create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:22 . Memory (MB): peak = 463.508 ; gain = 184.387 +create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 462.984 ; gain = 184.277 Command: read_checkpoint -auto_incremental -incremental D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp INFO: [Vivado 12-5825] Read reference checkpoint from D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes @@ -25,13 +25,13 @@ INFO: [Designutils 20-5440] No compile time benefit to using incremental synthes INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 30200 +INFO: [Synth 8-7075] Helper process launched with PID 15424 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:18 . Memory (MB): peak = 1308.621 ; gain = 440.629 +Starting RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 1308.293 ; gain = 439.242 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'CPU' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/CPU.v:2] -INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-3472-Viviana/realtime/phase_locked_loop_stub.v:6] -INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-3472-Viviana/realtime/phase_locked_loop_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-27796-Viviana/realtime/phase_locked_loop_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-27796-Viviana/realtime/phase_locked_loop_stub.v:6] INFO: [Synth 8-6157] synthesizing module 'InstFetch' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstFetch.v:2] INFO: [Synth 8-6157] synthesizing module 'InstructionMemory' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3] INFO: [Synth 8-6155] done synthesizing module 'InstructionMemory' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3] @@ -66,18 +66,18 @@ WARNING: [Synth 8-7129] Port address[0] in module DataMemory is either unconnect WARNING: [Synth 8-7129] Port address[1] in module InstructionMemory is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module InstructionMemory is either unconnected or has no load --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1478.609 ; gain = 610.617 +Finished RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.973 ; gain = 609.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:30 . Memory (MB): peak = 1478.609 ; gain = 610.617 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1478.973 ; gain = 609.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:30 . Memory (MB): peak = 1478.609 ; gain = 610.617 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1478.973 ; gain = 609.922 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.793 . Memory (MB): peak = 1478.609 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.191 . Memory (MB): peak = 1478.973 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints @@ -90,22 +90,22 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi Resolution: To avoid this warning, move constraints listed in [.Xil/CPU_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1578.020 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1586.277 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.243 . Memory (MB): peak = 1578.020 ; gain = 0.000 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1586.277 ; gain = 0.000 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:01:07 . Memory (MB): peak = 1578.020 ; gain = 710.027 +Finished Constraint Validation : Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 1586.277 ; gain = 717.227 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tfgg484-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:01:07 . Memory (MB): peak = 1578.020 ; gain = 710.027 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 1586.277 ; gain = 717.227 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints @@ -114,10 +114,10 @@ Applied set_property IO_BUFFER_TYPE = NONE for hardware_clk. (constraint file d Applied set_property CLOCK_BUFFER_TYPE = NONE for hardware_clk. (constraint file d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc, line 4). Applied set_property KEEP_HIERARCHY = SOFT for pll. (constraint file auto generated constraint). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:01:07 . Memory (MB): peak = 1578.020 ; gain = 710.027 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 1586.277 ; gain = 717.227 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:01:29 . Memory (MB): peak = 1578.020 ; gain = 710.027 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:22 . Memory (MB): peak = 1586.277 ; gain = 717.227 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics @@ -173,7 +173,7 @@ DSP Report: Generating DSP alu/result0, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator alu/result0 is absorbed into DSP alu/result0. DSP Report: operator alu/result0 is absorbed into DSP alu/result0. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:03:07 . Memory (MB): peak = 1578.020 ; gain = 710.027 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:00:44 . Memory (MB): peak = 1586.277 ; gain = 717.227 --------------------------------------------------------------------------------- Sort Area is CPU__GC0 alu/result0_0 : 0 0 : 3101 5879 : Used 1 time 0 Sort Area is CPU__GC0 alu/result0_0 : 0 1 : 2778 5879 : Used 1 time 0 @@ -209,19 +209,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:39 ; elapsed = 00:03:21 . Memory (MB): peak = 1578.020 ; gain = 710.027 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:51 . Memory (MB): peak = 1586.277 ; gain = 717.227 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:44 ; elapsed = 00:03:49 . Memory (MB): peak = 1712.805 ; gain = 844.812 +Finished Timing Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:01:07 . Memory (MB): peak = 1714.559 ; gain = 845.508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:45 ; elapsed = 00:04:00 . Memory (MB): peak = 1719.152 ; gain = 851.160 +Finished Technology Mapping : Time (s): cpu = 00:00:02 ; elapsed = 00:01:14 . Memory (MB): peak = 1720.918 ; gain = 851.867 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -239,37 +239,37 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:46 ; elapsed = 00:04:09 . Memory (MB): peak = 1719.152 ; gain = 851.160 +Finished IO Insertion : Time (s): cpu = 00:00:03 ; elapsed = 00:01:19 . Memory (MB): peak = 1720.918 ; gain = 851.867 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:46 ; elapsed = 00:04:09 . Memory (MB): peak = 1719.152 ; gain = 851.160 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:03 ; elapsed = 00:01:19 . Memory (MB): peak = 1720.918 ; gain = 851.867 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:46 ; elapsed = 00:04:12 . Memory (MB): peak = 1719.152 ; gain = 851.160 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:46 ; elapsed = 00:04:12 . Memory (MB): peak = 1719.152 ; gain = 851.160 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:46 ; elapsed = 00:04:12 . Memory (MB): peak = 1719.152 ; gain = 851.160 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:46 ; elapsed = 00:04:13 . Memory (MB): peak = 1719.152 ; gain = 851.160 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -300,12 +300,12 @@ Report Cell Usage: |2 |CARRY4 | 39| |3 |DSP48E1 | 3| |4 |LUT1 | 15| -|5 |LUT2 | 155| -|6 |LUT3 | 229| -|7 |LUT4 | 279| -|8 |LUT5 | 831| -|9 |LUT6 | 7147| -|10 |MUXF7 | 2373| +|5 |LUT2 | 154| +|6 |LUT3 | 230| +|7 |LUT4 | 281| +|8 |LUT5 | 825| +|9 |LUT6 | 7154| +|10 |MUXF7 | 2377| |11 |MUXF8 | 1088| |12 |FDRE | 17752| |13 |FDSE | 368| @@ -313,27 +313,27 @@ Report Cell Usage: |15 |OBUF | 13| +------+------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:46 ; elapsed = 00:04:13 . Memory (MB): peak = 1719.152 ; gain = 851.160 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:03:58 . Memory (MB): peak = 1719.152 ; gain = 751.750 -Synthesis Optimization Complete : Time (s): cpu = 00:00:46 ; elapsed = 00:04:13 . Memory (MB): peak = 1719.152 ; gain = 851.160 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:03 ; elapsed = 00:01:18 . Memory (MB): peak = 1720.918 ; gain = 744.562 +Synthesis Optimization Complete : Time (s): cpu = 00:00:03 ; elapsed = 00:01:22 . Memory (MB): peak = 1720.918 ; gain = 851.867 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1724.391 ; gain = 0.000 -INFO: [Netlist 29-17] Analyzing 3503 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.294 . Memory (MB): peak = 1720.918 ; gain = 0.000 +INFO: [Netlist 29-17] Analyzing 3507 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1729.113 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1720.918 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Synth Design complete | Checksum: 93dc575b +Synth Design complete | Checksum: 560bc728 INFO: [Common 17-83] Releasing license: Synthesis 51 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:51 ; elapsed = 00:04:35 . Memory (MB): peak = 1729.113 ; gain = 1252.605 -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1729.113 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:03 ; elapsed = 00:01:29 . Memory (MB): peak = 1720.918 ; gain = 1244.781 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1720.918 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 14:27:28 2024... +INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 23:39:08 2024... diff --git a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb index 6537ad0..86a535e 100644 Binary files a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb and b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb differ diff --git a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt index 861a62c..5936dd1 100644 --- a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt +++ b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 -| Date : Sat Jul 13 14:27:28 2024 +| Date : Sat Jul 13 23:39:08 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb | Design : CPU @@ -31,13 +31,13 @@ Table of Contents +-------------------------+-------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +-------------------------+-------+-------+------------+-----------+-------+ -| Slice LUTs* | 8380 | 0 | 0 | 20800 | 40.29 | -| LUT as Logic | 8380 | 0 | 0 | 20800 | 40.29 | +| Slice LUTs* | 8384 | 0 | 0 | 20800 | 40.31 | +| LUT as Logic | 8384 | 0 | 0 | 20800 | 40.31 | | LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | | Slice Registers | 18120 | 0 | 0 | 41600 | 43.56 | | Register as Flip Flop | 18120 | 0 | 0 | 41600 | 43.56 | | Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | -| F7 Muxes | 2373 | 0 | 0 | 16300 | 14.56 | +| F7 Muxes | 2377 | 0 | 0 | 16300 | 14.58 | | F8 Muxes | 1088 | 0 | 0 | 8150 | 13.35 | +-------------------------+-------+-------+------------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -153,14 +153,14 @@ Warning! LUT value is adjusted to account for LUT combining. | Ref Name | Used | Functional Category | +----------+-------+---------------------+ | FDRE | 17752 | Flop & Latch | -| LUT6 | 7147 | LUT | -| MUXF7 | 2373 | MuxFx | +| LUT6 | 7154 | LUT | +| MUXF7 | 2377 | MuxFx | | MUXF8 | 1088 | MuxFx | -| LUT5 | 831 | LUT | +| LUT5 | 825 | LUT | | FDSE | 368 | Flop & Latch | -| LUT4 | 279 | LUT | -| LUT3 | 229 | LUT | -| LUT2 | 155 | LUT | +| LUT4 | 281 | LUT | +| LUT3 | 230 | LUT | +| LUT2 | 154 | LUT | | CARRY4 | 39 | CarryLogic | | LUT1 | 15 | LUT | | OBUF | 13 | IO | diff --git a/PipelineProcessor.runs/synth_1/vivado.jou b/PipelineProcessor.runs/synth_1/vivado.jou index b13ccaf..f702d7e 100644 --- a/PipelineProcessor.runs/synth_1/vivado.jou +++ b/PipelineProcessor.runs/synth_1/vivado.jou @@ -3,8 +3,8 @@ # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Sat Jul 13 14:22:20 2024 -# Process ID: 3472 +# Start of session at: Sat Jul 13 23:37:30 2024 +# Process ID: 27796 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1 # Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds diff --git a/PipelineProcessor.runs/synth_1/vivado.pb b/PipelineProcessor.runs/synth_1/vivado.pb index fcd6e03..8786247 100644 Binary files a/PipelineProcessor.runs/synth_1/vivado.pb and b/PipelineProcessor.runs/synth_1/vivado.pb differ diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb b/PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb index c7493e1..83f391e 100644 Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb and b/PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem index ae63b48..e594de4 100644 Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem and b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem differ diff --git a/PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb b/PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb index 672bcb8..b155e40 100644 Binary files a/PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb and b/PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v index 149800d..f12dbd8 100644 --- a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v +++ b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v @@ -8,7 +8,7 @@ module InstructionMemory ( always @(*) begin case (address[31:2]) 20'd0: instruction <= 32'h3c1d4000; - 20'd1: instruction <= 32'h23bd07ff; + 20'd1: instruction <= 32'h23bd07fc; 20'd2: instruction <= 32'h3c104000; 20'd3: instruction <= 32'h22100020; 20'd4: instruction <= 32'h2011003f; @@ -43,174 +43,173 @@ module InstructionMemory ( 20'd33: instruction <= 32'hae110038; 20'd34: instruction <= 32'h20110071; 20'd35: instruction <= 32'hae11003c; - 20'd36: instruction <= 32'h0c00002a; - 20'd37: instruction <= 32'h3c084000; - 20'd38: instruction <= 32'h8d040060; - 20'd39: instruction <= 32'h0c000077; - 20'd40: instruction <= 32'h0c00002a; - 20'd41: instruction <= 32'h08000028; - 20'd42: instruction <= 32'h23bdffec; - 20'd43: instruction <= 32'hafbf0004; - 20'd44: instruction <= 32'hafb00008; - 20'd45: instruction <= 32'hafb1000c; - 20'd46: instruction <= 32'hafb20010; - 20'd47: instruction <= 32'hafb30014; - 20'd48: instruction <= 32'h3c104000; - 20'd49: instruction <= 32'h22110010; - 20'd50: instruction <= 32'h22100060; - 20'd51: instruction <= 32'h20120000; - 20'd52: instruction <= 32'h8e130000; - 20'd53: instruction <= 32'h22100004; - 20'd54: instruction <= 32'h00124080; - 20'd55: instruction <= 32'h02084020; - 20'd56: instruction <= 32'h8d040000; - 20'd57: instruction <= 32'h22250000; - 20'd58: instruction <= 32'h0c000046; - 20'd59: instruction <= 32'h22520001; - 20'd60: instruction <= 32'h02724022; - 20'd61: instruction <= 32'h1d00fff8; - 20'd62: instruction <= 32'h0c000070; - 20'd63: instruction <= 32'h8fbf0004; - 20'd64: instruction <= 32'h8fb00008; - 20'd65: instruction <= 32'h8fb1000c; - 20'd66: instruction <= 32'h8fb20010; - 20'd67: instruction <= 32'h8fb30014; - 20'd68: instruction <= 32'h23bd0014; - 20'd69: instruction <= 32'h03e00008; - 20'd70: instruction <= 32'h23bdffe0; - 20'd71: instruction <= 32'hafbf0004; - 20'd72: instruction <= 32'hafb00008; - 20'd73: instruction <= 32'hafb1000c; - 20'd74: instruction <= 32'hafb20010; - 20'd75: instruction <= 32'hafb30014; - 20'd76: instruction <= 32'hafb40018; - 20'd77: instruction <= 32'hafb5001c; - 20'd78: instruction <= 32'hafb60020; - 20'd79: instruction <= 32'h20900000; - 20'd80: instruction <= 32'h20b10000; - 20'd81: instruction <= 32'h3c124000; - 20'd82: instruction <= 32'h22520020; - 20'd83: instruction <= 32'h20130be2; - 20'd84: instruction <= 32'h22140000; - 20'd85: instruction <= 32'h20160100; - 20'd86: instruction <= 32'h20150004; - 20'd87: instruction <= 32'h3288000f; - 20'd88: instruction <= 32'h00084080; - 20'd89: instruction <= 32'h02484020; - 20'd90: instruction <= 32'h8d080000; - 20'd91: instruction <= 32'h01164025; - 20'd92: instruction <= 32'hae280000; - 20'd93: instruction <= 32'h0014a102; - 20'd94: instruction <= 32'h0016b040; - 20'd95: instruction <= 32'h20080400; - 20'd96: instruction <= 32'h2108ffff; - 20'd97: instruction <= 32'h1d00fffe; - 20'd98: instruction <= 32'h22b5ffff; - 20'd99: instruction <= 32'h1ea0fff3; - 20'd100: instruction <= 32'h2273ffff; - 20'd101: instruction <= 32'h1e60ffee; - 20'd102: instruction <= 32'h8fbf0004; - 20'd103: instruction <= 32'h8fb00008; - 20'd104: instruction <= 32'h8fb1000c; - 20'd105: instruction <= 32'h8fb20010; - 20'd106: instruction <= 32'h8fb30014; - 20'd107: instruction <= 32'h8fb40018; - 20'd108: instruction <= 32'h8fb5001c; - 20'd109: instruction <= 32'h8fb60020; - 20'd110: instruction <= 32'h23bd0020; - 20'd111: instruction <= 32'h03e00008; - 20'd112: instruction <= 32'h3c084000; - 20'd113: instruction <= 32'h21080010; - 20'd114: instruction <= 32'had000000; - 20'd115: instruction <= 32'h3c080100; - 20'd116: instruction <= 32'h2108ffff; - 20'd117: instruction <= 32'h1d00fffe; - 20'd118: instruction <= 32'h03e00008; - 20'd119: instruction <= 32'h23bdfff4; - 20'd120: instruction <= 32'hafbf0004; - 20'd121: instruction <= 32'hafb00008; - 20'd122: instruction <= 32'hafb1000c; - 20'd123: instruction <= 32'h20900000; - 20'd124: instruction <= 32'h20110001; - 20'd125: instruction <= 32'h02114022; - 20'd126: instruction <= 32'h19000009; - 20'd127: instruction <= 32'h24040000; - 20'd128: instruction <= 32'h2225ffff; - 20'd129: instruction <= 32'h00113021; - 20'd130: instruction <= 32'h0c00008d; - 20'd131: instruction <= 32'h00022021; - 20'd132: instruction <= 32'h00112821; - 20'd133: instruction <= 32'h0c0000b2; - 20'd134: instruction <= 32'h22310001; - 20'd135: instruction <= 32'h0800007d; - 20'd136: instruction <= 32'h8fbf0004; - 20'd137: instruction <= 32'h8fb00008; - 20'd138: instruction <= 32'h8fb1000c; - 20'd139: instruction <= 32'h23bd000c; - 20'd140: instruction <= 32'h03e00008; - 20'd141: instruction <= 32'h23bdffec; - 20'd142: instruction <= 32'hafb00004; - 20'd143: instruction <= 32'hafb10008; - 20'd144: instruction <= 32'hafb2000c; - 20'd145: instruction <= 32'hafb30010; - 20'd146: instruction <= 32'hafbf0014; - 20'd147: instruction <= 32'h00854022; - 20'd148: instruction <= 32'h19000002; - 20'd149: instruction <= 32'h00801020; - 20'd150: instruction <= 32'h080000ab; - 20'd151: instruction <= 32'h00048021; - 20'd152: instruction <= 32'h00058821; - 20'd153: instruction <= 32'h00069021; - 20'd154: instruction <= 32'h02119820; - 20'd155: instruction <= 32'h00139842; - 20'd156: instruction <= 32'h3c084000; - 20'd157: instruction <= 32'h21080064; - 20'd158: instruction <= 32'h00134880; - 20'd159: instruction <= 32'h01284820; - 20'd160: instruction <= 32'h8d290000; - 20'd161: instruction <= 32'h00125080; - 20'd162: instruction <= 32'h01485020; - 20'd163: instruction <= 32'h8d4a0000; - 20'd164: instruction <= 32'h012a4022; - 20'd165: instruction <= 32'h19000003; - 20'd166: instruction <= 32'h2265ffff; - 20'd167: instruction <= 32'h0c00008d; - 20'd168: instruction <= 32'h080000ab; - 20'd169: instruction <= 32'h22640001; - 20'd170: instruction <= 32'h0c00008d; - 20'd171: instruction <= 32'h8fb00004; - 20'd172: instruction <= 32'h8fb10008; - 20'd173: instruction <= 32'h8fb2000c; - 20'd174: instruction <= 32'h8fb30010; - 20'd175: instruction <= 32'h8fbf0014; - 20'd176: instruction <= 32'h23bd0014; - 20'd177: instruction <= 32'h03e00008; - 20'd178: instruction <= 32'h23bdfff4; - 20'd179: instruction <= 32'hafb00004; - 20'd180: instruction <= 32'hafb10008; - 20'd181: instruction <= 32'hafbf000c; - 20'd182: instruction <= 32'h3c104000; - 20'd183: instruction <= 32'h22100064; - 20'd184: instruction <= 32'h00054080; - 20'd185: instruction <= 32'h02089020; - 20'd186: instruction <= 32'h8e520000; - 20'd187: instruction <= 32'h20b1ffff; - 20'd188: instruction <= 32'h02244022; - 20'd189: instruction <= 32'h05000006; - 20'd190: instruction <= 32'h00114080; - 20'd191: instruction <= 32'h02084020; - 20'd192: instruction <= 32'h8d090000; - 20'd193: instruction <= 32'had090004; - 20'd194: instruction <= 32'h2231ffff; - 20'd195: instruction <= 32'h080000bc; - 20'd196: instruction <= 32'h00044080; - 20'd197: instruction <= 32'h02084020; - 20'd198: instruction <= 32'had120000; - 20'd199: instruction <= 32'h8fb00004; - 20'd200: instruction <= 32'h8fb10008; - 20'd201: instruction <= 32'h8fbf000c; - 20'd202: instruction <= 32'h23bd000c; - 20'd203: instruction <= 32'h03e00008; + 20'd36: instruction <= 32'h3c084000; + 20'd37: instruction <= 32'h8d040060; + 20'd38: instruction <= 32'h0c000076; + 20'd39: instruction <= 32'h0c000029; + 20'd40: instruction <= 32'h08000027; + 20'd41: instruction <= 32'h23bdffec; + 20'd42: instruction <= 32'hafbf0004; + 20'd43: instruction <= 32'hafb00008; + 20'd44: instruction <= 32'hafb1000c; + 20'd45: instruction <= 32'hafb20010; + 20'd46: instruction <= 32'hafb30014; + 20'd47: instruction <= 32'h3c104000; + 20'd48: instruction <= 32'h22110010; + 20'd49: instruction <= 32'h22100060; + 20'd50: instruction <= 32'h20120000; + 20'd51: instruction <= 32'h8e130000; + 20'd52: instruction <= 32'h22100004; + 20'd53: instruction <= 32'h00124080; + 20'd54: instruction <= 32'h02084020; + 20'd55: instruction <= 32'h8d040000; + 20'd56: instruction <= 32'h22250000; + 20'd57: instruction <= 32'h0c000045; + 20'd58: instruction <= 32'h22520001; + 20'd59: instruction <= 32'h02724022; + 20'd60: instruction <= 32'h1d00fff8; + 20'd61: instruction <= 32'h0c00006f; + 20'd62: instruction <= 32'h8fbf0004; + 20'd63: instruction <= 32'h8fb00008; + 20'd64: instruction <= 32'h8fb1000c; + 20'd65: instruction <= 32'h8fb20010; + 20'd66: instruction <= 32'h8fb30014; + 20'd67: instruction <= 32'h23bd0014; + 20'd68: instruction <= 32'h03e00008; + 20'd69: instruction <= 32'h23bdffe0; + 20'd70: instruction <= 32'hafbf0004; + 20'd71: instruction <= 32'hafb00008; + 20'd72: instruction <= 32'hafb1000c; + 20'd73: instruction <= 32'hafb20010; + 20'd74: instruction <= 32'hafb30014; + 20'd75: instruction <= 32'hafb40018; + 20'd76: instruction <= 32'hafb5001c; + 20'd77: instruction <= 32'hafb60020; + 20'd78: instruction <= 32'h20900000; + 20'd79: instruction <= 32'h20b10000; + 20'd80: instruction <= 32'h3c124000; + 20'd81: instruction <= 32'h22520020; + 20'd82: instruction <= 32'h20130be2; + 20'd83: instruction <= 32'h22140000; + 20'd84: instruction <= 32'h20160100; + 20'd85: instruction <= 32'h20150004; + 20'd86: instruction <= 32'h3288000f; + 20'd87: instruction <= 32'h00084080; + 20'd88: instruction <= 32'h02484020; + 20'd89: instruction <= 32'h8d080000; + 20'd90: instruction <= 32'h01164025; + 20'd91: instruction <= 32'hae280000; + 20'd92: instruction <= 32'h0014a102; + 20'd93: instruction <= 32'h0016b040; + 20'd94: instruction <= 32'h20080400; + 20'd95: instruction <= 32'h2108ffff; + 20'd96: instruction <= 32'h1d00fffe; + 20'd97: instruction <= 32'h22b5ffff; + 20'd98: instruction <= 32'h1ea0fff3; + 20'd99: instruction <= 32'h2273ffff; + 20'd100: instruction <= 32'h1e60ffee; + 20'd101: instruction <= 32'h8fbf0004; + 20'd102: instruction <= 32'h8fb00008; + 20'd103: instruction <= 32'h8fb1000c; + 20'd104: instruction <= 32'h8fb20010; + 20'd105: instruction <= 32'h8fb30014; + 20'd106: instruction <= 32'h8fb40018; + 20'd107: instruction <= 32'h8fb5001c; + 20'd108: instruction <= 32'h8fb60020; + 20'd109: instruction <= 32'h23bd0020; + 20'd110: instruction <= 32'h03e00008; + 20'd111: instruction <= 32'h3c084000; + 20'd112: instruction <= 32'h21080010; + 20'd113: instruction <= 32'had000000; + 20'd114: instruction <= 32'h3c080100; + 20'd115: instruction <= 32'h2108ffff; + 20'd116: instruction <= 32'h1d00fffe; + 20'd117: instruction <= 32'h03e00008; + 20'd118: instruction <= 32'h23bdfff4; + 20'd119: instruction <= 32'hafbf0004; + 20'd120: instruction <= 32'hafb00008; + 20'd121: instruction <= 32'hafb1000c; + 20'd122: instruction <= 32'h20900000; + 20'd123: instruction <= 32'h20110001; + 20'd124: instruction <= 32'h02114022; + 20'd125: instruction <= 32'h19000009; + 20'd126: instruction <= 32'h24040000; + 20'd127: instruction <= 32'h2225ffff; + 20'd128: instruction <= 32'h00113021; + 20'd129: instruction <= 32'h0c00008c; + 20'd130: instruction <= 32'h00022021; + 20'd131: instruction <= 32'h00112821; + 20'd132: instruction <= 32'h0c0000b1; + 20'd133: instruction <= 32'h22310001; + 20'd134: instruction <= 32'h0800007c; + 20'd135: instruction <= 32'h8fbf0004; + 20'd136: instruction <= 32'h8fb00008; + 20'd137: instruction <= 32'h8fb1000c; + 20'd138: instruction <= 32'h23bd000c; + 20'd139: instruction <= 32'h03e00008; + 20'd140: instruction <= 32'h23bdffec; + 20'd141: instruction <= 32'hafb00004; + 20'd142: instruction <= 32'hafb10008; + 20'd143: instruction <= 32'hafb2000c; + 20'd144: instruction <= 32'hafb30010; + 20'd145: instruction <= 32'hafbf0014; + 20'd146: instruction <= 32'h00854022; + 20'd147: instruction <= 32'h19000002; + 20'd148: instruction <= 32'h00801020; + 20'd149: instruction <= 32'h080000aa; + 20'd150: instruction <= 32'h00048021; + 20'd151: instruction <= 32'h00058821; + 20'd152: instruction <= 32'h00069021; + 20'd153: instruction <= 32'h02119820; + 20'd154: instruction <= 32'h00139842; + 20'd155: instruction <= 32'h3c084000; + 20'd156: instruction <= 32'h21080064; + 20'd157: instruction <= 32'h00134880; + 20'd158: instruction <= 32'h01284820; + 20'd159: instruction <= 32'h8d290000; + 20'd160: instruction <= 32'h00125080; + 20'd161: instruction <= 32'h01485020; + 20'd162: instruction <= 32'h8d4a0000; + 20'd163: instruction <= 32'h012a4022; + 20'd164: instruction <= 32'h19000003; + 20'd165: instruction <= 32'h2265ffff; + 20'd166: instruction <= 32'h0c00008c; + 20'd167: instruction <= 32'h080000aa; + 20'd168: instruction <= 32'h22640001; + 20'd169: instruction <= 32'h0c00008c; + 20'd170: instruction <= 32'h8fb00004; + 20'd171: instruction <= 32'h8fb10008; + 20'd172: instruction <= 32'h8fb2000c; + 20'd173: instruction <= 32'h8fb30010; + 20'd174: instruction <= 32'h8fbf0014; + 20'd175: instruction <= 32'h23bd0014; + 20'd176: instruction <= 32'h03e00008; + 20'd177: instruction <= 32'h23bdfff4; + 20'd178: instruction <= 32'hafb00004; + 20'd179: instruction <= 32'hafb10008; + 20'd180: instruction <= 32'hafbf000c; + 20'd181: instruction <= 32'h3c104000; + 20'd182: instruction <= 32'h22100064; + 20'd183: instruction <= 32'h00054080; + 20'd184: instruction <= 32'h02089020; + 20'd185: instruction <= 32'h8e520000; + 20'd186: instruction <= 32'h20b1ffff; + 20'd187: instruction <= 32'h02244022; + 20'd188: instruction <= 32'h05000006; + 20'd189: instruction <= 32'h00114080; + 20'd190: instruction <= 32'h02084020; + 20'd191: instruction <= 32'h8d090000; + 20'd192: instruction <= 32'had090004; + 20'd193: instruction <= 32'h2231ffff; + 20'd194: instruction <= 32'h080000bb; + 20'd195: instruction <= 32'h00044080; + 20'd196: instruction <= 32'h02084020; + 20'd197: instruction <= 32'had120000; + 20'd198: instruction <= 32'h8fb00004; + 20'd199: instruction <= 32'h8fb10008; + 20'd200: instruction <= 32'h8fbf000c; + 20'd201: instruction <= 32'h23bd000c; + 20'd202: instruction <= 32'h03e00008; default: instruction <= 32'h00000000; endcase end diff --git a/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp b/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp index afc36df..d6bde76 100644 Binary files a/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp and b/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp differ diff --git a/PipelineProcessor.xpr b/PipelineProcessor.xpr index 2dff9e6..0eaa488 100644 --- a/PipelineProcessor.xpr +++ b/PipelineProcessor.xpr @@ -60,7 +60,7 @@