Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023 | Date : Mon Jul 15 21:31:56 2024 | Host : Viviana running 64-bit major release (build 9200) | Command : report_clock_utilization -file CPU_clock_utilization_routed.rpt | Design : CPU | Device : 7a35t-fgg484 | Speed File : -1 PRODUCTION 1.23 2018-06-13 | Design State : Routed --------------------------------------------------------------------------------------------------------------------------------------------- Clock Utilization Report Table of Contents ----------------- 1. Clock Primitive Utilization 2. Global Clock Resources 3. Global Clock Source Details 4. Clock Regions: Key Resource Utilization 5. Clock Regions : Global Clock Summary 6. Device Cell Placement Summary for Global Clock g0 7. Device Cell Placement Summary for Global Clock g1 8. Clock Region Cell Placement per Global Clock: Region X0Y0 9. Clock Region Cell Placement per Global Clock: Region X1Y0 10. Clock Region Cell Placement per Global Clock: Region X0Y1 11. Clock Region Cell Placement per Global Clock: Region X1Y1 12. Clock Region Cell Placement per Global Clock: Region X0Y2 13. Clock Region Cell Placement per Global Clock: Region X1Y2 1. Clock Primitive Utilization ------------------------------ +----------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +----------+------+-----------+-----+--------------+--------+ | BUFGCTRL | 2 | 32 | 0 | 0 | 0 | | BUFH | 0 | 72 | 0 | 0 | 0 | | BUFIO | 0 | 20 | 0 | 0 | 0 | | BUFMR | 0 | 10 | 0 | 0 | 0 | | BUFR | 0 | 20 | 0 | 0 | 0 | | MMCM | 0 | 5 | 0 | 0 | 0 | | PLL | 1 | 5 | 0 | 0 | 0 | +----------+------+-----------+-----+--------------+--------+ 2. Global Clock Resources ------------------------- +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+ | g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 6 | 18132 | 0 | 20.000 | clk_out1_phase_locked_loop | pll/inst/clkout1_buf/O | pll/inst/clk_out1 | | g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 1 | 0 | 20.000 | clkfbout_phase_locked_loop | pll/inst/clkf_buf/O | pll/inst/clkfbout_buf_phase_locked_loop | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads 3. Global Clock Source Details ------------------------------ +-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+----------------------------+----------------------------------+-------------------------------------+ | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | +-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+----------------------------+----------------------------------+-------------------------------------+ | src0 | g0 | PLLE2_ADV/CLKOUT0 | None | PLLE2_ADV_X1Y0 | X1Y0 | 1 | 0 | 20.000 | clk_out1_phase_locked_loop | pll/inst/plle2_adv_inst/CLKOUT0 | pll/inst/clk_out1_phase_locked_loop | | src1 | g1 | PLLE2_ADV/CLKFBOUT | None | PLLE2_ADV_X1Y0 | X1Y0 | 1 | 0 | 20.000 | clkfbout_phase_locked_loop | pll/inst/plle2_adv_inst/CLKFBOUT | pll/inst/clkfbout_phase_locked_loop | +-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+----------------------------+----------------------------------+-------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads 4. Clock Regions: Key Resource Utilization ------------------------------------------ +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3068 | 1200 | 988 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4193 | 1500 | 1239 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | | X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2689 | 1200 | 887 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3944 | 1500 | 1126 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | | X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3420 | 1800 | 711 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 818 | 950 | 246 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts 5. Clock Regions : Global Clock Summary --------------------------------------- All Modules +----+----+----+ | | X0 | X1 | +----+----+----+ | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+----+ 6. Device Cell Placement Summary for Global Clock g0 ---------------------------------------------------- +-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+ | g0 | BUFG/O | n/a | clk_out1_phase_locked_loop | 20.000 | {0.000 10.000} | 18132 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-------+-------+-----------------------+ | | X0 | X1 | HORIZONTAL PROG DELAY | +----+-------+-------+-----------------------+ | Y2 | 3420 | 818 | 0 | | Y1 | 2689 | 3944 | 0 | | Y0 | 3068 | 4193 | 0 | +----+-------+-------+-----------------------+ 7. Device Cell Placement Summary for Global Clock g1 ---------------------------------------------------- +-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-----------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-----------------------------------------+ | g1 | BUFG/O | n/a | clkfbout_phase_locked_loop | 20.000 | {0.000 10.000} | 0 | 0 | 1 | 0 | pll/inst/clkfbout_buf_phase_locked_loop | +-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-----------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+-----------------------+ | | X0 | X1 | HORIZONTAL PROG DELAY | +----+----+----+-----------------------+ | Y2 | 0 | 0 | - | | Y1 | 0 | 0 | - | | Y0 | 0 | 1 | 0 | +----+----+----+-----------------------+ 8. Clock Region Cell Placement per Global Clock: Region X0Y0 ------------------------------------------------------------ +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | g0 | n/a | BUFG/O | None | 3068 | 0 | 3068 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 9. Clock Region Cell Placement per Global Clock: Region X1Y0 ------------------------------------------------------------ +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+ | g0 | n/a | BUFG/O | None | 4193 | 0 | 4193 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | | g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | pll/inst/clkfbout_buf_phase_locked_loop | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 10. Clock Region Cell Placement per Global Clock: Region X0Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | g0 | n/a | BUFG/O | None | 2689 | 0 | 2689 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 11. Clock Region Cell Placement per Global Clock: Region X1Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | g0 | n/a | BUFG/O | None | 3944 | 0 | 3944 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 12. Clock Region Cell Placement per Global Clock: Region X0Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ | g0 | n/a | BUFG/O | None | 3420 | 0 | 3420 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 13. Clock Region Cell Placement per Global Clock: Region X1Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-------------------+ | g0 | n/a | BUFG/O | None | 818 | 0 | 818 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 | +-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts # Location of BUFG Primitives set_property LOC BUFGCTRL_X0Y1 [get_cells pll/inst/clkf_buf] set_property LOC BUFGCTRL_X0Y0 [get_cells pll/inst/clkout1_buf] # Location of IO Primitives which is load of clock spine # Location of clock ports set_property LOC IOB_X1Y24 [get_ports hardware_clk] # Clock net "pll/inst/clk_out1" driven by instance "pll/inst/clkout1_buf" located at site "BUFGCTRL_X0Y0" #startgroup create_pblock {CLKAG_pll/inst/clk_out1} add_cells_to_pblock [get_pblocks {CLKAG_pll/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pll/inst/clk_out1"}]]] resize_pblock [get_pblocks {CLKAG_pll/inst/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2} #endgroup