`timescale 1ns / 1ps

module ALU (
    input  [ 4:0] funct,
    input  [31:0] in_1,
    input  [31:0] in_2,
    output [31:0] result
);

    wire lt_signed;

    assign lt_signed = (in_1[31] ^ in_2[31]) ? ((in_1[31] == 1'b0 && in_2[31] == 1'b1) ? 0 : 1):
                   (in_1[30:0] < in_2[30:0]);

    always @(*) begin
        case (funct)
            5'b00000: result = in_1 & in_2;  // 0, and
            5'b00001: result = in_1 | in_2;  // 1, or
            5'b00010: result = in_1 + in_2;  // 2, add
            5'b00110: result = in_1 - in_2;  // 6, sub
            5'b00111: result = {31'b0, lt_signed};  // 7, slt signed
            5'b01000: result = {31'b0, in_1 < in_2};  // 8, slt unsigned
            5'b01100: result = ~(in_1 | in_2);  // 12, nor
            5'b01101: result = in_1 ^ in_2;  // 13, xor
            5'b10000: result = in_2 << in_1[4:0];  // 16, sll
            5'b10001: result = {31'b0, in_1 == in_2};  // 17, eq
            5'b10010: result = {31'b0, ~(in_1 == in_2)};  // 18, neq
            5'b10011: result = {31'b0, (in_1[31] == 1'b0 && in_1 != 32'h00000000)};  // 19, gtz
            5'b10100: result = {31'b0, in_1[31] == 1'b1};  // 20, ltz
            5'b10101: result = {31'b0, (in_1[31] == 1'b1 || in_1 == 32'h00000000)};  // 21, lez
            5'b11000: result = {in2 >> in1[4:0]};  // 24, srl
            5'b11001: result = {{32{in2[31]}}, in2} >> in1[4:0];  // 25, sra
            5'b11010: result = in1 * in2;  // 26, mul
            default:  result = 31'h00000000;
        endcase
    end
endmodule