`timescale 1ns / 1ps

module DataMemory (
    input clk,
    input [31:0] address,
    input write_enable,
    input [31:0] write_data,
    output reg [31:0] read_data,
    output [31:0] bcd_hardwire
);
    parameter integer MEM_SIZE = 1024;
    parameter integer START_ADDRESS = 32'h00000000;

    reg [31:0] memory_data[MEM_SIZE + START_ADDRESS - 1:START_ADDRESS];

    assign bcd_hardwire = memory_data[START_ADDRESS + 4];

    always @(posedge clk) begin
        if (write_enable) begin
            memory_data[address] <= write_data;
        end
        read_data <= memory_data[address];
    end
endmodule