`timescale 1ns / 1ps

module InstructionMemory (
    input  [31:0] address,
    output reg [31:0] instruction
);

always @(*) begin
    case (address[31:2])
        20'd0: instruction <= 32'h20210001;
        20'd1: instruction <= 32'h08000000;
        default: instruction <= 32'h00000000;
    endcase
end

endmodule