`timescale 1ns / 1ps
module MemoryAccess (
    input clk,
    // From prev stage
    input prev_register_write,
    input prev_WB_source,
    input prev_memory_write,
    input [31:0] prev_ALU_result,
    input [31:0] prev_memory_write_data,
    input [4:0] prev_register_write_destination,
    input [4:0] prev_rt_address,
    // From forward unit
    input MEM_write_data_source,
    // From WB
    input [31:0] WB_forwarded_data,
    // To Forward unit
    output [4:0] rt_address,
    // To next stage
    output register_write,
    output WB_source,
    output [31:0] memory_read_data,
    output [31:0] ALU_result,
    output [4:0] register_write_destination,

    // Data memory IO
    output data_memory_write,
    output [31:0] data_memory_address,
    output [31:0] data_memory_write_data,
    input [31:0] data_memory_read_data
);

    reg MEM_register_write;
    reg MEM_WB_source;
    reg MEM_memory_write;
    reg [31:0] MEM_ALU_result;
    reg [31:0] MEM_memory_write_data;
    reg [4:0] MEM_register_write_destination;
    reg [4:0] MEM_rt_address;

    // wire memory_write_data_include_forward;
    // assign memory_write_data_include_forward = (MEM_write_data_source == 1'b0) ?
    //                                             MEM_memory_write_data : WB_forwarded_data;

    // DataMemory data_memory(
    //     .clk(clk),
    //     .address(MEM_ALU_result),
    //     .write_enable(MEM_memory_write),
    //     .write_data(memory_write_data_include_forward),
    //     .read_data(memory_read_data)
    // );
    assign data_memory = MEM_memory_write;
    assign data_memory_address = MEM_ALU_result;
    assign data_memory_write_data = (MEM_write_data_source == 1'b0) ?
                                                MEM_memory_write_data : WB_forwarded_data;
    assign read_data = data_memory_read_data;

    assign rt_address = MEM_rt_address;
    assign register_write = MEM_register_write;
    assign WB_source = MEM_WB_source;
    assign ALU_result = MEM_ALU_result;
    assign register_write_destination = MEM_register_write_destination;

    always @(posedge clk) begin
        MEM_register_write <= prev_register_write;
        MEM_WB_source <= prev_WB_source;
        MEM_memory_write <= prev_memory_write;
        MEM_ALU_result <= prev_ALU_result;
        MEM_memory_write_data <= prev_memory_write_data;
        MEM_register_write_destination <= prev_register_write_destination;
        MEM_rt_address <= prev_rt_address;
    end
endmodule