`timescale 1ns / 1ps
module WriteBack (
    input clk,
    // From prev stage
    input prev_register_write,
    input prev_WB_source,
    input [31:0] prev_memory_read_data,
    input [31:0] prev_ALU_result,
    input [4:0] prev_register_write_destination,
    // To many things, really
    output register_write,
    output [31:0] register_write_data,
    output [4:0] register_write_addr
);

    reg WB_register_write;
    reg WB_WB_source;
    reg [31:0] WB_memory_read_data;
    reg [31:0] WB_ALU_result;
    reg [4:0] WB_register_write_destination;

    assign register_write = WB_register_write;
    assign register_write_data = (WB_WB_source == 1'b0) ? WB_ALU_result : WB_memory_read_data;
    assign register_write_addr = WB_register_write_destination;

    always @(posedge clk) begin
        WB_register_write <= prev_register_write;
        WB_WB_source <= prev_WB_source;
        WB_memory_read_data <= prev_memory_read_data;
        WB_ALU_result <= prev_ALU_result;
        WB_register_write_destination <= prev_register_write_destination;
    end
endmodule