158 lines
8.9 KiB
Plaintext
158 lines
8.9 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
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| Date : Mon Jul 15 21:31:54 2024
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| Host : Viviana running 64-bit major release (build 9200)
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| Command : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
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| Design : CPU
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| Device : xc7a35tfgg484-1
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| Design State : routed
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| Grade : commercial
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| Process : typical
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| Characterization : Production
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Power Report
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Table of Contents
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-----------------
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1. Summary
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1.1 On-Chip Components
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1.2 Power Supply Summary
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1.3 Confidence Level
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2. Settings
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2.1 Environment
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2.2 Clock Constraints
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3. Detailed Reports
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3.1 By Hierarchy
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1. Summary
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----------
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+--------------------------+--------------+
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| Total On-Chip Power (W) | 0.188 |
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| Design Power Budget (W) | Unspecified* |
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| Power Budget Margin (W) | NA |
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| Dynamic (W) | 0.119 |
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| Device Static (W) | 0.069 |
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| Effective TJA (C/W) | 2.8 |
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| Max Ambient (C) | 84.5 |
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| Junction Temperature (C) | 25.5 |
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| Confidence Level | Medium |
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| Setting File | --- |
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| Simulation Activity File | --- |
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| Design Nets Matched | NA |
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+--------------------------+--------------+
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* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
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1.1 On-Chip Components
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----------------------
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+----------------+-----------+----------+-----------+-----------------+
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| On-Chip | Power (W) | Used | Available | Utilization (%) |
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+----------------+-----------+----------+-----------+-----------------+
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| Clocks | 0.015 | 5 | --- | --- |
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| Slice Logic | 0.003 | 30293 | --- | --- |
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| LUT as Logic | 0.003 | 8344 | 20800 | 40.12 |
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| CARRY4 | <0.001 | 39 | 8150 | 0.48 |
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| Register | <0.001 | 18132 | 41600 | 43.59 |
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| F7/F8 Muxes | <0.001 | 3465 | 32600 | 10.63 |
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| Others | 0.000 | 12 | --- | --- |
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| Signals | 0.002 | 22010 | --- | --- |
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| PLL | 0.099 | 1 | 5 | 20.00 |
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| DSPs | <0.001 | 3 | 90 | 3.33 |
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| I/O | <0.001 | 15 | 250 | 6.00 |
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| Static Power | 0.069 | | | |
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| Total | 0.188 | | | |
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+----------------+-----------+----------+-----------+-----------------+
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1.2 Power Supply Summary
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------------------------
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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| Vccint | 1.000 | 0.039 | 0.029 | 0.010 | NA | Unspecified | NA |
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| Vccaux | 1.800 | 0.063 | 0.050 | 0.013 | NA | Unspecified | NA |
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| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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1.3 Confidence Level
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--------------------
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+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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| User Input Data | Confidence | Details | Action |
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+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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| Design implementation state | High | Design is routed | |
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| Clock nodes activity | High | User specified more than 95% of clocks | |
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| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
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| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
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| Device models | High | Device models are Production | |
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| Overall confidence level | Medium | | |
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+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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2. Settings
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-----------
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2.1 Environment
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---------------
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+-----------------------+--------------------------+
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| Ambient Temp (C) | 25.0 |
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| ThetaJA (C/W) | 2.8 |
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| Airflow (LFM) | 250 |
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| Heat Sink | medium (Medium Profile) |
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| ThetaSA (C/W) | 4.6 |
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| Board Selection | medium (10"x10") |
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| # of Board Layers | 12to15 (12 to 15 Layers) |
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| Board Temperature (C) | 25.0 |
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+-----------------------+--------------------------+
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2.2 Clock Constraints
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---------------------
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+----------------------------+-------------------------------------+-----------------+
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| Clock | Domain | Constraint (ns) |
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+----------------------------+-------------------------------------+-----------------+
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| clk_out1_phase_locked_loop | pll/inst/clk_out1_phase_locked_loop | 20.0 |
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| clkfbout_phase_locked_loop | pll/inst/clkfbout_phase_locked_loop | 20.0 |
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| hardware_clk | hardware_clk | 10.0 |
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+----------------------------+-------------------------------------+-----------------+
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3. Detailed Reports
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-------------------
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3.1 By Hierarchy
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----------------
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+----------------------+-----------+
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| Name | Power (W) |
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+----------------------+-----------+
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| CPU | 0.119 |
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| data_memory | 0.013 |
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| instruction_decode | 0.002 |
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| instruction_fetch | 0.001 |
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| pll | 0.100 |
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| inst | 0.100 |
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| write_back | 0.002 |
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+----------------------+-----------+
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