51 lines
2.0 KiB
Plaintext
51 lines
2.0 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
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| Date : Fri Jul 12 21:06:53 2024
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| Host : Viviana running 64-bit major release (build 9200)
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| Command : report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx
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| Design : CPU
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| Device : xc7a35tfgg484-1
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| Speed File : -1
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| Design State : Fully Routed
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Report Methodology
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: design_1
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Design limits: <entire design considered>
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Max violations: <unlimited>
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Violations found: 3
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+----------+----------+-----------------+------------+
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| Rule | Severity | Description | Violations |
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+----------+----------+-----------------+------------+
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| SYNTH-10 | Warning | Wide multiplier | 3 |
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+----------+----------+-----------------+------------+
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2. REPORT DETAILS
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-----------------
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SYNTH-10#1 Warning
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Wide multiplier
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Detected multiplier at execution/alu/result0 of size 16x18, it is decomposed from a wide multipler into 4 DSP blocks.
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Related violations: <none>
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SYNTH-10#2 Warning
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Wide multiplier
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Detected multiplier at execution/alu/result0__0 of size 18x18, it is decomposed from a wide multipler into 4 DSP blocks.
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Related violations: <none>
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SYNTH-10#3 Warning
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Wide multiplier
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Detected multiplier at execution/alu/result0__1 of size 18x16, it is decomposed from a wide multipler into 4 DSP blocks.
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Related violations: <none>
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