21 lines
383 B
Verilog
21 lines
383 B
Verilog
`timescale 1ns / 1ps
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module test_cpu ();
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reg sim_clk = 0;
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reg reset = 0;
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wire [11:0] bcd_control;
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wire clk_locked;
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initial begin
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forever begin
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#5 sim_clk <= ~sim_clk;
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end
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end
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CPU cpu(
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.hardware_clk(sim_clk),
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.reset(reset),
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.clock_locked(clk_locked),
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.bcd_control(bcd_control)
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);
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endmodule
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