38 lines
1.5 KiB
Verilog
38 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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module ALU (
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input [ 4:0] funct,
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input [31:0] in_1,
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input [31:0] in_2,
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output reg [31:0] result
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);
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wire lt_signed;
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assign lt_signed = (in_1[31] ^ in_2[31]) ? ((in_1[31] == 1'b0 && in_2[31] == 1'b1) ? 0 : 1):
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(in_1[30:0] < in_2[30:0]);
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always @(*) begin
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case (funct)
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5'b00000: result <= in_1 & in_2; // 0, and
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5'b00001: result <= in_1 | in_2; // 1, or
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5'b00010: result <= in_1 + in_2; // 2, add
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5'b00110: result <= in_1 - in_2; // 6, sub
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5'b00111: result <= {31'b0, lt_signed}; // 7, slt signed
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5'b01000: result <= {31'b0, in_1 < in_2}; // 8, slt unsigned
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5'b01100: result <= ~(in_1 | in_2); // 12, nor
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5'b01101: result <= in_1 ^ in_2; // 13, xor
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5'b10000: result <= in_2 << in_1[4:0]; // 16, sll
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5'b10001: result <= {31'b0, in_1 == in_2}; // 17, eq
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5'b10010: result <= {31'b0, ~(in_1 == in_2)}; // 18, neq
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5'b10011: result <= {31'b0, (in_1[31] == 1'b0 && in_1 != 32'h00000000)}; // 19, gtz
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5'b10100: result <= {31'b0, in_1[31] == 1'b1}; // 20, ltz
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5'b10101: result <= {31'b0, (in_1[31] == 1'b1 || in_1 == 32'h00000000)}; // 21, lez
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5'b11000: result <= {in_2 >> in_1[4:0]}; // 24, srl
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5'b11001: result <= {{32{in_2[31]}}, in_2} >> in_1[4:0]; // 25, sra
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5'b11010: result <= in_1 * in_2; // 26, mul
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default: result <= 31'h00000000;
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endcase
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end
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endmodule
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