35 lines
1.4 KiB
Verilog
35 lines
1.4 KiB
Verilog
`timescale 1ns / 1ps
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module InstructionMemory (
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input [31:0] address,
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output reg [31:0] instruction
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);
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always @(*) begin
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case (address[31:2])
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20'd0: instruction <= 32'h20110002; // addi $s1, $zero, 2
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20'd1: instruction <= 32'h00000000;
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20'd2: instruction <= 32'h00000000;
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20'd3: instruction <= 32'h00000000;
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20'd4: instruction <= 32'h00000000;
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20'd5: instruction <= 32'h20120050; // addi $s2, $zero, 0x50
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20'd6: instruction <= 32'h00000000;
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20'd7: instruction <= 32'h00000000;
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20'd8: instruction <= 32'h00000000;
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20'd9: instruction <= 32'h00000000;
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20'd10: instruction <= 32'h02408009; // jalr $s2, $s0
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// end:
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20'd11: instruction <= 32'h0800000b; // j end
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// Note the address
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20'd20: instruction <= 32'h20130003; // addi $s3, $zero, 3
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20'd21: instruction <= 32'h00000000;
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20'd22: instruction <= 32'h00000000;
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20'd23: instruction <= 32'h00000000;
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20'd24: instruction <= 32'h00000000;
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20'd25: instruction <= 32'h02000008; // jr $s0
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default: instruction <= 32'h00000000;
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endcase
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end
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endmodule
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