245 lines
21 KiB
Plaintext
245 lines
21 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
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| Date : Sat Jul 13 14:29:52 2024
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| Host : Viviana running 64-bit major release (build 9200)
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| Command : report_clock_utilization -file CPU_clock_utilization_routed.rpt
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| Design : CPU
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| Device : 7a35t-fgg484
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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| Design State : Routed
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Clock Utilization Report
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Table of Contents
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-----------------
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1. Clock Primitive Utilization
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2. Global Clock Resources
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3. Global Clock Source Details
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4. Clock Regions: Key Resource Utilization
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5. Clock Regions : Global Clock Summary
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6. Device Cell Placement Summary for Global Clock g0
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7. Device Cell Placement Summary for Global Clock g1
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8. Clock Region Cell Placement per Global Clock: Region X0Y0
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9. Clock Region Cell Placement per Global Clock: Region X1Y0
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10. Clock Region Cell Placement per Global Clock: Region X0Y1
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11. Clock Region Cell Placement per Global Clock: Region X1Y1
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12. Clock Region Cell Placement per Global Clock: Region X0Y2
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13. Clock Region Cell Placement per Global Clock: Region X1Y2
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1. Clock Primitive Utilization
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------------------------------
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+----------+------+-----------+-----+--------------+--------+
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| Type | Used | Available | LOC | Clock Region | Pblock |
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+----------+------+-----------+-----+--------------+--------+
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| BUFGCTRL | 2 | 32 | 0 | 0 | 0 |
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| BUFH | 0 | 72 | 0 | 0 | 0 |
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| BUFIO | 0 | 20 | 0 | 0 | 0 |
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| BUFMR | 0 | 10 | 0 | 0 | 0 |
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| BUFR | 0 | 20 | 0 | 0 | 0 |
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| MMCM | 0 | 5 | 0 | 0 | 0 |
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| PLL | 1 | 5 | 0 | 0 | 0 |
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+----------+------+-----------+-----+--------------+--------+
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2. Global Clock Resources
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-------------------------
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+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+
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| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
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+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+
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| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 6 | 18132 | 0 | 20.000 | clk_out1_phase_locked_loop | pll/inst/clkout1_buf/O | pll/inst/clk_out1 |
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| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 1 | 0 | 20.000 | clkfbout_phase_locked_loop | pll/inst/clkf_buf/O | pll/inst/clkfbout_buf_phase_locked_loop |
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+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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3. Global Clock Source Details
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------------------------------
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+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+----------------------------+----------------------------------+-------------------------------------+
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| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
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+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+----------------------------+----------------------------------+-------------------------------------+
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| src0 | g0 | PLLE2_ADV/CLKOUT0 | None | PLLE2_ADV_X1Y0 | X1Y0 | 1 | 0 | 20.000 | clk_out1_phase_locked_loop | pll/inst/plle2_adv_inst/CLKOUT0 | pll/inst/clk_out1_phase_locked_loop |
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| src1 | g1 | PLLE2_ADV/CLKFBOUT | None | PLLE2_ADV_X1Y0 | X1Y0 | 1 | 0 | 20.000 | clkfbout_phase_locked_loop | pll/inst/plle2_adv_inst/CLKFBOUT | pll/inst/clkfbout_phase_locked_loop |
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+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+----------------------------+----------------------------------+-------------------------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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4. Clock Regions: Key Resource Utilization
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------------------------------------------
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+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
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| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1517 | 1200 | 460 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
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| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3911 | 1500 | 1072 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
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| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2799 | 1200 | 937 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
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| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3610 | 1500 | 1055 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
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| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4277 | 1800 | 774 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
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| X1Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 2018 | 950 | 601 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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* Global Clock column represents track count; while other columns represents cell counts
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5. Clock Regions : Global Clock Summary
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---------------------------------------
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All Modules
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+----+----+----+
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| | X0 | X1 |
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+----+----+----+
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| Y2 | 0 | 0 |
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| Y1 | 0 | 0 |
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| Y0 | 0 | 0 |
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+----+----+----+
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6. Device Cell Placement Summary for Global Clock g0
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----------------------------------------------------
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+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+
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| g0 | BUFG/O | n/a | clk_out1_phase_locked_loop | 20.000 | {0.000 10.000} | 18132 | 0 | 0 | 0 | pll/inst/clk_out1 |
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+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+-------+-------+-----------------------+
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| | X0 | X1 | HORIZONTAL PROG DELAY |
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+----+-------+-------+-----------------------+
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| Y2 | 4277 | 2018 | 0 |
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| Y1 | 2799 | 3610 | 0 |
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| Y0 | 1517 | 3911 | 0 |
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+----+-------+-------+-----------------------+
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7. Device Cell Placement Summary for Global Clock g1
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----------------------------------------------------
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+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-----------------------------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-----------------------------------------+
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| g1 | BUFG/O | n/a | clkfbout_phase_locked_loop | 20.000 | {0.000 10.000} | 0 | 0 | 1 | 0 | pll/inst/clkfbout_buf_phase_locked_loop |
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+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-----------------------------------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+----+----+-----------------------+
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| | X0 | X1 | HORIZONTAL PROG DELAY |
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+----+----+----+-----------------------+
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| Y2 | 0 | 0 | - |
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| Y1 | 0 | 0 | - |
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| Y0 | 0 | 1 | 0 |
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+----+----+----+-----------------------+
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8. Clock Region Cell Placement per Global Clock: Region X0Y0
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------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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| g0 | n/a | BUFG/O | None | 1517 | 0 | 1517 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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9. Clock Region Cell Placement per Global Clock: Region X1Y0
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------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+
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| g0 | n/a | BUFG/O | None | 3911 | 0 | 3911 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
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| g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | pll/inst/clkfbout_buf_phase_locked_loop |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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10. Clock Region Cell Placement per Global Clock: Region X0Y1
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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| g0 | n/a | BUFG/O | None | 2799 | 0 | 2799 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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11. Clock Region Cell Placement per Global Clock: Region X1Y1
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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| g0 | n/a | BUFG/O | None | 3610 | 0 | 3610 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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12. Clock Region Cell Placement per Global Clock: Region X0Y2
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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| g0 | n/a | BUFG/O | None | 4277 | 0 | 4277 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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13. Clock Region Cell Placement per Global Clock: Region X1Y2
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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| g0 | n/a | BUFG/O | None | 2018 | 0 | 2018 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
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* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
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** Non-Clock Loads column represents cell count of non-clock pin loads
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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# Location of BUFG Primitives
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set_property LOC BUFGCTRL_X0Y1 [get_cells pll/inst/clkf_buf]
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set_property LOC BUFGCTRL_X0Y0 [get_cells pll/inst/clkout1_buf]
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# Location of IO Primitives which is load of clock spine
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# Location of clock ports
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set_property LOC IOB_X1Y24 [get_ports hardware_clk]
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# Clock net "pll/inst/clk_out1" driven by instance "pll/inst/clkout1_buf" located at site "BUFGCTRL_X0Y0"
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#startgroup
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create_pblock {CLKAG_pll/inst/clk_out1}
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add_cells_to_pblock [get_pblocks {CLKAG_pll/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pll/inst/clk_out1"}]]]
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resize_pblock [get_pblocks {CLKAG_pll/inst/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
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#endgroup
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