3375 lines
254 KiB
Plaintext
3375 lines
254 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
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| Date : Sat Jul 13 14:29:52 2024
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| Host : Viviana running 64-bit major release (build 9200)
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| Command : report_timing_summary -max_paths 10 -report_unconstrained -file CPU_timing_summary_routed.rpt -pb CPU_timing_summary_routed.pb -rpx CPU_timing_summary_routed.rpx -warn_on_violation
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| Design : CPU
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| Device : 7a35t-fgg484
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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| Design State : Routed
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------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Timing Summary Report
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------------------------------------------------------------------------------------------------
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| Timer Settings
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| --------------
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------------------------------------------------------------------------------------------------
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Enable Multi Corner Analysis : Yes
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Enable Pessimism Removal : Yes
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Pessimism Removal Resolution : Nearest Common Node
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Enable Input Delay Default Clock : No
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Enable Preset / Clear Arcs : No
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Disable Flight Delays : No
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Ignore I/O Paths : No
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Timing Early Launch at Borrowing Latches : No
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Borrow Time for Max Delay Exceptions : Yes
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Merge Timing Exceptions : Yes
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Inter-SLR Compensation : Conservative
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Corner Analyze Analyze
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Name Max Paths Min Paths
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------ --------- ---------
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Slow Yes Yes
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Fast Yes Yes
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------------------------------------------------------------------------------------------------
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| Report Methodology
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| ------------------
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------------------------------------------------------------------------------------------------
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Rule Severity Description Violations
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-------- -------- --------------- ----------
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SYNTH-10 Warning Wide multiplier 3
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Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
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check_timing report
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Table of Contents
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-----------------
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1. checking no_clock (0)
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2. checking constant_clock (0)
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3. checking pulse_width_clock (0)
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4. checking unconstrained_internal_endpoints (0)
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5. checking no_input_delay (1)
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6. checking no_output_delay (12)
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7. checking multiple_clock (0)
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8. checking generated_clocks (0)
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9. checking loops (0)
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10. checking partial_input_delay (0)
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11. checking partial_output_delay (0)
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12. checking latch_loops (0)
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1. checking no_clock (0)
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------------------------
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There are 0 register/latch pins with no clock.
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2. checking constant_clock (0)
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------------------------------
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There are 0 register/latch pins with constant_clock.
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3. checking pulse_width_clock (0)
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---------------------------------
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There are 0 register/latch pins which need pulse_width check
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4. checking unconstrained_internal_endpoints (0)
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------------------------------------------------
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There are 0 pins that are not constrained for maximum delay.
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There are 0 pins that are not constrained for maximum delay due to constant clock.
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5. checking no_input_delay (1)
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------------------------------
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There is 1 input port with no input delay specified. (HIGH)
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There are 0 input ports with no input delay but user has a false path constraint.
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6. checking no_output_delay (12)
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--------------------------------
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There are 12 ports with no output delay specified. (HIGH)
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There are 0 ports with no output delay but user has a false path constraint
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There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
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7. checking multiple_clock (0)
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------------------------------
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There are 0 register/latch pins with multiple clocks.
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8. checking generated_clocks (0)
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--------------------------------
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There are 0 generated clocks that are not connected to a clock source.
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9. checking loops (0)
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---------------------
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There are 0 combinational loops in the design.
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10. checking partial_input_delay (0)
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------------------------------------
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There are 0 input ports with partial input delay specified.
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11. checking partial_output_delay (0)
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-------------------------------------
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There are 0 ports with partial output delay specified.
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12. checking latch_loops (0)
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----------------------------
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There are 0 combinational latch loops in the design through latch input
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------------------------------------------------------------------------------------------------
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| Design Timing Summary
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| ---------------------
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------------------------------------------------------------------------------------------------
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WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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2.679 0.000 0 35779 0.070 0.000 0 35779 3.000 0.000 0 18138
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All user specified timing constraints are met.
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------------------------------------------------------------------------------------------------
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| Clock Summary
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| -------------
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------------------------------------------------------------------------------------------------
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Clock Waveform(ns) Period(ns) Frequency(MHz)
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----- ------------ ---------- --------------
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hardware_clk {0.000 5.000} 10.000 100.000
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clk_out1_phase_locked_loop {0.000 10.000} 20.000 50.000
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clkfbout_phase_locked_loop {0.000 10.000} 20.000 50.000
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------------------------------------------------------------------------------------------------
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| Intra Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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hardware_clk 3.000 0.000 0 1
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clk_out1_phase_locked_loop 2.679 0.000 0 35779 0.070 0.000 0 35779 9.500 0.000 0 18134
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clkfbout_phase_locked_loop 17.845 0.000 0 3
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------------------------------------------------------------------------------------------------
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| Inter Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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------------------------------------------------------------------------------------------------
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| Other Path Groups Table
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| -----------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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------------------------------------------------------------------------------------------------
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| User Ignored Path Table
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| -----------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock
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---------- ---------- --------
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------------------------------------------------------------------------------------------------
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| Unconstrained Path Table
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| ------------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock
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---------- ---------- --------
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(none) clk_out1_phase_locked_loop
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(none) clkfbout_phase_locked_loop
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(none) clk_out1_phase_locked_loop
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------------------------------------------------------------------------------------------------
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| Timing Details
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| --------------
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------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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From Clock: hardware_clk
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To Clock: hardware_clk
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Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Pulse Width Checks
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--------------------------------------------------------------------------------------
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Clock Name: hardware_clk
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Waveform(ns): { 0.000 5.000 }
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Period(ns): 10.000
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Sources: { hardware_clk }
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Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
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Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 10.000 8.751 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKIN1
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Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 10.000 42.633 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKIN1
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Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKIN1
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Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKIN1
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High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKIN1
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High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKIN1
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---------------------------------------------------------------------------------------------------
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From Clock: clk_out1_phase_locked_loop
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To Clock: clk_out1_phase_locked_loop
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Setup : 0 Failing Endpoints, Worst Slack 2.679ns, Total Violation 0.000ns
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Hold : 0 Failing Endpoints, Worst Slack 0.070ns, Total Violation 0.000ns
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PW : 0 Failing Endpoints, Worst Slack 9.500ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Max Delay Paths
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--------------------------------------------------------------------------------------
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Slack (MET) : 2.679ns (required time - arrival time)
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Source: write_back/WB_memory_read_data_reg[1]/C
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(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: memory_access/MEM_ALU_result_reg[24]/D
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(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: clk_out1_phase_locked_loop
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
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Data Path Delay: 17.177ns (logic 7.918ns (46.097%) route 9.259ns (53.903%))
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Logic Levels: 12 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3)
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Clock Path Skew: -0.118ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 )
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Source Clock Delay (SCD): -2.420ns
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Clock Pessimism Removal (CPR): -0.505ns
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Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.203ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock clk_out1_phase_locked_loop rise edge)
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0.000 0.000 r
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R4 0.000 0.000 r hardware_clk (IN)
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net (fo=0) 0.000 0.000 pll/inst/clk_in1
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R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
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net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
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PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
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-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
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net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
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BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
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net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1
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SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C
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------------------------------------------------------------------- -------------------
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SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q
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net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1]
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SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O
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net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0]
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SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O
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net (fo=2, routed) 0.905 3.857 execution/result0__0_3
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SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O
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net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1]
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DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
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4.036 8.665 r execution/alu/result0__0/PCOUT[47]
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net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106
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DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
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1.518 10.185 r execution/alu/result0__1/P[0]
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net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105
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SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O
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net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0
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SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3])
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0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3]
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net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0
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SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3])
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0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3]
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net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0
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SLICE_X12Y18 CARRY4 (Prop_carry4_CI_O[0])
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0.219 12.085 r execution/alu/result0_inferred__11/i__carry__1/O[0]
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net (fo=1, routed) 0.803 12.888 execution/alu/result0_inferred__11/i__carry__1_n_7
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SLICE_X8Y21 LUT4 (Prop_lut4_I3_O) 0.295 13.183 r execution/alu/MEM_ALU_result[24]_i_13/O
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net (fo=1, routed) 0.646 13.829 execution/alu/MEM_ALU_result[24]_i_13_n_0
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SLICE_X5Y21 LUT6 (Prop_lut6_I5_O) 0.124 13.953 r execution/alu/MEM_ALU_result[24]_i_4/O
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net (fo=1, routed) 0.680 14.633 execution/alu/MEM_ALU_result[24]_i_4_n_0
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SLICE_X8Y21 LUT6 (Prop_lut6_I3_O) 0.124 14.757 r execution/alu/MEM_ALU_result[24]_i_1/O
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net (fo=1, routed) 0.000 14.757 memory_access/prev_ALU_result[24]
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SLICE_X8Y21 FDRE r memory_access/MEM_ALU_result_reg[24]/D
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------------------------------------------------------------------- -------------------
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(clock clk_out1_phase_locked_loop rise edge)
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20.000 20.000 r
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R4 0.000 20.000 r hardware_clk (IN)
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net (fo=0) 0.000 20.000 pll/inst/clk_in1
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R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O
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net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop
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PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
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-7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0
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net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop
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BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O
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net (fo=18132, routed) 1.438 17.967 memory_access/clk_out1
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SLICE_X8Y21 FDRE r memory_access/MEM_ALU_result_reg[24]/C
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clock pessimism -0.505 17.462
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clock uncertainty -0.108 17.354
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SLICE_X8Y21 FDRE (Setup_fdre_C_D) 0.081 17.435 memory_access/MEM_ALU_result_reg[24]
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-------------------------------------------------------------------
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required time 17.435
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arrival time -14.757
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-------------------------------------------------------------------
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slack 2.679
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Slack (MET) : 3.013ns (required time - arrival time)
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Source: write_back/WB_memory_read_data_reg[1]/C
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(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: memory_access/MEM_ALU_result_reg[23]/D
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(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: clk_out1_phase_locked_loop
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
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Data Path Delay: 16.858ns (logic 7.909ns (46.917%) route 8.949ns (53.083%))
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Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3)
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Clock Path Skew: -0.051ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -1.966ns = ( 18.034 - 20.000 )
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Source Clock Delay (SCD): -2.420ns
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Clock Pessimism Removal (CPR): -0.505ns
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Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.203ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock clk_out1_phase_locked_loop rise edge)
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0.000 0.000 r
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R4 0.000 0.000 r hardware_clk (IN)
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net (fo=0) 0.000 0.000 pll/inst/clk_in1
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R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
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net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
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PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
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-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
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net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
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BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
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net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1
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SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C
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------------------------------------------------------------------- -------------------
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SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q
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net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1]
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SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O
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net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0]
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SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O
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net (fo=2, routed) 0.905 3.857 execution/result0__0_3
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SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O
|
|
net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1]
|
|
DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
|
|
4.036 8.665 r execution/alu/result0__0/PCOUT[47]
|
|
net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106
|
|
DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
|
|
1.518 10.185 r execution/alu/result0__1/P[0]
|
|
net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105
|
|
SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O
|
|
net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0
|
|
SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3]
|
|
net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0
|
|
SLICE_X12Y17 CARRY4 (Prop_carry4_CI_O[3])
|
|
0.315 12.064 r execution/alu/result0_inferred__11/i__carry__0/O[3]
|
|
net (fo=1, routed) 0.818 12.882 execution/alu/result0_inferred__11/i__carry__0_n_4
|
|
SLICE_X7Y17 LUT4 (Prop_lut4_I3_O) 0.307 13.189 r execution/alu/MEM_ALU_result[23]_i_11/O
|
|
net (fo=1, routed) 0.701 13.891 execution/alu/MEM_ALU_result[23]_i_11_n_0
|
|
SLICE_X3Y21 LUT6 (Prop_lut6_I5_O) 0.124 14.015 r execution/alu/MEM_ALU_result[23]_i_4/O
|
|
net (fo=1, routed) 0.299 14.313 execution/alu/MEM_ALU_result[23]_i_4_n_0
|
|
SLICE_X7Y21 LUT6 (Prop_lut6_I3_O) 0.124 14.437 r execution/alu/MEM_ALU_result[23]_i_1/O
|
|
net (fo=1, routed) 0.000 14.437 memory_access/prev_ALU_result[23]
|
|
SLICE_X7Y21 FDRE r memory_access/MEM_ALU_result_reg[23]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
20.000 20.000 r
|
|
R4 0.000 20.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 20.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.505 18.034 memory_access/clk_out1
|
|
SLICE_X7Y21 FDRE r memory_access/MEM_ALU_result_reg[23]/C
|
|
clock pessimism -0.505 17.529
|
|
clock uncertainty -0.108 17.421
|
|
SLICE_X7Y21 FDRE (Setup_fdre_C_D) 0.029 17.450 memory_access/MEM_ALU_result_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time 17.450
|
|
arrival time -14.437
|
|
-------------------------------------------------------------------
|
|
slack 3.013
|
|
|
|
Slack (MET) : 3.041ns (required time - arrival time)
|
|
Source: write_back/WB_memory_read_data_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: memory_access/MEM_ALU_result_reg[28]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 16.830ns (logic 8.035ns (47.741%) route 8.795ns (52.259%))
|
|
Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=2)
|
|
Clock Path Skew: -0.050ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.965ns = ( 18.035 - 20.000 )
|
|
Source Clock Delay (SCD): -2.420ns
|
|
Clock Pessimism Removal (CPR): -0.505ns
|
|
Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1
|
|
SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q
|
|
net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1]
|
|
SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O
|
|
net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0]
|
|
SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O
|
|
net (fo=2, routed) 0.905 3.857 execution/result0__0_3
|
|
SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O
|
|
net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1]
|
|
DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
|
|
4.036 8.665 r execution/alu/result0__0/PCOUT[47]
|
|
net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106
|
|
DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
|
|
1.518 10.185 r execution/alu/result0__1/P[0]
|
|
net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105
|
|
SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O
|
|
net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0
|
|
SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3]
|
|
net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0
|
|
SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3]
|
|
net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0
|
|
SLICE_X12Y18 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 11.983 r execution/alu/result0_inferred__11/i__carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 11.983 execution/alu/result0_inferred__11/i__carry__1_n_0
|
|
SLICE_X12Y19 CARRY4 (Prop_carry4_CI_O[0])
|
|
0.219 12.202 r execution/alu/result0_inferred__11/i__carry__2/O[0]
|
|
net (fo=1, routed) 0.835 13.037 execution/alu/result0_inferred__11/i__carry__2_n_7
|
|
SLICE_X6Y19 LUT4 (Prop_lut4_I3_O) 0.295 13.332 r execution/alu/MEM_ALU_result[28]_i_12/O
|
|
net (fo=1, routed) 0.427 13.759 execution/alu/MEM_ALU_result[28]_i_12_n_0
|
|
SLICE_X5Y20 LUT5 (Prop_lut5_I4_O) 0.124 13.883 r execution/alu/MEM_ALU_result[28]_i_4/O
|
|
net (fo=1, routed) 0.403 14.286 execution/alu/MEM_ALU_result[28]_i_4_n_0
|
|
SLICE_X5Y20 LUT6 (Prop_lut6_I3_O) 0.124 14.410 r execution/alu/MEM_ALU_result[28]_i_1/O
|
|
net (fo=1, routed) 0.000 14.410 memory_access/prev_ALU_result[28]
|
|
SLICE_X5Y20 FDRE r memory_access/MEM_ALU_result_reg[28]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
20.000 20.000 r
|
|
R4 0.000 20.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 20.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.506 18.035 memory_access/clk_out1
|
|
SLICE_X5Y20 FDRE r memory_access/MEM_ALU_result_reg[28]/C
|
|
clock pessimism -0.505 17.530
|
|
clock uncertainty -0.108 17.422
|
|
SLICE_X5Y20 FDRE (Setup_fdre_C_D) 0.029 17.451 memory_access/MEM_ALU_result_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 17.451
|
|
arrival time -14.410
|
|
-------------------------------------------------------------------
|
|
slack 3.041
|
|
|
|
Slack (MET) : 3.055ns (required time - arrival time)
|
|
Source: write_back/WB_memory_read_data_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: memory_access/MEM_ALU_result_reg[29]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 16.817ns (logic 8.150ns (48.463%) route 8.667ns (51.537%))
|
|
Logic Levels: 13 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=2)
|
|
Clock Path Skew: -0.050ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.965ns = ( 18.035 - 20.000 )
|
|
Source Clock Delay (SCD): -2.420ns
|
|
Clock Pessimism Removal (CPR): -0.505ns
|
|
Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1
|
|
SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q
|
|
net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1]
|
|
SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O
|
|
net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0]
|
|
SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O
|
|
net (fo=2, routed) 0.905 3.857 execution/result0__0_3
|
|
SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O
|
|
net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1]
|
|
DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
|
|
4.036 8.665 r execution/alu/result0__0/PCOUT[47]
|
|
net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106
|
|
DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
|
|
1.518 10.185 r execution/alu/result0__1/P[0]
|
|
net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105
|
|
SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O
|
|
net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0
|
|
SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3]
|
|
net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0
|
|
SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3]
|
|
net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0
|
|
SLICE_X12Y18 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 11.983 r execution/alu/result0_inferred__11/i__carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 11.983 execution/alu/result0_inferred__11/i__carry__1_n_0
|
|
SLICE_X12Y19 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 12.306 r execution/alu/result0_inferred__11/i__carry__2/O[1]
|
|
net (fo=1, routed) 0.600 12.905 execution/alu/result0_inferred__11/i__carry__2_n_6
|
|
SLICE_X6Y19 LUT4 (Prop_lut4_I3_O) 0.306 13.211 r execution/alu/MEM_ALU_result[29]_i_10/O
|
|
net (fo=1, routed) 0.453 13.664 execution/alu/MEM_ALU_result[29]_i_10_n_0
|
|
SLICE_X6Y21 LUT5 (Prop_lut5_I4_O) 0.124 13.788 r execution/alu/MEM_ALU_result[29]_i_4/O
|
|
net (fo=1, routed) 0.484 14.273 execution/alu/MEM_ALU_result[29]_i_4_n_0
|
|
SLICE_X7Y20 LUT6 (Prop_lut6_I3_O) 0.124 14.397 r execution/alu/MEM_ALU_result[29]_i_1/O
|
|
net (fo=1, routed) 0.000 14.397 memory_access/prev_ALU_result[29]
|
|
SLICE_X7Y20 FDRE r memory_access/MEM_ALU_result_reg[29]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
20.000 20.000 r
|
|
R4 0.000 20.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 20.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.506 18.035 memory_access/clk_out1
|
|
SLICE_X7Y20 FDRE r memory_access/MEM_ALU_result_reg[29]/C
|
|
clock pessimism -0.505 17.530
|
|
clock uncertainty -0.108 17.422
|
|
SLICE_X7Y20 FDRE (Setup_fdre_C_D) 0.029 17.451 memory_access/MEM_ALU_result_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time 17.451
|
|
arrival time -14.397
|
|
-------------------------------------------------------------------
|
|
slack 3.055
|
|
|
|
Slack (MET) : 3.160ns (required time - arrival time)
|
|
Source: write_back/WB_memory_read_data_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: memory_access/MEM_ALU_result_reg[30]_rep/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 16.600ns (logic 7.937ns (47.813%) route 8.663ns (52.187%))
|
|
Logic Levels: 12 (CARRY4=4 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=2)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.032ns = ( 17.968 - 20.000 )
|
|
Source Clock Delay (SCD): -2.420ns
|
|
Clock Pessimism Removal (CPR): -0.505ns
|
|
Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1
|
|
SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q
|
|
net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1]
|
|
SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O
|
|
net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0]
|
|
SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O
|
|
net (fo=2, routed) 0.905 3.857 execution/result0__0_3
|
|
SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O
|
|
net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1]
|
|
DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
|
|
4.036 8.665 r execution/alu/result0__0/PCOUT[47]
|
|
net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106
|
|
DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
|
|
1.518 10.185 r execution/alu/result0__1/P[0]
|
|
net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105
|
|
SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O
|
|
net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0
|
|
SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3]
|
|
net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0
|
|
SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3]
|
|
net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0
|
|
SLICE_X12Y18 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 11.983 r execution/alu/result0_inferred__11/i__carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 11.983 execution/alu/result0_inferred__11/i__carry__1_n_0
|
|
SLICE_X12Y19 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 12.222 r execution/alu/result0_inferred__11/i__carry__2/O[2]
|
|
net (fo=1, routed) 0.671 12.892 execution/alu/result0_inferred__11/i__carry__2_n_5
|
|
SLICE_X10Y21 LUT4 (Prop_lut4_I3_O) 0.301 13.193 r execution/alu/MEM_ALU_result[30]_i_3/O
|
|
net (fo=2, routed) 0.294 13.487 execution/alu/MEM_ALU_result[30]_i_3_n_0
|
|
SLICE_X10Y21 LUT6 (Prop_lut6_I2_O) 0.124 13.611 r execution/alu/MEM_ALU_result[30]_rep_i_1/O
|
|
net (fo=1, routed) 0.568 14.180 memory_access/MEM_ALU_result_reg[30]_rep_29
|
|
SLICE_X10Y21 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
20.000 20.000 r
|
|
R4 0.000 20.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 20.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.439 17.968 memory_access/clk_out1
|
|
SLICE_X10Y21 FDRE r memory_access/MEM_ALU_result_reg[30]_rep/C
|
|
clock pessimism -0.505 17.463
|
|
clock uncertainty -0.108 17.355
|
|
SLICE_X10Y21 FDRE (Setup_fdre_C_D) -0.016 17.339 memory_access/MEM_ALU_result_reg[30]_rep
|
|
-------------------------------------------------------------------
|
|
required time 17.339
|
|
arrival time -14.180
|
|
-------------------------------------------------------------------
|
|
slack 3.160
|
|
|
|
Slack (MET) : 3.264ns (required time - arrival time)
|
|
Source: write_back/WB_memory_read_data_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: memory_access/MEM_ALU_result_reg[25]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 16.608ns (logic 8.033ns (48.367%) route 8.575ns (51.633%))
|
|
Logic Levels: 12 (CARRY4=3 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3)
|
|
Clock Path Skew: -0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.966ns = ( 18.034 - 20.000 )
|
|
Source Clock Delay (SCD): -2.420ns
|
|
Clock Pessimism Removal (CPR): -0.505ns
|
|
Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1
|
|
SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q
|
|
net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1]
|
|
SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O
|
|
net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0]
|
|
SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O
|
|
net (fo=2, routed) 0.905 3.857 execution/result0__0_3
|
|
SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O
|
|
net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1]
|
|
DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
|
|
4.036 8.665 r execution/alu/result0__0/PCOUT[47]
|
|
net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106
|
|
DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
|
|
1.518 10.185 r execution/alu/result0__1/P[0]
|
|
net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105
|
|
SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O
|
|
net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0
|
|
SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3]
|
|
net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0
|
|
SLICE_X12Y17 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 11.866 r execution/alu/result0_inferred__11/i__carry__0/CO[3]
|
|
net (fo=1, routed) 0.000 11.866 execution/alu/result0_inferred__11/i__carry__0_n_0
|
|
SLICE_X12Y18 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 12.189 r execution/alu/result0_inferred__11/i__carry__1/O[1]
|
|
net (fo=1, routed) 0.725 12.914 execution/alu/result0_inferred__11/i__carry__1_n_6
|
|
SLICE_X7Y20 LUT4 (Prop_lut4_I3_O) 0.306 13.220 r execution/alu/MEM_ALU_result[25]_i_11/O
|
|
net (fo=1, routed) 0.436 13.656 execution/alu/MEM_ALU_result[25]_i_11_n_0
|
|
SLICE_X4Y21 LUT6 (Prop_lut6_I5_O) 0.124 13.780 r execution/alu/MEM_ALU_result[25]_i_4/O
|
|
net (fo=1, routed) 0.284 14.064 execution/alu/MEM_ALU_result[25]_i_4_n_0
|
|
SLICE_X7Y21 LUT6 (Prop_lut6_I3_O) 0.124 14.188 r execution/alu/MEM_ALU_result[25]_i_1/O
|
|
net (fo=1, routed) 0.000 14.188 memory_access/prev_ALU_result[25]
|
|
SLICE_X7Y21 FDRE r memory_access/MEM_ALU_result_reg[25]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
20.000 20.000 r
|
|
R4 0.000 20.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 20.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.505 18.034 memory_access/clk_out1
|
|
SLICE_X7Y21 FDRE r memory_access/MEM_ALU_result_reg[25]/C
|
|
clock pessimism -0.505 17.529
|
|
clock uncertainty -0.108 17.421
|
|
SLICE_X7Y21 FDRE (Setup_fdre_C_D) 0.031 17.452 memory_access/MEM_ALU_result_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time 17.452
|
|
arrival time -14.188
|
|
-------------------------------------------------------------------
|
|
slack 3.264
|
|
|
|
Slack (MET) : 3.380ns (required time - arrival time)
|
|
Source: write_back/WB_memory_read_data_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: memory_access/MEM_ALU_result_reg[22]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 16.542ns (logic 7.827ns (47.315%) route 8.715ns (52.685%))
|
|
Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3)
|
|
Clock Path Skew: -0.048ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.963ns = ( 18.037 - 20.000 )
|
|
Source Clock Delay (SCD): -2.420ns
|
|
Clock Pessimism Removal (CPR): -0.505ns
|
|
Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1
|
|
SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q
|
|
net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1]
|
|
SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O
|
|
net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0]
|
|
SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O
|
|
net (fo=2, routed) 0.905 3.857 execution/result0__0_3
|
|
SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O
|
|
net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1]
|
|
DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
|
|
4.036 8.665 r execution/alu/result0__0/PCOUT[47]
|
|
net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106
|
|
DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
|
|
1.518 10.185 r execution/alu/result0__1/P[0]
|
|
net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105
|
|
SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O
|
|
net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0
|
|
SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3]
|
|
net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0
|
|
SLICE_X12Y17 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 11.988 r execution/alu/result0_inferred__11/i__carry__0/O[2]
|
|
net (fo=1, routed) 0.579 12.567 execution/alu/result0_inferred__11/i__carry__0_n_5
|
|
SLICE_X7Y17 LUT4 (Prop_lut4_I3_O) 0.301 12.868 r execution/alu/MEM_ALU_result[22]_i_12/O
|
|
net (fo=1, routed) 0.565 13.433 execution/alu/MEM_ALU_result[22]_i_12_n_0
|
|
SLICE_X1Y18 LUT6 (Prop_lut6_I5_O) 0.124 13.557 r execution/alu/MEM_ALU_result[22]_i_4/O
|
|
net (fo=1, routed) 0.441 13.998 execution/alu/MEM_ALU_result[22]_i_4_n_0
|
|
SLICE_X2Y20 LUT6 (Prop_lut6_I3_O) 0.124 14.122 r execution/alu/MEM_ALU_result[22]_i_1/O
|
|
net (fo=1, routed) 0.000 14.122 memory_access/prev_ALU_result[22]
|
|
SLICE_X2Y20 FDRE r memory_access/MEM_ALU_result_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
20.000 20.000 r
|
|
R4 0.000 20.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 20.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.508 18.037 memory_access/clk_out1
|
|
SLICE_X2Y20 FDRE r memory_access/MEM_ALU_result_reg[22]/C
|
|
clock pessimism -0.505 17.532
|
|
clock uncertainty -0.108 17.424
|
|
SLICE_X2Y20 FDRE (Setup_fdre_C_D) 0.077 17.501 memory_access/MEM_ALU_result_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 17.501
|
|
arrival time -14.122
|
|
-------------------------------------------------------------------
|
|
slack 3.380
|
|
|
|
Slack (MET) : 3.438ns (required time - arrival time)
|
|
Source: write_back/WB_memory_read_data_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: memory_access/MEM_ALU_result_reg[21]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 16.488ns (logic 7.916ns (48.011%) route 8.572ns (51.989%))
|
|
Logic Levels: 11 (CARRY4=2 DSP48E1=2 LUT2=1 LUT3=2 LUT4=1 LUT6=3)
|
|
Clock Path Skew: -0.048ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.963ns = ( 18.037 - 20.000 )
|
|
Source Clock Delay (SCD): -2.420ns
|
|
Clock Pessimism Removal (CPR): -0.505ns
|
|
Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1
|
|
SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q
|
|
net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1]
|
|
SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O
|
|
net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0]
|
|
SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O
|
|
net (fo=2, routed) 0.905 3.857 execution/result0__0_3
|
|
SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O
|
|
net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1]
|
|
DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_PCOUT[47])
|
|
4.036 8.665 r execution/alu/result0__0/PCOUT[47]
|
|
net (fo=1, routed) 0.002 8.667 execution/alu/result0__0_n_106
|
|
DSP48_X0Y8 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
|
|
1.518 10.185 r execution/alu/result0__1/P[0]
|
|
net (fo=2, routed) 0.906 11.092 execution/alu/result0__1_n_105
|
|
SLICE_X12Y16 LUT2 (Prop_lut2_I0_O) 0.124 11.216 r execution/alu/i__carry_i_3__0/O
|
|
net (fo=1, routed) 0.000 11.216 execution/alu/i__carry_i_3__0_n_0
|
|
SLICE_X12Y16 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.533 11.749 r execution/alu/result0_inferred__11/i__carry/CO[3]
|
|
net (fo=1, routed) 0.000 11.749 execution/alu/result0_inferred__11/i__carry_n_0
|
|
SLICE_X12Y17 CARRY4 (Prop_carry4_CI_O[1])
|
|
0.323 12.072 r execution/alu/result0_inferred__11/i__carry__0/O[1]
|
|
net (fo=1, routed) 0.697 12.769 execution/alu/result0_inferred__11/i__carry__0_n_6
|
|
SLICE_X5Y17 LUT4 (Prop_lut4_I1_O) 0.306 13.075 r execution/alu/MEM_ALU_result[21]_i_12/O
|
|
net (fo=1, routed) 0.449 13.524 execution/alu/MEM_ALU_result[21]_i_12_n_0
|
|
SLICE_X1Y19 LUT6 (Prop_lut6_I5_O) 0.124 13.648 r execution/alu/MEM_ALU_result[21]_i_4/O
|
|
net (fo=1, routed) 0.295 13.943 execution/alu/MEM_ALU_result[21]_i_4_n_0
|
|
SLICE_X2Y19 LUT6 (Prop_lut6_I3_O) 0.124 14.067 r execution/alu/MEM_ALU_result[21]_i_1/O
|
|
net (fo=1, routed) 0.000 14.067 memory_access/prev_ALU_result[21]
|
|
SLICE_X2Y19 FDRE r memory_access/MEM_ALU_result_reg[21]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
20.000 20.000 r
|
|
R4 0.000 20.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 20.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.508 18.037 memory_access/clk_out1
|
|
SLICE_X2Y19 FDRE r memory_access/MEM_ALU_result_reg[21]/C
|
|
clock pessimism -0.505 17.532
|
|
clock uncertainty -0.108 17.424
|
|
SLICE_X2Y19 FDRE (Setup_fdre_C_D) 0.081 17.505 memory_access/MEM_ALU_result_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time 17.505
|
|
arrival time -14.067
|
|
-------------------------------------------------------------------
|
|
slack 3.438
|
|
|
|
Slack (MET) : 3.466ns (required time - arrival time)
|
|
Source: write_back/WB_memory_read_data_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: memory_access/MEM_ALU_result_reg[3]_rep__18/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 16.324ns (logic 5.041ns (30.880%) route 11.283ns (69.120%))
|
|
Logic Levels: 7 (DSP48E1=1 LUT3=2 LUT6=4)
|
|
Clock Path Skew: -0.040ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.034ns = ( 17.966 - 20.000 )
|
|
Source Clock Delay (SCD): -2.420ns
|
|
Clock Pessimism Removal (CPR): -0.427ns
|
|
Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1
|
|
SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q
|
|
net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1]
|
|
SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O
|
|
net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0]
|
|
SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O
|
|
net (fo=2, routed) 0.905 3.857 execution/result0__0_3
|
|
SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O
|
|
net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1]
|
|
DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_P[3])
|
|
3.841 8.470 r execution/alu/result0__0/P[3]
|
|
net (fo=1, routed) 0.752 9.223 execution/alu/result0__0_n_102
|
|
SLICE_X10Y16 LUT6 (Prop_lut6_I1_O) 0.124 9.347 r execution/alu/MEM_ALU_result[3]_i_10/O
|
|
net (fo=1, routed) 0.452 9.799 execution/alu/MEM_ALU_result[3]_i_10_n_0
|
|
SLICE_X9Y18 LUT6 (Prop_lut6_I5_O) 0.124 9.923 r execution/alu/MEM_ALU_result[3]_i_4/O
|
|
net (fo=34, routed) 3.289 13.212 execution/alu/MEM_ALU_result[3]_i_4_n_0
|
|
SLICE_X43Y99 LUT6 (Prop_lut6_I3_O) 0.124 13.336 r execution/alu/MEM_ALU_result[3]_rep_i_1__18/O
|
|
net (fo=1, routed) 0.568 13.904 memory_access/MEM_ALU_result_reg[3]_rep__18_6
|
|
SLICE_X43Y99 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__18/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
20.000 20.000 r
|
|
R4 0.000 20.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 20.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.438 17.966 memory_access/clk_out1
|
|
SLICE_X43Y99 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__18/C
|
|
clock pessimism -0.427 17.540
|
|
clock uncertainty -0.108 17.432
|
|
SLICE_X43Y99 FDRE (Setup_fdre_C_D) -0.062 17.370 memory_access/MEM_ALU_result_reg[3]_rep__18
|
|
-------------------------------------------------------------------
|
|
required time 17.370
|
|
arrival time -13.904
|
|
-------------------------------------------------------------------
|
|
slack 3.466
|
|
|
|
Slack (MET) : 3.484ns (required time - arrival time)
|
|
Source: write_back/WB_memory_read_data_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: memory_access/MEM_ALU_result_reg[3]_rep__25/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (clk_out1_phase_locked_loop rise@20.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 16.404ns (logic 5.041ns (30.729%) route 11.363ns (69.271%))
|
|
Logic Levels: 7 (DSP48E1=1 LUT3=2 LUT6=4)
|
|
Clock Path Skew: 0.063ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.859ns = ( 18.141 - 20.000 )
|
|
Source Clock Delay (SCD): -2.420ns
|
|
Clock Pessimism Removal (CPR): -0.498ns
|
|
Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.556 -2.420 write_back/clk_out1
|
|
SLICE_X53Y61 FDRE r write_back/WB_memory_read_data_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X53Y61 FDRE (Prop_fdre_C_Q) 0.456 -1.964 r write_back/WB_memory_read_data_reg[1]/Q
|
|
net (fo=10, routed) 2.846 0.882 write_back/WB_memory_read_data[1]
|
|
SLICE_X54Y4 LUT3 (Prop_lut3_I0_O) 0.124 1.006 r write_back/registers[1][1]_i_2/O
|
|
net (fo=35, routed) 1.822 2.828 memory_access/WB_register_write_data[0]
|
|
SLICE_X32Y10 LUT6 (Prop_lut6_I2_O) 0.124 2.952 f memory_access/result0__0_i_22/O
|
|
net (fo=2, routed) 0.905 3.857 execution/result0__0_3
|
|
SLICE_X12Y10 LUT3 (Prop_lut3_I2_O) 0.124 3.981 r execution/result0__0_i_16/O
|
|
net (fo=141, routed) 0.649 4.629 execution/alu/ALU_in1[1]
|
|
DSP48_X0Y7 DSP48E1 (Prop_dsp48e1_A[1]_P[3])
|
|
3.841 8.470 r execution/alu/result0__0/P[3]
|
|
net (fo=1, routed) 0.752 9.223 execution/alu/result0__0_n_102
|
|
SLICE_X10Y16 LUT6 (Prop_lut6_I1_O) 0.124 9.347 r execution/alu/MEM_ALU_result[3]_i_10/O
|
|
net (fo=1, routed) 0.452 9.799 execution/alu/MEM_ALU_result[3]_i_10_n_0
|
|
SLICE_X9Y18 LUT6 (Prop_lut6_I5_O) 0.124 9.923 r execution/alu/MEM_ALU_result[3]_i_4/O
|
|
net (fo=34, routed) 3.324 13.247 execution/alu/MEM_ALU_result[3]_i_4_n_0
|
|
SLICE_X48Y104 LUT6 (Prop_lut6_I3_O) 0.124 13.371 r execution/alu/MEM_ALU_result[3]_rep_i_1__25/O
|
|
net (fo=1, routed) 0.613 13.984 memory_access/MEM_ALU_result_reg[3]_rep__25_2
|
|
SLICE_X48Y104 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__25/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
20.000 20.000 r
|
|
R4 0.000 20.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 20.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 21.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 22.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 14.862 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 16.438 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 16.529 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.612 18.141 memory_access/clk_out1
|
|
SLICE_X48Y104 FDRE r memory_access/MEM_ALU_result_reg[3]_rep__25/C
|
|
clock pessimism -0.498 17.643
|
|
clock uncertainty -0.108 17.535
|
|
SLICE_X48Y104 FDRE (Setup_fdre_C_D) -0.067 17.468 memory_access/MEM_ALU_result_reg[3]_rep__25
|
|
-------------------------------------------------------------------
|
|
required time 17.468
|
|
arrival time -13.984
|
|
-------------------------------------------------------------------
|
|
slack 3.484
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.070ns (arrival time - required time)
|
|
Source: memory_access/MEM_memory_write_data_reg[20]_rep__5/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: data_memory/memory_data_reg[268435472][20]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 0.411ns (logic 0.141ns (34.345%) route 0.270ns (65.655%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.269ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.294ns
|
|
Source Clock Delay (SCD): -0.524ns
|
|
Clock Pessimism Removal (CPR): -0.039ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.563 -0.524 memory_access/clk_out1
|
|
SLICE_X41Y46 FDRE r memory_access/MEM_memory_write_data_reg[20]_rep__5/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y46 FDRE (Prop_fdre_C_Q) 0.141 -0.383 r memory_access/MEM_memory_write_data_reg[20]_rep__5/Q
|
|
net (fo=64, routed) 0.270 -0.114 data_memory/memory_data_reg[268435457][31]_0[20]
|
|
SLICE_X43Y51 FDRE r data_memory/memory_data_reg[268435472][20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.832 -0.294 data_memory/clk_out1
|
|
SLICE_X43Y51 FDRE r data_memory/memory_data_reg[268435472][20]/C
|
|
clock pessimism 0.039 -0.255
|
|
SLICE_X43Y51 FDRE (Hold_fdre_C_D) 0.072 -0.183 data_memory/memory_data_reg[268435472][20]
|
|
-------------------------------------------------------------------
|
|
required time 0.183
|
|
arrival time -0.114
|
|
-------------------------------------------------------------------
|
|
slack 0.070
|
|
|
|
Slack (MET) : 0.079ns (arrival time - required time)
|
|
Source: memory_access/MEM_memory_write_data_reg[25]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: data_memory/memory_data_reg[268435951][25]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 0.313ns (logic 0.141ns (45.059%) route 0.172ns (54.941%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.182ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.291ns
|
|
Source Clock Delay (SCD): -0.440ns
|
|
Clock Pessimism Removal (CPR): -0.034ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.647 -0.440 memory_access/clk_out1
|
|
SLICE_X15Y100 FDRE r memory_access/MEM_memory_write_data_reg[25]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y100 FDRE (Prop_fdre_C_Q) 0.141 -0.299 r memory_access/MEM_memory_write_data_reg[25]/Q
|
|
net (fo=64, routed) 0.172 -0.127 data_memory/memory_data_reg[268435905][31]_0[25]
|
|
SLICE_X14Y98 FDRE r data_memory/memory_data_reg[268435951][25]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.834 -0.291 data_memory/clk_out1
|
|
SLICE_X14Y98 FDRE r data_memory/memory_data_reg[268435951][25]/C
|
|
clock pessimism 0.034 -0.257
|
|
SLICE_X14Y98 FDRE (Hold_fdre_C_D) 0.052 -0.205 data_memory/memory_data_reg[268435951][25]
|
|
-------------------------------------------------------------------
|
|
required time 0.205
|
|
arrival time -0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.079
|
|
|
|
Slack (MET) : 0.080ns (arrival time - required time)
|
|
Source: memory_access/MEM_memory_write_data_reg[0]_rep__4/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: data_memory/memory_data_reg[268435548][0]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 0.413ns (logic 0.164ns (39.691%) route 0.249ns (60.309%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.263ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.299ns
|
|
Source Clock Delay (SCD): -0.528ns
|
|
Clock Pessimism Removal (CPR): -0.034ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.559 -0.528 memory_access/clk_out1
|
|
SLICE_X38Y36 FDRE r memory_access/MEM_memory_write_data_reg[0]_rep__4/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X38Y36 FDRE (Prop_fdre_C_Q) 0.164 -0.364 r memory_access/MEM_memory_write_data_reg[0]_rep__4/Q
|
|
net (fo=64, routed) 0.249 -0.115 data_memory/memory_data_reg[268435521][31]_0[0]
|
|
SLICE_X35Y37 FDRE r data_memory/memory_data_reg[268435548][0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.827 -0.299 data_memory/clk_out1
|
|
SLICE_X35Y37 FDRE r data_memory/memory_data_reg[268435548][0]/C
|
|
clock pessimism 0.034 -0.265
|
|
SLICE_X35Y37 FDRE (Hold_fdre_C_D) 0.070 -0.195 data_memory/memory_data_reg[268435548][0]
|
|
-------------------------------------------------------------------
|
|
required time 0.195
|
|
arrival time -0.115
|
|
-------------------------------------------------------------------
|
|
slack 0.080
|
|
|
|
Slack (MET) : 0.086ns (arrival time - required time)
|
|
Source: memory_access/MEM_memory_write_data_reg[31]_rep__4/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: data_memory/memory_data_reg[268435541][31]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 0.414ns (logic 0.164ns (39.608%) route 0.250ns (60.392%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.262ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.300ns
|
|
Source Clock Delay (SCD): -0.528ns
|
|
Clock Pessimism Removal (CPR): -0.034ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.559 -0.528 memory_access/clk_out1
|
|
SLICE_X38Y36 FDRE r memory_access/MEM_memory_write_data_reg[31]_rep__4/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X38Y36 FDRE (Prop_fdre_C_Q) 0.164 -0.364 r memory_access/MEM_memory_write_data_reg[31]_rep__4/Q
|
|
net (fo=64, routed) 0.250 -0.114 data_memory/memory_data_reg[268435521][31]_0[31]
|
|
SLICE_X35Y36 FDRE r data_memory/memory_data_reg[268435541][31]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.826 -0.300 data_memory/clk_out1
|
|
SLICE_X35Y36 FDRE r data_memory/memory_data_reg[268435541][31]/C
|
|
clock pessimism 0.034 -0.266
|
|
SLICE_X35Y36 FDRE (Hold_fdre_C_D) 0.066 -0.200 data_memory/memory_data_reg[268435541][31]
|
|
-------------------------------------------------------------------
|
|
required time 0.200
|
|
arrival time -0.114
|
|
-------------------------------------------------------------------
|
|
slack 0.086
|
|
|
|
Slack (MET) : 0.092ns (arrival time - required time)
|
|
Source: memory_access/MEM_memory_write_data_reg[31]_rep__4/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: data_memory/memory_data_reg[268435548][31]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 0.425ns (logic 0.164ns (38.560%) route 0.261ns (61.440%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.263ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.299ns
|
|
Source Clock Delay (SCD): -0.528ns
|
|
Clock Pessimism Removal (CPR): -0.034ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.559 -0.528 memory_access/clk_out1
|
|
SLICE_X38Y36 FDRE r memory_access/MEM_memory_write_data_reg[31]_rep__4/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X38Y36 FDRE (Prop_fdre_C_Q) 0.164 -0.364 r memory_access/MEM_memory_write_data_reg[31]_rep__4/Q
|
|
net (fo=64, routed) 0.261 -0.103 data_memory/memory_data_reg[268435521][31]_0[31]
|
|
SLICE_X35Y37 FDRE r data_memory/memory_data_reg[268435548][31]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.827 -0.299 data_memory/clk_out1
|
|
SLICE_X35Y37 FDRE r data_memory/memory_data_reg[268435548][31]/C
|
|
clock pessimism 0.034 -0.265
|
|
SLICE_X35Y37 FDRE (Hold_fdre_C_D) 0.070 -0.195 data_memory/memory_data_reg[268435548][31]
|
|
-------------------------------------------------------------------
|
|
required time 0.195
|
|
arrival time -0.103
|
|
-------------------------------------------------------------------
|
|
slack 0.092
|
|
|
|
Slack (MET) : 0.093ns (arrival time - required time)
|
|
Source: instruction_decode/IFID_PC_plus_4_reg[21]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: instruction_decode/register_file/registers_reg[10][21]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 0.447ns (logic 0.186ns (41.615%) route 0.261ns (58.385%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.262ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.301ns
|
|
Source Clock Delay (SCD): -0.529ns
|
|
Clock Pessimism Removal (CPR): -0.034ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.558 -0.529 instruction_decode/clk_out1
|
|
SLICE_X28Y16 FDRE r instruction_decode/IFID_PC_plus_4_reg[21]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X28Y16 FDRE (Prop_fdre_C_Q) 0.141 -0.388 r instruction_decode/IFID_PC_plus_4_reg[21]/Q
|
|
net (fo=39, routed) 0.261 -0.127 write_back/registers_reg[3][31][21]
|
|
SLICE_X39Y16 LUT6 (Prop_lut6_I3_O) 0.045 -0.082 r write_back/registers[10][21]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.082 instruction_decode/register_file/registers_reg[10][31]_0[21]
|
|
SLICE_X39Y16 FDRE r instruction_decode/register_file/registers_reg[10][21]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.825 -0.301 instruction_decode/register_file/clk_out1
|
|
SLICE_X39Y16 FDRE r instruction_decode/register_file/registers_reg[10][21]/C
|
|
clock pessimism 0.034 -0.267
|
|
SLICE_X39Y16 FDRE (Hold_fdre_C_D) 0.092 -0.175 instruction_decode/register_file/registers_reg[10][21]
|
|
-------------------------------------------------------------------
|
|
required time 0.175
|
|
arrival time -0.082
|
|
-------------------------------------------------------------------
|
|
slack 0.093
|
|
|
|
Slack (MET) : 0.093ns (arrival time - required time)
|
|
Source: memory_access/MEM_memory_write_data_reg[6]_rep__0/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: data_memory/memory_data_reg[268435776][6]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.128ns (33.753%) route 0.251ns (66.247%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.269ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.294ns
|
|
Source Clock Delay (SCD): -0.524ns
|
|
Clock Pessimism Removal (CPR): -0.039ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.563 -0.524 memory_access/clk_out1
|
|
SLICE_X31Y44 FDRE r memory_access/MEM_memory_write_data_reg[6]_rep__0/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X31Y44 FDRE (Prop_fdre_C_Q) 0.128 -0.396 r memory_access/MEM_memory_write_data_reg[6]_rep__0/Q
|
|
net (fo=64, routed) 0.251 -0.145 data_memory/memory_data_reg[268435777][31]_0[6]
|
|
SLICE_X28Y51 FDRE r data_memory/memory_data_reg[268435776][6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.832 -0.294 data_memory/clk_out1
|
|
SLICE_X28Y51 FDRE r data_memory/memory_data_reg[268435776][6]/C
|
|
clock pessimism 0.039 -0.255
|
|
SLICE_X28Y51 FDRE (Hold_fdre_C_D) 0.017 -0.238 data_memory/memory_data_reg[268435776][6]
|
|
-------------------------------------------------------------------
|
|
required time 0.238
|
|
arrival time -0.145
|
|
-------------------------------------------------------------------
|
|
slack 0.093
|
|
|
|
Slack (MET) : 0.094ns (arrival time - required time)
|
|
Source: memory_access/MEM_memory_write_data_reg[7]_rep__2/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: data_memory/memory_data_reg[268435711][7]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 0.373ns (logic 0.128ns (34.278%) route 0.245ns (65.722%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.261ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.222ns
|
|
Source Clock Delay (SCD): -0.453ns
|
|
Clock Pessimism Removal (CPR): -0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.634 -0.453 memory_access/clk_out1
|
|
SLICE_X32Y129 FDRE r memory_access/MEM_memory_write_data_reg[7]_rep__2/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X32Y129 FDRE (Prop_fdre_C_Q) 0.128 -0.325 r memory_access/MEM_memory_write_data_reg[7]_rep__2/Q
|
|
net (fo=64, routed) 0.245 -0.079 data_memory/memory_data_reg[268435649][31]_0[7]
|
|
SLICE_X37Y128 FDRE r data_memory/memory_data_reg[268435711][7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.904 -0.222 data_memory/clk_out1
|
|
SLICE_X37Y128 FDRE r data_memory/memory_data_reg[268435711][7]/C
|
|
clock pessimism 0.030 -0.192
|
|
SLICE_X37Y128 FDRE (Hold_fdre_C_D) 0.019 -0.173 data_memory/memory_data_reg[268435711][7]
|
|
-------------------------------------------------------------------
|
|
required time 0.173
|
|
arrival time -0.079
|
|
-------------------------------------------------------------------
|
|
slack 0.094
|
|
|
|
Slack (MET) : 0.097ns (arrival time - required time)
|
|
Source: memory_access/MEM_memory_write_data_reg[7]_rep__2/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: data_memory/memory_data_reg[268435708][7]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 0.376ns (logic 0.128ns (34.010%) route 0.248ns (65.990%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.261ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.222ns
|
|
Source Clock Delay (SCD): -0.453ns
|
|
Clock Pessimism Removal (CPR): -0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.634 -0.453 memory_access/clk_out1
|
|
SLICE_X32Y129 FDRE r memory_access/MEM_memory_write_data_reg[7]_rep__2/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X32Y129 FDRE (Prop_fdre_C_Q) 0.128 -0.325 r memory_access/MEM_memory_write_data_reg[7]_rep__2/Q
|
|
net (fo=64, routed) 0.248 -0.076 data_memory/memory_data_reg[268435649][31]_0[7]
|
|
SLICE_X36Y128 FDRE r data_memory/memory_data_reg[268435708][7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.904 -0.222 data_memory/clk_out1
|
|
SLICE_X36Y128 FDRE r data_memory/memory_data_reg[268435708][7]/C
|
|
clock pessimism 0.030 -0.192
|
|
SLICE_X36Y128 FDRE (Hold_fdre_C_D) 0.019 -0.173 data_memory/memory_data_reg[268435708][7]
|
|
-------------------------------------------------------------------
|
|
required time 0.173
|
|
arrival time -0.076
|
|
-------------------------------------------------------------------
|
|
slack 0.097
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: memory_access/MEM_memory_write_data_reg[5]_rep__1/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: data_memory/memory_data_reg[268435761][5]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: clk_out1_phase_locked_loop
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_out1_phase_locked_loop rise@0.000ns - clk_out1_phase_locked_loop rise@0.000ns)
|
|
Data Path Delay: 0.433ns (logic 0.141ns (32.546%) route 0.292ns (67.454%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.255ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.312ns
|
|
Source Clock Delay (SCD): -0.533ns
|
|
Clock Pessimism Removal (CPR): -0.034ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.554 -0.533 memory_access/clk_out1
|
|
SLICE_X36Y81 FDRE r memory_access/MEM_memory_write_data_reg[5]_rep__1/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y81 FDRE (Prop_fdre_C_Q) 0.141 -0.392 r memory_access/MEM_memory_write_data_reg[5]_rep__1/Q
|
|
net (fo=64, routed) 0.292 -0.100 data_memory/memory_data_reg[268435713][31]_0[5]
|
|
SLICE_X32Y75 FDRE r data_memory/memory_data_reg[268435761][5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.813 -0.312 data_memory/clk_out1
|
|
SLICE_X32Y75 FDRE r data_memory/memory_data_reg[268435761][5]/C
|
|
clock pessimism 0.034 -0.278
|
|
SLICE_X32Y75 FDRE (Hold_fdre_C_D) 0.070 -0.208 data_memory/memory_data_reg[268435761][5]
|
|
-------------------------------------------------------------------
|
|
required time 0.208
|
|
arrival time -0.100
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: clk_out1_phase_locked_loop
|
|
Waveform(ns): { 0.000 10.000 }
|
|
Period(ns): 20.000
|
|
Sources: { pll/inst/plle2_adv_inst/CLKOUT0 }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y0 pll/inst/clkout1_buf/I
|
|
Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 20.000 18.751 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKOUT0
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X32Y31 data_memory/memory_data_reg[268435456][14]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X32Y31 data_memory/memory_data_reg[268435456][15]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X48Y54 data_memory/memory_data_reg[268435456][16]/C
|
|
Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 20.000 140.000 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKOUT0
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X39Y38 data_memory/memory_data_reg[268435456][0]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][10]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X59Y38 data_memory/memory_data_reg[268435456][11]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X32Y31 data_memory/memory_data_reg[268435456][12]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X61Y20 data_memory/memory_data_reg[268435456][13]/C
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: clkfbout_phase_locked_loop
|
|
To Clock: clkfbout_phase_locked_loop
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: clkfbout_phase_locked_loop
|
|
Waveform(ns): { 0.000 10.000 }
|
|
Period(ns): 20.000
|
|
Sources: { pll/inst/plle2_adv_inst/CLKFBOUT }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y1 pll/inst/clkf_buf/I
|
|
Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKFBOUT
|
|
Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKFBIN
|
|
Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKFBIN
|
|
Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 140.000 PLLE2_ADV_X1Y0 pll/inst/plle2_adv_inst/CLKFBOUT
|
|
|
|
|
|
|
|
--------------------------------------------------------------------------------------
|
|
Path Group: (none)
|
|
From Clock: clk_out1_phase_locked_loop
|
|
To Clock:
|
|
|
|
Max Delay 12 Endpoints
|
|
Min Delay 12 Endpoints
|
|
--------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][0]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[0]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 6.786ns (logic 3.997ns (58.900%) route 2.789ns (41.100%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.566 -2.410 data_memory/clk_out1
|
|
SLICE_X45Y42 FDRE r data_memory/memory_data_reg[268435460][0]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X45Y42 FDRE (Prop_fdre_C_Q) 0.456 -1.954 r data_memory/memory_data_reg[268435460][0]_lopt_replica/Q
|
|
net (fo=1, routed) 2.789 0.835 lopt
|
|
N2 OBUF (Prop_obuf_I_O) 3.541 4.376 r bcd_control_OBUF[0]_inst/O
|
|
net (fo=0) 0.000 4.376 bcd_control[0]
|
|
N2 r bcd_control[0] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][11]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[11]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 6.606ns (logic 3.992ns (60.431%) route 2.614ns (39.569%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.637 -2.339 data_memory/clk_out1
|
|
SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][11]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.456 -1.883 r data_memory/memory_data_reg[268435460][11]_lopt_replica/Q
|
|
net (fo=1, routed) 2.614 0.731 lopt_2
|
|
M2 OBUF (Prop_obuf_I_O) 3.536 4.267 r bcd_control_OBUF[11]_inst/O
|
|
net (fo=0) 0.000 4.267 bcd_control[11]
|
|
M2 r bcd_control[11] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][8]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[8]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 6.536ns (logic 4.160ns (63.646%) route 2.376ns (36.354%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.551 -2.425 data_memory/clk_out1
|
|
SLICE_X51Y24 FDRE r data_memory/memory_data_reg[268435460][8]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X51Y24 FDRE (Prop_fdre_C_Q) 0.419 -2.006 r data_memory/memory_data_reg[268435460][8]_lopt_replica/Q
|
|
net (fo=1, routed) 2.376 0.370 lopt_10
|
|
Y3 OBUF (Prop_obuf_I_O) 3.741 4.111 r bcd_control_OBUF[8]_inst/O
|
|
net (fo=0) 0.000 4.111 bcd_control[8]
|
|
Y3 r bcd_control[8] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][9]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[9]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 6.422ns (logic 4.016ns (62.541%) route 2.406ns (37.459%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.637 -2.339 data_memory/clk_out1
|
|
SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.456 -1.883 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q
|
|
net (fo=1, routed) 2.406 0.523 lopt_11
|
|
R1 OBUF (Prop_obuf_I_O) 3.560 4.083 r bcd_control_OBUF[9]_inst/O
|
|
net (fo=0) 0.000 4.083 bcd_control[9]
|
|
R1 r bcd_control[9] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][5]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[5]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 6.274ns (logic 4.014ns (63.978%) route 2.260ns (36.022%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.637 -2.339 data_memory/clk_out1
|
|
SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.456 -1.883 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q
|
|
net (fo=1, routed) 2.260 0.377 lopt_7
|
|
P1 OBUF (Prop_obuf_I_O) 3.558 3.935 r bcd_control_OBUF[5]_inst/O
|
|
net (fo=0) 0.000 3.935 bcd_control[5]
|
|
P1 r bcd_control[5] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][3]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[3]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 6.329ns (logic 4.012ns (63.387%) route 2.317ns (36.613%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.551 -2.425 data_memory/clk_out1
|
|
SLICE_X51Y24 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X51Y24 FDRE (Prop_fdre_C_Q) 0.456 -1.969 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q
|
|
net (fo=1, routed) 2.317 0.348 lopt_5
|
|
U5 OBUF (Prop_obuf_I_O) 3.556 3.904 r bcd_control_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 3.904 bcd_control[3]
|
|
U5 r bcd_control[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][1]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[1]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 6.098ns (logic 3.991ns (65.436%) route 2.108ns (34.564%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.637 -2.339 data_memory/clk_out1
|
|
SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][1]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.456 -1.883 r data_memory/memory_data_reg[268435460][1]_lopt_replica/Q
|
|
net (fo=1, routed) 2.108 0.225 lopt_3
|
|
P5 OBUF (Prop_obuf_I_O) 3.535 3.759 r bcd_control_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 3.759 bcd_control[1]
|
|
P5 r bcd_control[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][6]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[6]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 6.088ns (logic 4.010ns (65.856%) route 2.079ns (34.144%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.635 -2.341 data_memory/clk_out1
|
|
SLICE_X65Y38 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y38 FDRE (Prop_fdre_C_Q) 0.456 -1.885 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q
|
|
net (fo=1, routed) 2.079 0.194 lopt_8
|
|
W4 OBUF (Prop_obuf_I_O) 3.554 3.747 r bcd_control_OBUF[6]_inst/O
|
|
net (fo=0) 0.000 3.747 bcd_control[6]
|
|
W4 r bcd_control[6] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][10]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[10]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 6.059ns (logic 4.000ns (66.015%) route 2.059ns (33.985%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.638 -2.338 data_memory/clk_out1
|
|
SLICE_X65Y46 FDRE r data_memory/memory_data_reg[268435460][10]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y46 FDRE (Prop_fdre_C_Q) 0.456 -1.882 r data_memory/memory_data_reg[268435460][10]_lopt_replica/Q
|
|
net (fo=1, routed) 2.059 0.177 lopt_1
|
|
P2 OBUF (Prop_obuf_I_O) 3.544 3.721 r bcd_control_OBUF[10]_inst/O
|
|
net (fo=0) 0.000 3.721 bcd_control[10]
|
|
P2 r bcd_control[10] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][4]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[4]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 5.732ns (logic 4.011ns (69.973%) route 1.721ns (30.027%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.501 1.501 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.754 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.482 -5.728 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.655 -4.072 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -3.976 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.630 -2.346 data_memory/clk_out1
|
|
SLICE_X65Y16 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y16 FDRE (Prop_fdre_C_Q) 0.456 -1.890 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q
|
|
net (fo=1, routed) 1.721 -0.169 lopt_6
|
|
T5 OBUF (Prop_obuf_I_O) 3.555 3.386 r bcd_control_OBUF[4]_inst/O
|
|
net (fo=0) 0.000 3.386 bcd_control[4]
|
|
T5 r bcd_control[4] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][2]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[2]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.697ns (logic 1.369ns (80.669%) route 0.328ns (19.331%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.590 -0.497 data_memory/clk_out1
|
|
SLICE_X65Y16 FDRE r data_memory/memory_data_reg[268435460][2]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y16 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r data_memory/memory_data_reg[268435460][2]_lopt_replica/Q
|
|
net (fo=1, routed) 0.328 -0.028 lopt_4
|
|
V5 OBUF (Prop_obuf_I_O) 1.228 1.200 r bcd_control_OBUF[2]_inst/O
|
|
net (fo=0) 0.000 1.200 bcd_control[2]
|
|
V5 r bcd_control[2] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][7]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[7]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.727ns (logic 1.392ns (80.615%) route 0.335ns (19.385%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.593 -0.494 data_memory/clk_out1
|
|
SLICE_X65Y38 FDRE r data_memory/memory_data_reg[268435460][7]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][7]_lopt_replica/Q
|
|
net (fo=1, routed) 0.335 -0.018 lopt_9
|
|
V3 OBUF (Prop_obuf_I_O) 1.251 1.233 r bcd_control_OBUF[7]_inst/O
|
|
net (fo=0) 0.000 1.233 bcd_control[7]
|
|
V3 r bcd_control[7] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][4]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[4]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.760ns (logic 1.397ns (79.361%) route 0.363ns (20.639%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.590 -0.497 data_memory/clk_out1
|
|
SLICE_X65Y16 FDRE r data_memory/memory_data_reg[268435460][4]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y16 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r data_memory/memory_data_reg[268435460][4]_lopt_replica/Q
|
|
net (fo=1, routed) 0.363 0.007 lopt_6
|
|
T5 OBUF (Prop_obuf_I_O) 1.256 1.263 r bcd_control_OBUF[4]_inst/O
|
|
net (fo=0) 0.000 1.263 bcd_control[4]
|
|
T5 r bcd_control[4] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][10]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[10]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.885ns (logic 1.386ns (73.515%) route 0.499ns (26.485%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.595 -0.492 data_memory/clk_out1
|
|
SLICE_X65Y46 FDRE r data_memory/memory_data_reg[268435460][10]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y46 FDRE (Prop_fdre_C_Q) 0.141 -0.351 r data_memory/memory_data_reg[268435460][10]_lopt_replica/Q
|
|
net (fo=1, routed) 0.499 0.148 lopt_1
|
|
P2 OBUF (Prop_obuf_I_O) 1.245 1.393 r bcd_control_OBUF[10]_inst/O
|
|
net (fo=0) 0.000 1.393 bcd_control[10]
|
|
P2 r bcd_control[10] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][6]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[6]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.887ns (logic 1.395ns (73.937%) route 0.492ns (26.063%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.593 -0.494 data_memory/clk_out1
|
|
SLICE_X65Y38 FDRE r data_memory/memory_data_reg[268435460][6]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.353 r data_memory/memory_data_reg[268435460][6]_lopt_replica/Q
|
|
net (fo=1, routed) 0.492 0.139 lopt_8
|
|
W4 OBUF (Prop_obuf_I_O) 1.254 1.393 r bcd_control_OBUF[6]_inst/O
|
|
net (fo=0) 0.000 1.393 bcd_control[6]
|
|
W4 r bcd_control[6] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][1]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[1]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.902ns (logic 1.376ns (72.357%) route 0.526ns (27.643%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.594 -0.493 data_memory/clk_out1
|
|
SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][1]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][1]_lopt_replica/Q
|
|
net (fo=1, routed) 0.526 0.174 lopt_3
|
|
P5 OBUF (Prop_obuf_I_O) 1.235 1.409 r bcd_control_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 1.409 bcd_control[1]
|
|
P5 r bcd_control[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][5]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[5]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.987ns (logic 1.400ns (70.452%) route 0.587ns (29.548%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.594 -0.493 data_memory/clk_out1
|
|
SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][5]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][5]_lopt_replica/Q
|
|
net (fo=1, routed) 0.587 0.235 lopt_7
|
|
P1 OBUF (Prop_obuf_I_O) 1.259 1.493 r bcd_control_OBUF[5]_inst/O
|
|
net (fo=0) 0.000 1.493 bcd_control[5]
|
|
P1 r bcd_control[5] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][3]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[3]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.034ns (logic 1.397ns (68.715%) route 0.636ns (31.285%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.553 -0.534 data_memory/clk_out1
|
|
SLICE_X51Y24 FDRE r data_memory/memory_data_reg[268435460][3]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X51Y24 FDRE (Prop_fdre_C_Q) 0.141 -0.393 r data_memory/memory_data_reg[268435460][3]_lopt_replica/Q
|
|
net (fo=1, routed) 0.636 0.243 lopt_5
|
|
U5 OBUF (Prop_obuf_I_O) 1.256 1.499 r bcd_control_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 1.499 bcd_control[3]
|
|
U5 r bcd_control[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][9]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[9]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.044ns (logic 1.402ns (68.602%) route 0.642ns (31.398%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.594 -0.493 data_memory/clk_out1
|
|
SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][9]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][9]_lopt_replica/Q
|
|
net (fo=1, routed) 0.642 0.289 lopt_11
|
|
R1 OBUF (Prop_obuf_I_O) 1.261 1.551 r bcd_control_OBUF[9]_inst/O
|
|
net (fo=0) 0.000 1.551 bcd_control[9]
|
|
R1 r bcd_control[9] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: data_memory/memory_data_reg[268435460][11]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: bcd_control[11]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.108ns (logic 1.378ns (65.371%) route 0.730ns (34.629%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.269 0.269 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.709 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.322 -1.614 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.501 -1.113 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.087 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.594 -0.493 data_memory/clk_out1
|
|
SLICE_X65Y41 FDRE r data_memory/memory_data_reg[268435460][11]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X65Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.352 r data_memory/memory_data_reg[268435460][11]_lopt_replica/Q
|
|
net (fo=1, routed) 0.730 0.378 lopt_2
|
|
M2 OBUF (Prop_obuf_I_O) 1.237 1.615 r bcd_control_OBUF[11]_inst/O
|
|
net (fo=0) 0.000 1.615 bcd_control[11]
|
|
M2 r bcd_control[11] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
|
|
|
|
|
|
|
|
--------------------------------------------------------------------------------------
|
|
Path Group: (none)
|
|
From Clock: clkfbout_phase_locked_loop
|
|
To Clock:
|
|
|
|
Max Delay 1 Endpoint
|
|
Min Delay 1 Endpoint
|
|
--------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: pll/inst/plle2_adv_inst/CLKFBOUT
|
|
(clock source 'clkfbout_phase_locked_loop' {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: pll/inst/plle2_adv_inst/CLKFBIN
|
|
Path Group: (none)
|
|
Path Type: Max at Fast Process Corner
|
|
Data Path Delay: 1.396ns (logic 0.029ns (2.077%) route 1.367ns (97.923%))
|
|
Logic Levels: 1 (BUFG=1)
|
|
Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clkfbout_phase_locked_loop fall edge)
|
|
10.000 10.000 f
|
|
R4 0.000 10.000 f hardware_clk (IN)
|
|
net (fo=0) 0.000 10.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 10.457 f pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 10.938 pll/inst/clk_in1_phase_locked_loop
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT)
|
|
-2.638 8.300 f pll/inst/plle2_adv_inst/CLKFBOUT
|
|
net (fo=1, routed) 0.546 8.845 pll/inst/clkfbout_phase_locked_loop
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 8.874 f pll/inst/clkf_buf/O
|
|
net (fo=1, routed) 0.822 9.696 pll/inst/clkfbout_buf_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV f pll/inst/plle2_adv_inst/CLKFBIN
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: pll/inst/plle2_adv_inst/CLKFBOUT
|
|
(clock source 'clkfbout_phase_locked_loop' {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: pll/inst/plle2_adv_inst/CLKFBIN
|
|
Path Group: (none)
|
|
Path Type: Min at Slow Process Corner
|
|
Data Path Delay: 3.146ns (logic 0.091ns (2.892%) route 3.055ns (97.108%))
|
|
Logic Levels: 1 (BUFG=1)
|
|
Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.119ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clkfbout_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT)
|
|
-7.750 -5.138 r pll/inst/plle2_adv_inst/CLKFBOUT
|
|
net (fo=1, routed) 1.576 -3.562 pll/inst/clkfbout_phase_locked_loop
|
|
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkf_buf/O
|
|
net (fo=1, routed) 1.479 -1.992 pll/inst/clkfbout_buf_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV r pll/inst/plle2_adv_inst/CLKFBIN
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
|
|
|
|
|
|
|
|
--------------------------------------------------------------------------------------
|
|
Path Group: (none)
|
|
From Clock:
|
|
To Clock: clk_out1_phase_locked_loop
|
|
|
|
Max Delay 18132 Endpoints
|
|
Min Delay 18132 Endpoints
|
|
--------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: hardware_reset
|
|
(input port)
|
|
Destination: data_memory/memory_data_reg[268435704][15]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Data Path Delay: 16.011ns (logic 1.650ns (10.304%) route 14.362ns (89.696%))
|
|
Logic Levels: 2 (IBUF=1 LUT2=1)
|
|
Clock Path Skew: -1.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.858ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
B22 0.000 0.000 r hardware_reset (IN)
|
|
net (fo=0) 0.000 0.000 hardware_reset
|
|
B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O
|
|
net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 9.503 16.011 data_memory/reset
|
|
SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][15]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1
|
|
SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][15]/C
|
|
|
|
Slack: inf
|
|
Source: hardware_reset
|
|
(input port)
|
|
Destination: data_memory/memory_data_reg[268435704][20]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Data Path Delay: 16.011ns (logic 1.650ns (10.304%) route 14.362ns (89.696%))
|
|
Logic Levels: 2 (IBUF=1 LUT2=1)
|
|
Clock Path Skew: -1.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.858ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
B22 0.000 0.000 r hardware_reset (IN)
|
|
net (fo=0) 0.000 0.000 hardware_reset
|
|
B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O
|
|
net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 9.503 16.011 data_memory/reset
|
|
SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][20]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1
|
|
SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][20]/C
|
|
|
|
Slack: inf
|
|
Source: hardware_reset
|
|
(input port)
|
|
Destination: data_memory/memory_data_reg[268435704][26]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Data Path Delay: 16.011ns (logic 1.650ns (10.304%) route 14.362ns (89.696%))
|
|
Logic Levels: 2 (IBUF=1 LUT2=1)
|
|
Clock Path Skew: -1.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.858ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
B22 0.000 0.000 r hardware_reset (IN)
|
|
net (fo=0) 0.000 0.000 hardware_reset
|
|
B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O
|
|
net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 9.503 16.011 data_memory/reset
|
|
SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][26]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1
|
|
SLICE_X22Y143 FDRE r data_memory/memory_data_reg[268435704][26]/C
|
|
|
|
Slack: inf
|
|
Source: hardware_reset
|
|
(input port)
|
|
Destination: data_memory/memory_data_reg[268435653][20]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Data Path Delay: 16.011ns (logic 1.650ns (10.304%) route 14.361ns (89.696%))
|
|
Logic Levels: 2 (IBUF=1 LUT2=1)
|
|
Clock Path Skew: -1.857ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.857ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
B22 0.000 0.000 r hardware_reset (IN)
|
|
net (fo=0) 0.000 0.000 hardware_reset
|
|
B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O
|
|
net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 9.503 16.011 data_memory/reset
|
|
SLICE_X16Y144 FDRE r data_memory/memory_data_reg[268435653][20]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.614 -1.857 data_memory/clk_out1
|
|
SLICE_X16Y144 FDRE r data_memory/memory_data_reg[268435653][20]/C
|
|
|
|
Slack: inf
|
|
Source: hardware_reset
|
|
(input port)
|
|
Destination: data_memory/memory_data_reg[268435680][23]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Data Path Delay: 16.010ns (logic 1.650ns (10.304%) route 14.360ns (89.696%))
|
|
Logic Levels: 2 (IBUF=1 LUT2=1)
|
|
Clock Path Skew: -1.859ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.859ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
B22 0.000 0.000 r hardware_reset (IN)
|
|
net (fo=0) 0.000 0.000 hardware_reset
|
|
B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O
|
|
net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 9.502 16.010 data_memory/reset
|
|
SLICE_X11Y138 FDRE r data_memory/memory_data_reg[268435680][23]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.612 -1.859 data_memory/clk_out1
|
|
SLICE_X11Y138 FDRE r data_memory/memory_data_reg[268435680][23]/C
|
|
|
|
Slack: inf
|
|
Source: hardware_reset
|
|
(input port)
|
|
Destination: data_memory/memory_data_reg[268435680][25]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Data Path Delay: 16.010ns (logic 1.650ns (10.304%) route 14.360ns (89.696%))
|
|
Logic Levels: 2 (IBUF=1 LUT2=1)
|
|
Clock Path Skew: -1.859ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.859ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
B22 0.000 0.000 r hardware_reset (IN)
|
|
net (fo=0) 0.000 0.000 hardware_reset
|
|
B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O
|
|
net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 9.502 16.010 data_memory/reset
|
|
SLICE_X11Y138 FDRE r data_memory/memory_data_reg[268435680][25]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.612 -1.859 data_memory/clk_out1
|
|
SLICE_X11Y138 FDRE r data_memory/memory_data_reg[268435680][25]/C
|
|
|
|
Slack: inf
|
|
Source: hardware_reset
|
|
(input port)
|
|
Destination: data_memory/memory_data_reg[268435685][23]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Data Path Delay: 16.010ns (logic 1.650ns (10.304%) route 14.360ns (89.696%))
|
|
Logic Levels: 2 (IBUF=1 LUT2=1)
|
|
Clock Path Skew: -1.859ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.859ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
B22 0.000 0.000 r hardware_reset (IN)
|
|
net (fo=0) 0.000 0.000 hardware_reset
|
|
B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O
|
|
net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 9.502 16.010 data_memory/reset
|
|
SLICE_X10Y138 FDRE r data_memory/memory_data_reg[268435685][23]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.612 -1.859 data_memory/clk_out1
|
|
SLICE_X10Y138 FDRE r data_memory/memory_data_reg[268435685][23]/C
|
|
|
|
Slack: inf
|
|
Source: hardware_reset
|
|
(input port)
|
|
Destination: data_memory/memory_data_reg[268435685][25]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Data Path Delay: 16.010ns (logic 1.650ns (10.304%) route 14.360ns (89.696%))
|
|
Logic Levels: 2 (IBUF=1 LUT2=1)
|
|
Clock Path Skew: -1.859ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.859ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
B22 0.000 0.000 r hardware_reset (IN)
|
|
net (fo=0) 0.000 0.000 hardware_reset
|
|
B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O
|
|
net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 9.502 16.010 data_memory/reset
|
|
SLICE_X10Y138 FDRE r data_memory/memory_data_reg[268435685][25]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.612 -1.859 data_memory/clk_out1
|
|
SLICE_X10Y138 FDRE r data_memory/memory_data_reg[268435685][25]/C
|
|
|
|
Slack: inf
|
|
Source: hardware_reset
|
|
(input port)
|
|
Destination: data_memory/memory_data_reg[268435705][15]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Data Path Delay: 16.007ns (logic 1.650ns (10.306%) route 14.357ns (89.694%))
|
|
Logic Levels: 2 (IBUF=1 LUT2=1)
|
|
Clock Path Skew: -1.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.858ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
B22 0.000 0.000 r hardware_reset (IN)
|
|
net (fo=0) 0.000 0.000 hardware_reset
|
|
B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O
|
|
net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 9.499 16.007 data_memory/reset
|
|
SLICE_X23Y143 FDRE r data_memory/memory_data_reg[268435705][15]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1
|
|
SLICE_X23Y143 FDRE r data_memory/memory_data_reg[268435705][15]/C
|
|
|
|
Slack: inf
|
|
Source: hardware_reset
|
|
(input port)
|
|
Destination: data_memory/memory_data_reg[268435705][20]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Data Path Delay: 16.007ns (logic 1.650ns (10.306%) route 14.357ns (89.694%))
|
|
Logic Levels: 2 (IBUF=1 LUT2=1)
|
|
Clock Path Skew: -1.858ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.858ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
B22 0.000 0.000 r hardware_reset (IN)
|
|
net (fo=0) 0.000 0.000 hardware_reset
|
|
B22 IBUF (Prop_ibuf_I_O) 1.526 1.526 r hardware_reset_IBUF_inst/O
|
|
net (fo=2, routed) 4.858 6.384 data_memory/memory_data_reg[268435457][0]_0
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I0_O) 0.124 6.508 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 9.499 16.007 data_memory/reset
|
|
SLICE_X23Y143 FDRE r data_memory/memory_data_reg[268435705][20]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 1.430 1.430 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.611 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-7.750 -5.138 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.576 -3.562 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -3.471 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 1.613 -1.858 data_memory/clk_out1
|
|
SLICE_X23Y143 FDRE r data_memory/memory_data_reg[268435705][20]/C
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: pll/inst/plle2_adv_inst/LOCKED
|
|
(internal pin)
|
|
Destination: data_memory/memory_data_reg[268435474][6]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 0.947ns (logic 0.045ns (4.750%) route 0.902ns (95.250%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED
|
|
net (fo=2, routed) 0.377 0.377 data_memory/locked
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 0.525 0.947 data_memory/reset
|
|
SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435474][6]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1
|
|
SLICE_X65Y49 FDRE r data_memory/memory_data_reg[268435474][6]/C
|
|
|
|
Slack: inf
|
|
Source: pll/inst/plle2_adv_inst/LOCKED
|
|
(internal pin)
|
|
Destination: data_memory/memory_data_reg[268435475][6]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 0.947ns (logic 0.045ns (4.750%) route 0.902ns (95.250%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED
|
|
net (fo=2, routed) 0.377 0.377 data_memory/locked
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 0.525 0.947 data_memory/reset
|
|
SLICE_X64Y49 FDRE r data_memory/memory_data_reg[268435475][6]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1
|
|
SLICE_X64Y49 FDRE r data_memory/memory_data_reg[268435475][6]/C
|
|
|
|
Slack: inf
|
|
Source: pll/inst/plle2_adv_inst/LOCKED
|
|
(internal pin)
|
|
Destination: data_memory/memory_data_reg[268435485][6]/S
|
|
(rising edge-triggered cell FDSE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 0.980ns (logic 0.045ns (4.590%) route 0.935ns (95.410%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED
|
|
net (fo=2, routed) 0.377 0.377 data_memory/locked
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 0.558 0.980 data_memory/reset
|
|
SLICE_X63Y49 FDSE r data_memory/memory_data_reg[268435485][6]/S
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1
|
|
SLICE_X63Y49 FDSE r data_memory/memory_data_reg[268435485][6]/C
|
|
|
|
Slack: inf
|
|
Source: pll/inst/plle2_adv_inst/LOCKED
|
|
(internal pin)
|
|
Destination: data_memory/memory_data_reg[268435524][21]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED
|
|
net (fo=2, routed) 0.377 0.377 data_memory/locked
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 0.562 0.985 data_memory/reset
|
|
SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][21]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1
|
|
SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][21]/C
|
|
|
|
Slack: inf
|
|
Source: pll/inst/plle2_adv_inst/LOCKED
|
|
(internal pin)
|
|
Destination: data_memory/memory_data_reg[268435524][23]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED
|
|
net (fo=2, routed) 0.377 0.377 data_memory/locked
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 0.562 0.985 data_memory/reset
|
|
SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][23]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1
|
|
SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][23]/C
|
|
|
|
Slack: inf
|
|
Source: pll/inst/plle2_adv_inst/LOCKED
|
|
(internal pin)
|
|
Destination: data_memory/memory_data_reg[268435524][28]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED
|
|
net (fo=2, routed) 0.377 0.377 data_memory/locked
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 0.562 0.985 data_memory/reset
|
|
SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][28]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1
|
|
SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][28]/C
|
|
|
|
Slack: inf
|
|
Source: pll/inst/plle2_adv_inst/LOCKED
|
|
(internal pin)
|
|
Destination: data_memory/memory_data_reg[268435524][29]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED
|
|
net (fo=2, routed) 0.377 0.377 data_memory/locked
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 0.562 0.985 data_memory/reset
|
|
SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][29]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1
|
|
SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][29]/C
|
|
|
|
Slack: inf
|
|
Source: pll/inst/plle2_adv_inst/LOCKED
|
|
(internal pin)
|
|
Destination: data_memory/memory_data_reg[268435524][6]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 0.985ns (logic 0.045ns (4.570%) route 0.940ns (95.430%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED
|
|
net (fo=2, routed) 0.377 0.377 data_memory/locked
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 0.562 0.985 data_memory/reset
|
|
SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][6]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.867 -0.259 data_memory/clk_out1
|
|
SLICE_X62Y49 FDRE r data_memory/memory_data_reg[268435524][6]/C
|
|
|
|
Slack: inf
|
|
Source: pll/inst/plle2_adv_inst/LOCKED
|
|
(internal pin)
|
|
Destination: data_memory/memory_data_reg[268435478][6]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 1.011ns (logic 0.045ns (4.451%) route 0.966ns (95.549%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED
|
|
net (fo=2, routed) 0.377 0.377 data_memory/locked
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 0.589 1.011 data_memory/reset
|
|
SLICE_X65Y51 FDRE r data_memory/memory_data_reg[268435478][6]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.864 -0.261 data_memory/clk_out1
|
|
SLICE_X65Y51 FDRE r data_memory/memory_data_reg[268435478][6]/C
|
|
|
|
Slack: inf
|
|
Source: pll/inst/plle2_adv_inst/LOCKED
|
|
(internal pin)
|
|
Destination: data_memory/memory_data_reg[268435480][6]/R
|
|
(rising edge-triggered cell FDRE clocked by clk_out1_phase_locked_loop {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 1.011ns (logic 0.045ns (4.451%) route 0.966ns (95.549%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Uncertainty: 0.260ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.203ns
|
|
Phase Error (PE): 0.156ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV 0.000 0.000 f pll/inst/plle2_adv_inst/LOCKED
|
|
net (fo=2, routed) 0.377 0.377 data_memory/locked
|
|
SLICE_X65Y48 LUT2 (Prop_lut2_I1_O) 0.045 0.422 r data_memory/memory_data[268435967][31]_i_1/O
|
|
net (fo=17907, routed) 0.589 1.011 data_memory/reset
|
|
SLICE_X64Y51 FDRE r data_memory/memory_data_reg[268435480][6]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_out1_phase_locked_loop rise edge)
|
|
0.000 0.000 r
|
|
R4 0.000 0.000 r hardware_clk (IN)
|
|
net (fo=0) 0.000 0.000 pll/inst/clk_in1
|
|
R4 IBUF (Prop_ibuf_I_O) 0.457 0.457 r pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.938 pll/inst/clk_in1_phase_locked_loop
|
|
PLLE2_ADV_X1Y0 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.638 -1.700 r pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.546 -1.155 pll/inst/clk_out1_phase_locked_loop
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.126 r pll/inst/clkout1_buf/O
|
|
net (fo=18132, routed) 0.864 -0.261 data_memory/clk_out1
|
|
SLICE_X64Y51 FDRE r data_memory/memory_data_reg[268435480][6]/C
|
|
|
|
|
|
|
|
|
|
|