149 lines
7.3 KiB
Verilog
149 lines
7.3 KiB
Verilog
`timescale 1ns / 1ps
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module DataMemory (
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input clk,
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input reset,
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input [31:0] address,
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input write_enable,
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input [31:0] write_data,
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output [31:0] read_data,
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output [31:0] bcd_hardwire
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);
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parameter integer MEM_SIZE_IN_WORD = 64;
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parameter integer START_ADDRESS = 32'h00000000;
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localparam integer StartAddressInWord = START_ADDRESS / 4;
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reg [31:0] memory_data[MEM_SIZE_IN_WORD + StartAddressInWord - 1 : StartAddressInWord];
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assign bcd_hardwire = memory_data[StartAddressInWord+4];
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assign read_data = memory_data[address[31:2]];
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integer i;
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initial begin
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for (i = StartAddressInWord; i < 24 + StartAddressInWord; i = i + 1) begin
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memory_data[i] <= 32'h00000000;
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end
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for (
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i = 72 + StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1
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) begin
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memory_data[i] <= 32'h00000000;
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end
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memory_data[StartAddressInWord+24] <= 32'h0000002F;
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memory_data[StartAddressInWord+25] <= 32'h000018D0;
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memory_data[StartAddressInWord+26] <= 32'h00003A27;
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memory_data[StartAddressInWord+27] <= 32'h00004786;
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memory_data[StartAddressInWord+28] <= 32'h0000C94D;
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memory_data[StartAddressInWord+29] <= 32'h000064CA;
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memory_data[StartAddressInWord+30] <= 32'h00008027;
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memory_data[StartAddressInWord+31] <= 32'h0000C8C3;
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memory_data[StartAddressInWord+32] <= 32'h0000E08B;
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memory_data[StartAddressInWord+33] <= 32'h00006E15;
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memory_data[StartAddressInWord+34] <= 32'h0000AA22;
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memory_data[StartAddressInWord+35] <= 32'h00002E07;
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memory_data[StartAddressInWord+36] <= 32'h00009F23;
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memory_data[StartAddressInWord+37] <= 32'h00002F2B;
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memory_data[StartAddressInWord+38] <= 32'h00004227;
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memory_data[StartAddressInWord+39] <= 32'h0000022C;
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memory_data[StartAddressInWord+40] <= 32'h00009776;
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memory_data[StartAddressInWord+41] <= 32'h00009477;
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memory_data[StartAddressInWord+42] <= 32'h0000AAF5;
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memory_data[StartAddressInWord+43] <= 32'h000080BE;
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memory_data[StartAddressInWord+44] <= 32'h00002CC7;
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memory_data[StartAddressInWord+45] <= 32'h00009D7D;
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memory_data[StartAddressInWord+46] <= 32'h00000F95;
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memory_data[StartAddressInWord+47] <= 32'h0000E060;
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memory_data[StartAddressInWord+48] <= 32'h00002137;
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memory_data[StartAddressInWord+49] <= 32'h0000A5E5;
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memory_data[StartAddressInWord+50] <= 32'h00001C49;
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memory_data[StartAddressInWord+51] <= 32'h0000C308;
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memory_data[StartAddressInWord+52] <= 32'h00001A04;
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memory_data[StartAddressInWord+53] <= 32'h00005F99;
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memory_data[StartAddressInWord+54] <= 32'h0000124C;
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memory_data[StartAddressInWord+55] <= 32'h0000ABB3;
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memory_data[StartAddressInWord+56] <= 32'h00000E87;
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memory_data[StartAddressInWord+57] <= 32'h00005E55;
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memory_data[StartAddressInWord+58] <= 32'h00002197;
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memory_data[StartAddressInWord+59] <= 32'h00000AA4;
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memory_data[StartAddressInWord+60] <= 32'h0000F7FE;
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memory_data[StartAddressInWord+61] <= 32'h00007F32;
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memory_data[StartAddressInWord+62] <= 32'h0000C5A5;
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memory_data[StartAddressInWord+63] <= 32'h0000D87C;
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memory_data[StartAddressInWord+64] <= 32'h0000E996;
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memory_data[StartAddressInWord+65] <= 32'h00007345;
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memory_data[StartAddressInWord+66] <= 32'h00009213;
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memory_data[StartAddressInWord+67] <= 32'h000076EE;
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memory_data[StartAddressInWord+68] <= 32'h0000260B;
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memory_data[StartAddressInWord+69] <= 32'h0000E0D8;
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memory_data[StartAddressInWord+70] <= 32'h0000D9CA;
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memory_data[StartAddressInWord+71] <= 32'h00003B9F;
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end
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always @(posedge clk) begin
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if (reset) begin
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for (i = StartAddressInWord; i < 24 + StartAddressInWord; i = i + 1) begin
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memory_data[i] <= 32'h00000000;
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end
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for (
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i = 72 + StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1
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) begin
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memory_data[i] <= 32'h00000000;
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end
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memory_data[StartAddressInWord+24] <= 32'h0000002F;
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memory_data[StartAddressInWord+25] <= 32'h000018D0;
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memory_data[StartAddressInWord+26] <= 32'h00003A27;
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memory_data[StartAddressInWord+27] <= 32'h00004786;
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memory_data[StartAddressInWord+28] <= 32'h0000C94D;
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memory_data[StartAddressInWord+29] <= 32'h000064CA;
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memory_data[StartAddressInWord+30] <= 32'h00008027;
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memory_data[StartAddressInWord+31] <= 32'h0000C8C3;
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memory_data[StartAddressInWord+32] <= 32'h0000E08B;
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memory_data[StartAddressInWord+33] <= 32'h00006E15;
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memory_data[StartAddressInWord+34] <= 32'h0000AA22;
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memory_data[StartAddressInWord+35] <= 32'h00002E07;
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memory_data[StartAddressInWord+36] <= 32'h00009F23;
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memory_data[StartAddressInWord+37] <= 32'h00002F2B;
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memory_data[StartAddressInWord+38] <= 32'h00004227;
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memory_data[StartAddressInWord+39] <= 32'h0000022C;
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memory_data[StartAddressInWord+40] <= 32'h00009776;
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memory_data[StartAddressInWord+41] <= 32'h00009477;
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memory_data[StartAddressInWord+42] <= 32'h0000AAF5;
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memory_data[StartAddressInWord+43] <= 32'h000080BE;
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memory_data[StartAddressInWord+44] <= 32'h00002CC7;
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memory_data[StartAddressInWord+45] <= 32'h00009D7D;
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memory_data[StartAddressInWord+46] <= 32'h00000F95;
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memory_data[StartAddressInWord+47] <= 32'h0000E060;
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memory_data[StartAddressInWord+48] <= 32'h00002137;
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memory_data[StartAddressInWord+49] <= 32'h0000A5E5;
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memory_data[StartAddressInWord+50] <= 32'h00001C49;
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memory_data[StartAddressInWord+51] <= 32'h0000C308;
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memory_data[StartAddressInWord+52] <= 32'h00001A04;
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memory_data[StartAddressInWord+53] <= 32'h00005F99;
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memory_data[StartAddressInWord+54] <= 32'h0000124C;
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memory_data[StartAddressInWord+55] <= 32'h0000ABB3;
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memory_data[StartAddressInWord+56] <= 32'h00000E87;
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memory_data[StartAddressInWord+57] <= 32'h00005E55;
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memory_data[StartAddressInWord+58] <= 32'h00002197;
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memory_data[StartAddressInWord+59] <= 32'h00000AA4;
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memory_data[StartAddressInWord+60] <= 32'h0000F7FE;
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memory_data[StartAddressInWord+61] <= 32'h00007F32;
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memory_data[StartAddressInWord+62] <= 32'h0000C5A5;
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memory_data[StartAddressInWord+63] <= 32'h0000D87C;
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memory_data[StartAddressInWord+64] <= 32'h0000E996;
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memory_data[StartAddressInWord+65] <= 32'h00007345;
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memory_data[StartAddressInWord+66] <= 32'h00009213;
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memory_data[StartAddressInWord+67] <= 32'h000076EE;
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memory_data[StartAddressInWord+68] <= 32'h0000260B;
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memory_data[StartAddressInWord+69] <= 32'h0000E0D8;
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memory_data[StartAddressInWord+70] <= 32'h0000D9CA;
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memory_data[StartAddressInWord+71] <= 32'h00003B9F;
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end else begin
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if (write_enable) begin
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memory_data[address[31:2]] <= write_data;
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end
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end
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end
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endmodule
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