237 lines
7.8 KiB
Verilog
237 lines
7.8 KiB
Verilog
`timescale 1ns / 1ps
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module CPU (
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input hardware_clk,
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input reset,
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output [11:0] bcd_control
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);
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// first, we split the clock
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wire clk;
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phase_locked_loop pll (
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.clk_in1 (hardware_clk),
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.clk_out1(clk)
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);
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// Out of IF
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wire IF_fetched_instruction;
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wire IF_PC_plus_4;
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// Out of ID
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wire [1:0] ID_PC_jump;
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wire [31:0] ID_branch_target;
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wire [31:0] ID_jump_target;
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wire [31:0] ID_jump_register_target;
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wire ID_is_branch;
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wire ID_is_loadword;
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wire ID_register_write;
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wire ID_WB_source;
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wire ID_memory_write;
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wire [4:0] ID_ALU_funtion;
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wire ID_ALU_source1;
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wire ID_ALU_source2;
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wire ID_register_write_desination_source;
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wire [31:0] ID_PC_plus_4;
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wire [31:0] ID_register_file_read_A;
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wire [31:0] ID_register_file_read_B;
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wire [4:0] ID_shamt;
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wire [31:0] ID_extended_immediate;
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wire [4:0] ID_rs_address;
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wire [4:0] ID_rt_address;
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wire [4:0] ID_rd_address;
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// Out of EX
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wire EX_PC_branch;
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wire [31:0] EX_branch_target;
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wire EX_register_write;
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wire EX_WB_source;
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wire EX_memory_write;
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wire [31:0] EX_ALU_result;
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wire [31:0] EX_memory_write_data;
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wire [4:0] EX_register_write_destination;
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wire [4:0] EX_rs_address;
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wire [4:0] EX_rt_address;
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// Out of MEM
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wire [4:0] MEM_rt_address;
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wire MEM_register_write;
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wire MEM_WB_source;
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wire [31:0] MEM_memory_read_data;
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wire [31:0] MEM_ALU_result;
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wire [4:0] MEM_register_write_destination;
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wire MEM_data_memory_write;
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wire [31:0] MEM_data_memory_address;
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wire [31:0] MEM_data_memory_write_data;
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// Out of WB
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wire WB_register_write;
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wire [31:0] WB_register_write_data;
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wire [4:0] WB_register_write_address;
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// Out of hazard control
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wire [1:0] hazard_IFID_source;
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wire hazard_IDEX_source;
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wire hazard_IF_need_stall;
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// Out of EXforward
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wire [1:0] EXforward_IDA_source;
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wire [1:0] EXforward_IDB_source;
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// Out of mem forward
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wire MEMforward_MEM_write_data_source;
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// Out of data memory
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wire [31:0] datamemory_read_data;
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wire [31:0] bcd_hardwire_control;
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assign bcd_control = bcd_hardwire_control[11:0];
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InstFetch instruction_fetch (
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.clk(clk),
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.branch_target(EX_branch_target),
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.jump_target(ID_jump_target),
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.jump_register_target(ID_jump_register_target),
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.PC_jump(ID_PC_jump),
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.PC_branch(EX_PC_branch),
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.need_stall(hazard_IF_need_stall),
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.fetched_instruction(IF_fetched_instruction),
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.PC_plus_4(IF_PC_plus_4),
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);
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InstDecode instruction_decode (
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.clk(clk),
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.prev_fetched_instruction(IF_fetched_instruction),
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.prev_PC_plus_4(IF_PC_plus_4),
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.IFIDSrc(hazard_IFID_source),
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.WB_write_enable(WB_write_enable),
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.WB_write_address(WB_write_address),
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.WB_write_data(WB_write_data),
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.PC_jump(ID_PC_jump),
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.jump_target(ID_jump_target),
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.jump_register_target(ID_jump_register_target),
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.is_loadword(ID_is_loadword),
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.is_branch(ID_is_branch),
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.WB_source(ID_WB_source),
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.memory_write(ID_memory_write),
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.ALU_function(ID_ALU_funtion),
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.ALU_source1(ID_ALU_source1),
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.ALU_source2(ID_ALU_source2),
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.register_write_destination_source(ID_register_write_desination_source),
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.register_write(ID_register_write),
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.PC_plus_4(ID_PC_plus_4),
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.register_file_read_A(ID_register_file_read_A),
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.register_file_read_B(ID_register_file_read_B),
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.shamt(ID_shamt),
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.extended_immediate(ID_extended_immediate),
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.rs_address(ID_rs_address),
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.rt_address(ID_rt_address),
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.rd_address(ID_rd_address)
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);
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Execution execution (
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.clk(clk),
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.prev_is_branch(ID_is_branch),
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.prev_WB_source(ID_WB_source),
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.prev_memory_write(ID_memory_write),
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.prev_ALU_function(ID_ALU_funtion),
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.prev_ALU_source1(ID_ALU_source1),
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.prev_ALU_source2(ID_ALU_source2),
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.prev_register_write_destination_source(ID_register_write_desination_source),
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.prev_register_write(ID_register_write),
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.prev_PC_plus_4(ID_PC_plus_4),
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.prev_register_file_read_A(ID_register_file_read_A),
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.prev_register_file_read_B(ID_register_file_read_B),
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.prev_shamt(ID_shamt),
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.prev_extended_immediate(ID_extended_immediate),
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.prev_rs_address(ID_rs_address),
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.prev_rt_address(ID_rt_address),
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.prev_rd_address(ID_rd_address),
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.IDEXSrc(hazard_IDEX_source),
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.operandASrc(EXforward_IDA_source),
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.operandBSrc(EXforward_IDB_source),
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.MEM_forwarded_data(MEM_ALU_result),
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.WB_forwarded_data(WB_register_write_data),
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.PC_branch(EX_PC_branch),
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.branch_target(EX_branch_target),
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.register_write(EX_register_write),
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.WB_source(EX_WB_source),
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.memory_write(EX_memory_write),
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.ALU_result(EX_ALU_result),
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.memory_write_data(EX_memory_write_data),
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.register_write_destination(EX_register_write_destination),
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.rs_address(EX_rs_address),
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.rt_address(EX_rt_address)
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);
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MemoryAccess memory_access (
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.clk(clk),
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.prev_register_write(EX_register_write),
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.prev_WB_source(EX_WB_source),
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.prev_memory_write(EX_memory_write),
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.prev_ALU_result(EX_ALU_result),
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.prev_memory_write_data(EX_memory_write_data),
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.prev_register_write_destination(EX_register_write_destination),
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.prev_rt_address(EX_rt_address),
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.MEM_write_data_source(MEMforward_MEM_write_data_source),
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.WB_forwarded_data(WB_register_write_data),
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.rt_address(MEM_rt_address),
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.register_write(MEM_register_write),
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.WB_source(MEM_WB_source),
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.memory_read_data(MEM_memory_read_data),
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.ALU_result(MEM_ALU_result),
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.register_write_destination(MEM_register_write_destination),
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.data_memory_write(MEM_data_memory_write),
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.data_memory_address(MEM_data_memory_address),
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.data_memory_write_data(MEM_data_memory_write_data),
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.data_memory_read_data(datamemory_read_data)
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);
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WriteBack write_back (
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.clk(clk),
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.prev_register_write(MEM_register_write),
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.prev_WB_source(MEM_WB_source),
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.prev_memory_read_data(MEM_memory_read_data),
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.prev_ALU_result(MEM_ALU_result),
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.prev_register_write_destination(MEM_register_write_destination),
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.register_write(WB_register_write),
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.register_write_data(WB_register_write_data),
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.register_write_addr(WB_register_write_address),
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);
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DataMemory data_memory (
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.clk(clk),
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.address(MEM_data_memory_address),
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.write_enable(MEM_data_memory_write),
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.write_data(MEM_data_memory_write_data),
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.read_data(datamemory_read_data),
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.bcd_hardwire(bcd_hardwire_control)
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);
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ExecutionForward execution_forward (
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.EX_rs_address(EX_rs_address),
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.EX_rt_address(EX_rt_address),
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.MEM_register_write(MEM_register_write),
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.MEM_register_write_address(MEM_register_write_address),
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.WB_register_write(WB_register_write),
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.WB_register_write_address(WB_register_write_address),
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.IDA_source(EXforward_IDA_source),
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.IDB_source(EXforward_IDB_source)
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);
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MemoryForward memory_forward (
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.WB_register_write(WB_register_write),
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.WB_register_write_address(WB_register_write_address),
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.MEM_rt_address(MEM_rt_address),
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.MEM_write_data_source(MEMforward_MEM_write_data_source),
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);
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HazardUnit hazard_unit (
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.PC_jump(ID_PC_jump),
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.is_loadword(ID_is_loadword),
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.PC_branch(EX_PC_branch),
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.IFID_source(hazard_IFID_source),
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.IDEX_source(hazard_IDEX_source),
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.IF_need_stall(hazard_IF_need_stall)
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);
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endmodule
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