77 lines
3.4 KiB
Verilog
77 lines
3.4 KiB
Verilog
`timescale 1ns / 1ps
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module ControlUnit (
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input [5:0] opcode,
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input [5:0] funct,
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output [1:0] PC_jump,
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output is_branch,
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output is_loadword,
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output write_ra,
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output ra_addr_source,
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output WB_source,
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output memory_write,
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output [4:0] ALU_function,
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output ALU_source1,
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output ALU_source2,
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output register_write,
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output register_write_destination_source,
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output [1:0] extendop
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);
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assign PC_jump = (opcode == 6'h2 || opcode == 6'h3) ? 2'b01:
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(opcode == 6'h0 && (funct == 6'h8 || funct == 6'h9)) ? 2'b10 : 2'b00;
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assign is_branch = (opcode == 6'h4 || opcode == 6'h5 || opcode == 6'h6 ||
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opcode == 6'h7 || opcode == 6'h1) ? 1 : 0;
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assign is_loadword = (opcode == 6'h23) ? 1 : 0;
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assign write_ra = (opcode == 6'h3) ? 1 : (opcode == 6'h0 && funct == 6'h9) ? 1 : 0;
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assign ra_addr_source = (opcode == 6'h0 && funct == 6'h9) ? 1 : 0;
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assign register_write = (opcode == 6'h2b || opcode == 6'h4 || opcode == 6'h5 ||
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opcode == 6'h6 || opcode == 6'h7 || opcode == 6'h1 ||
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opcode == 6'h1 || opcode == 6'h2 || opcode == 6'h3 ||
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(opcode == 6'h0 && (funct == 6'h8 || funct == 6'h9))) ? 0 : 1;
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assign WB_source = (opcode == 6'h23) ? 1 : 0;
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assign memory_write = (opcode == 6'h2b) ? 1 : 0;
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assign ALU_function = (opcode == 6'h0 && funct == 6'h24) ? 5'b00000:
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(opcode == 6'h0 && funct == 6'h25) ? 5'b00001:
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(opcode == 6'h0 && (funct == 6'h22 || funct == 6'h23)) ? 5'b00110:
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(opcode == 6'ha || (opcode == 6'h0 && funct == 6'h2a)) ? 5'b00111:
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(opcode == 6'hb || (opcode == 6'h0 && funct == 56'h2b)) ? 5'b01000:
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(opcode == 6'h0 && funct == 6'h27) ? 5'b01100:
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(opcode == 6'h0 && funct == 6'h26) ? 5'b01101:
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(opcode == 6'h0 && funct == 6'h0) ? 5'b10000:
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(opcode == 6'h4) ? 5'b10001:
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(opcode == 6'h5) ? 5'b10010:
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(opcode == 6'h7) ? 5'b10011:
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(opcode == 6'h1) ? 5'b10100:
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(opcode == 6'h6) ? 5'b10101:
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(opcode == 6'h0 && funct == 6'h2) ? 5'b11000:
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(opcode == 6'h0 && funct == 6'h3) ? 5'b11001:
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(opcode == 6'h0 && funct == 6'h18) ? 5'b11010:
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5'b00010;
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assign ALU_source1 = (opcode == 6'h0 &&
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(funct == 6'h0 || funct == 6'h2 || funct == 6'h3)) ? 1 : 0;
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assign ALU_source2 = (opcode == 6'h23 || opcode == 6'h2b || opcode == 6'hf ||
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opcode == 6'h8 || opcode == 6'h9 || opcode == 6'hc || opcode == 6'ha ||
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opcode == 6'hb) ? 1 : 0;
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assign register_write_destination_source = (opcode == 6'h23 || opcode == 6'h8 ||
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opcode == 6'h9 || opcode == 6'hc ||
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opcode == 6'ha || opcode == 6'hb ||
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(opcode == 6'h0 &&
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(funct == 6'h0 || funct == 6'h2 ||
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funct == 6'h3))) ? 0 : 1;
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assign extendop = (opcode == 6'hf) ? 2'b10:
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(opcode == 6'hc) ? 2'b01:2'b00;
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endmodule
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