39 lines
1.2 KiB
Verilog
39 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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module ExecutionForward (
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input [4:0] EX_rs_address,
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input [4:0] EX_rt_address,
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input MEM_register_write,
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input [4:0] MEM_register_write_address,
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input WB_register_write,
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input [4:0] WB_register_write_address,
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output [1:0] IDA_source,
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output [1:0] IDB_source
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);
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always @(*) begin
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if (MEM_register_write == 1'b1 && MEM_register_write_address == EX_rs_address &&
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EX_rs_address != 5'b00000) begin
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IDA_source = 2'b00;
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end else begin
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if (WB_register_write == 1'b1 && WB_register_write_address == EX_rs_address &&
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EX_rs_address != 5'b00000) begin
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IDA_source = 2'b10;
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end else begin
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IDA_source = 2'b00;
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end
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end
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if (MEM_register_write == 1'b1 && MEM_register_write_address == EX_rt_address &&
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EX_rt_address != 5'b00000) begin
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IDB_source = 2'b00;
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end else begin
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if (WB_register_write == 1'b1 && WB_register_write_address == EX_rt_address &&
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EX_rt_address != 5'b00000) begin
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IDB_source = 2'b10;
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end else begin
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IDB_source = 2'b00;
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end
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end
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end
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endmodule
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