26 lines
1.1 KiB
Verilog
26 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
|
|
|
|
module InstructionMemory (
|
|
input [31:0] address,
|
|
output reg [31:0] instruction
|
|
);
|
|
|
|
always @(*) begin
|
|
case (address[31:2])
|
|
20'd0: instruction <= 32'h3c1000ca; // lui $s0, 0xca
|
|
20'd6: instruction <= 32'h221000fe; // addi $s0, $s0, 0xfe
|
|
20'd11: instruction <= 32'h2011ffdf; // addi $s1, $zero, -0x21
|
|
20'd16: instruction <= 32'h00109100; // sll $s2, $s0, 4
|
|
20'd21: instruction <= 32'h00109082; // srl $s2, $s0, 2
|
|
20'd26: instruction <= 32'h00119043; // sra $s2, $s1, 1
|
|
20'd31: instruction <= 32'h0230902a; // slt $s2, $s1, $s0
|
|
20'd36: instruction <= 32'h0211902a; // slt $s2, $s0, $s1
|
|
20'd41: instruction <= 32'h0230882b; // sltu $s1, $s1, $s0
|
|
20'd46: instruction <= 32'h2a120004; // slti $s2, $s0, 0x4
|
|
20'd51: instruction <= 32'h2e12fffc; // sltiu $s2, $s0, -0x4
|
|
default: instruction <= 32'h00000000;
|
|
endcase
|
|
end
|
|
|
|
endmodule
|