25 lines
1.1 KiB
Verilog
25 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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module InstructionMemory (
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input [31:0] address,
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output reg [31:0] instruction
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);
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always @(*) begin
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case (address[31:2])
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20'd0: instruction <= 32'h20110001; // addi $s1, $zero, 1
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20'd6: instruction <= 32'h20120001; // addi $s2, $zero, 1
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20'd11: instruction <= 32'h12320009; // beq $s1, $s2, beq_target
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20'd16: instruction <= 32'h20130001; // addi $s3, $zero, 1
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// beq_target:
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20'd21: instruction <= 32'h22310001; // addi $s1, $s1, 1
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20'd26: instruction <= 32'h12320009; // beq $s1, $s2, beq_target2
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20'd31: instruction <= 32'h20130003; // addi $s3, $zero, 3
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// beq_target2:
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20'd36: instruction <= 32'h08100023; // j beq_target2
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default: instruction <= 32'h00000000;
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endcase
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end
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endmodule
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