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MipsPipelineProcessor/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt

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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Sat Jul 13 23:40:17 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file CPU_control_sets_placed.rpt
| Design : CPU
| Device : xc7a35t
---------------------------------------------------------------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Total control sets | 547 |
| Minimum number of control sets | 547 |
| Addition due to synthesis replication | 0 |
| Addition due to physical synthesis replication | 0 |
| Unused register locations in slices containing registers | 12 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions
2. Histogram
------------
+--------------------+-------+
| Fanout | Count |
+--------------------+-------+
| Total control sets | 547 |
| >= 0 to < 4 | 0 |
| >= 4 to < 6 | 0 |
| >= 6 to < 8 | 0 |
| >= 8 to < 10 | 0 |
| >= 10 to < 12 | 0 |
| >= 12 to < 14 | 0 |
| >= 14 to < 16 | 0 |
| >= 16 | 547 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 0 | 0 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 712 | 202 |
| Yes | No | No | 0 | 0 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 17420 | 6840 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+--------------------+------------------------------------------------------------+------------------------------+------------------+----------------+--------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
+--------------------+------------------------------------------------------------+------------------------------+------------------+----------------+--------------+
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_20[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_3[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_4[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | instruction_decode/register_file/p_0_in | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[10][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[24][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[2][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[12][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[30][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[21][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[25][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[31][31]_i_1_n_0 | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[23][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[29][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[13][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[26][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[4][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[8][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[11][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[16][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[19][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[17][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[5][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[28][31]_i_1_n_0 | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[27][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[3][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[9][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[14][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[18][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[22][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | instruction_decode/register_file/registers[7][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | execution/alu/E[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_5[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_24[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_27[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_52[0] | data_memory/reset | 17 | 32 | 1.88 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_43[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_3[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_9[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_37[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_4[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_23[0] | data_memory/reset | 17 | 32 | 1.88 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_2[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_25[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_38[0] | data_memory/reset | 18 | 32 | 1.78 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_39[0] | data_memory/reset | 18 | 32 | 1.78 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_42[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_45[0] | data_memory/reset | 18 | 32 | 1.78 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_1[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_8[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_7[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_22[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_3[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_34[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_46[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_48[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_9[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_50[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_36[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_35[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_0[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_7[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_8[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_28[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_29[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_30[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_40[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_58[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_6[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_5[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_31[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_19[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_49[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_4[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_26[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_44[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_47[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_6[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_51[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_2[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_32[0] | data_memory/reset | 18 | 32 | 1.78 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_33[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_41[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_1[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_12[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_13[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_4[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_11[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_1[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_11[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_14[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_0[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_19[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_20[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_26[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_6[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_12[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_10[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_18[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_21[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_15[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_22[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_8[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_13[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_9[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_2[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_7[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_10[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_16[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_17[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_23[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_24[0] | data_memory/reset | 17 | 32 | 1.88 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_28[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_30[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_30[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_31[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_27[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_32[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_2[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_33[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_25[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_29[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_5[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_3[0] | data_memory/reset | 17 | 32 | 1.88 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_0[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_0[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_57[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_4[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_33[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_35[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_19[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_42[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_44[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_27[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_6[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_56[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_3[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_52[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_34[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_21[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_27[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_30[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_7[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_23[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_10[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_35[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_29[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_36[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_22[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_37[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_13[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_38[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_39[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_25[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_31[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_46[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_14[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_47[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_15[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_20[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_48[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_54[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_11[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_40[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_5[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_24[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_32[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_5[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_53[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_55[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_36[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_16[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_17[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_4[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_45[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_41[0] | data_memory/reset | 8 | 32 | 4.00 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_49[0] | data_memory/reset | 8 | 32 | 4.00 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_50[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_2[0] | data_memory/reset | 8 | 32 | 4.00 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_34[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_28[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_43[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_51[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_63[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_9[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_8[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_60[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_7[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_62[0] | data_memory/reset | 18 | 32 | 1.78 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_6[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_59[0] | data_memory/reset | 17 | 32 | 1.88 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_61[0] | data_memory/reset | 18 | 32 | 1.78 |
| pll/inst/clk_out1 | write_back/E[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[1]_3[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[3]_1[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_13[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_24[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_5[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_4[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_5[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_7[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_11[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_16[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_40[0] | data_memory/reset | 17 | 32 | 1.88 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_5[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_30[0] | data_memory/reset | 17 | 32 | 1.88 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_6[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_6[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_11[0] | data_memory/reset | 18 | 32 | 1.78 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_23[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_12[0] | data_memory/reset | 17 | 32 | 1.88 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_32[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_3[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_41[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_7[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_2[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_3[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_2[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_15[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_12[0] | data_memory/reset | 8 | 32 | 4.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_29[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_11[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_13[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_14[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_15[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_26[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_16[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_8[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_14[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_20[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_9[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_13[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_9[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_0[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_10[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_17[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_7[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_0[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_25[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_6[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_10[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_31[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_17[0] | data_memory/reset | 8 | 32 | 4.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_9[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_22[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_27[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_28[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_4[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_8[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_1[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_10[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_12[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/E[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_0[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_1[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_1[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_26[0] | data_memory/reset | 17 | 32 | 1.88 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_4[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_19[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_1[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_21[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_2[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_2[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_2[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_4[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_0[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_2[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_0[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_2[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_0[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_11[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_0[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_1[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_4[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_0[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_4[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_3[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_12[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_6[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_14[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_0[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_17[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_18[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__9_1[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_2[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_5[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_3[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_2[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_1[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_10[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__14_1[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_2[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__17_1[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_5[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_2[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_2[0] | data_memory/reset | 17 | 32 | 1.88 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_3[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__26_1[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_13[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_16[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_0[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_3[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_3[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_15[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_2[0] | data_memory/reset | 7 | 32 | 4.57 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_22[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_5[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_1[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_3[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_2[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_1[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_1[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_2[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_0[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_0[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_20[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_2[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_23[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_24[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_25[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__27_1[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_2[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__30_1[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_4[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_2[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_4[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_1[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__29_1[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__30_2[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_28[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_9[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_3[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_3[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_0[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_4[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_3[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_1[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_27[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_2[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_3[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_2[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_2[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_4[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_5[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_1[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_3[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_3[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_1[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_3[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_2[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_2[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_4[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_0[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_5[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_1[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_8[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_7[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_2[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_3[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_4[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_2[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_0[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_2[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_3[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_1[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_1[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_4[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_1[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_6[0] | data_memory/reset | 18 | 32 | 1.78 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_3[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_5[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_2[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_2[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_5[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_1[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_1[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_2[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_5[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_3[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_3[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_3[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_1[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_1[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_1[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_2[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_19[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_23[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_1[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_0[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_11[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_5[0] | data_memory/reset | 18 | 32 | 1.78 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_20[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_12[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_10[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_26[0] | data_memory/reset | 18 | 32 | 1.78 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_9[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_4[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_7[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_2[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_1[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_10[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_30[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_2[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_13[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_8[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_25[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_18[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_15[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_24[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_0[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_11[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_3[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_9[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_27[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_6[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_0[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_11[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_12[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_13[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_14[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_14[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_17[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_19[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_22[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_29[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_0[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_16[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_28[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_6[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_12[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_31[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_3[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_4[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_5[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_1[0] | data_memory/reset | 19 | 32 | 1.68 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_10[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_15[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_16[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_17[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_18[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_2[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_1[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_13[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_20[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_7[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_8[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_21[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_14[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_7[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_14[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_17[0] | data_memory/reset | 18 | 32 | 1.78 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_19[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_23[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_29[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_3[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_25[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_32[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_22[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_34[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_20[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_9[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_25[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_27[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_30[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_4[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_21[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_5[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_7[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_28[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_8[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_0[0] | data_memory/reset | 18 | 32 | 1.78 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_38[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_35[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_3[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_23[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_1[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_18[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_5[0] | data_memory/reset | 10 | 32 | 3.20 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_11[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_24[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_37[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_6[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_22[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_8[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_11[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_10[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_12[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_36[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_33[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_13[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_15[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_14[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_13[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_2[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_16[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_17[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_1[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_19[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_18[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_2[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_6[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_20[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_9[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_31[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_24[0] | data_memory/reset | 16 | 32 | 2.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_4[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_12[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_15[0] | data_memory/reset | 8 | 32 | 4.00 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_10[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_16[0] | data_memory/reset | 9 | 32 | 3.56 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_21[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_32[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_33[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_35[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_24[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_31[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_36[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_37[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_25[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_26[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_29[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_34[0] | data_memory/reset | 14 | 32 | 2.29 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_21[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_23[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_28[0] | data_memory/reset | 11 | 32 | 2.91 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_22[0] | data_memory/reset | 13 | 32 | 2.46 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_38[0] | data_memory/reset | 15 | 32 | 2.13 |
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_39[0] | data_memory/reset | 12 | 32 | 2.67 |
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_3[0] | data_memory/reset | 15 | 44 | 2.93 |
| pll/inst/clk_out1 | | execution/alu/IFID_PC_plus_4 | 20 | 67 | 3.35 |
| pll/inst/clk_out1 | | execution/alu/SR[0] | 41 | 160 | 3.90 |
| pll/inst/clk_out1 | | data_memory/reset | 141 | 485 | 3.44 |
+--------------------+------------------------------------------------------------+------------------------------+------------------+----------------+--------------+
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