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MipsPipelineProcessor/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt

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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Sat Jul 13 23:40:17 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb
| Design : CPU
| Device : xc7a35tfgg484-1
| Speed File : -1
| Design State : Fully Placed
---------------------------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs | 8344 | 0 | 0 | 20800 | 40.12 |
| LUT as Logic | 8344 | 0 | 0 | 20800 | 40.12 |
| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 18132 | 0 | 0 | 41600 | 43.59 |
| Register as Flip Flop | 18132 | 0 | 0 | 41600 | 43.59 |
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 2377 | 0 | 0 | 16300 | 14.58 |
| F8 Muxes | 1088 | 0 | 0 | 8150 | 13.35 |
+-------------------------+-------+-------+------------+-----------+-------+
* Warning! LUT value is adjusted to account for LUT combining.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 368 | Yes | Set | - |
| 17764 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+--------------------------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+-------+-------+------------+-----------+-------+
| Slice | 7058 | 0 | 0 | 8150 | 86.60 |
| SLICEL | 4944 | 0 | | | |
| SLICEM | 2114 | 0 | | | |
| LUT as Logic | 8344 | 0 | 0 | 20800 | 40.12 |
| using O5 output only | 0 | | | | |
| using O6 output only | 8043 | | | | |
| using O5 and O6 | 301 | | | | |
| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 0 | 0 | | | |
| Slice Registers | 18132 | 0 | 0 | 41600 | 43.59 |
| Register driven from within the Slice | 1461 | | | | |
| Register driven from outside the Slice | 16671 | | | | |
| LUT in front of the register is unused | 14188 | | | | |
| LUT in front of the register is used | 2483 | | | | |
| Unique Control Sets | 547 | | 0 | 8150 | 6.71 |
+--------------------------------------------+-------+-------+------------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 50 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 100 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| DSPs | 3 | 0 | 0 | 90 | 3.33 |
| DSP48E1 only | 3 | | | | |
+----------------+------+-------+------------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 15 | 15 | 0 | 250 | 6.00 |
| IOB Master Pads | 6 | | | | |
| IOB Slave Pads | 9 | | | | |
| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 240 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 250 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 250 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
| BUFIO | 0 | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 1 | 0 | 0 | 5 | 20.00 |
| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 0 | 20 | 0.00 |
+------------+------+-------+------------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+-----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+-----------+-------+---------------------+
| FDRE | 17764 | Flop & Latch |
| LUT6 | 7154 | LUT |
| MUXF7 | 2377 | MuxFx |
| MUXF8 | 1088 | MuxFx |
| LUT5 | 825 | LUT |
| FDSE | 368 | Flop & Latch |
| LUT4 | 281 | LUT |
| LUT3 | 230 | LUT |
| LUT2 | 154 | LUT |
| CARRY4 | 39 | CarryLogic |
| OBUF | 13 | IO |
| DSP48E1 | 3 | Block Arithmetic |
| IBUF | 2 | IO |
| BUFG | 2 | Clock |
| PLLE2_ADV | 1 | Clock |
| LUT1 | 1 | LUT |
+-----------+-------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+-------------------+------+
| Ref Name | Used |
+-------------------+------+
| phase_locked_loop | 1 |
+-------------------+------+
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