190 lines
8.3 KiB
Plaintext
190 lines
8.3 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
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| Date : Sat Jul 13 23:39:08 2024
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| Host : Viviana running 64-bit major release (build 9200)
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| Command : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb
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| Design : CPU
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| Device : xc7a35tfgg484-1
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| Speed File : -1
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| Design State : Synthesized
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Memory
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3. DSP
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4. IO and GT Specific
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5. Clocking
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6. Specific Feature
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7. Primitives
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8. Black Boxes
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9. Instantiated Netlists
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1. Slice Logic
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--------------
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+-------------------------+-------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-------------------------+-------+-------+------------+-----------+-------+
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| Slice LUTs* | 8384 | 0 | 0 | 20800 | 40.31 |
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| LUT as Logic | 8384 | 0 | 0 | 20800 | 40.31 |
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| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 |
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| Slice Registers | 18120 | 0 | 0 | 41600 | 43.56 |
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| Register as Flip Flop | 18120 | 0 | 0 | 41600 | 43.56 |
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| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
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| F7 Muxes | 2377 | 0 | 0 | 16300 | 14.58 |
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| F8 Muxes | 1088 | 0 | 0 | 8150 | 13.35 |
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+-------------------------+-------+-------+------------+-----------+-------+
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* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
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Warning! LUT value is adjusted to account for LUT combining.
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 0 | Yes | - | Set |
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| 0 | Yes | - | Reset |
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| 368 | Yes | Set | - |
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| 17752 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. Memory
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---------
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+----------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+----------------+------+-------+------------+-----------+-------+
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| Block RAM Tile | 0 | 0 | 0 | 50 | 0.00 |
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| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 |
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| RAMB18 | 0 | 0 | 0 | 100 | 0.00 |
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+----------------+------+-------+------------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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3. DSP
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------
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+----------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+----------------+------+-------+------------+-----------+-------+
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| DSPs | 3 | 0 | 0 | 90 | 3.33 |
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| DSP48E1 only | 3 | | | | |
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+----------------+------+-------+------------+-----------+-------+
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4. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-----------------------------+------+-------+------------+-----------+-------+
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| Bonded IOB | 14 | 0 | 0 | 250 | 5.60 |
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| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
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| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
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| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 |
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| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 |
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| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 |
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| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 |
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| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 |
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| IBUFDS | 0 | 0 | 0 | 240 | 0.00 |
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| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
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| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 |
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| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 |
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| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
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| ILOGIC | 0 | 0 | 0 | 250 | 0.00 |
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| OLOGIC | 0 | 0 | 0 | 250 | 0.00 |
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+-----------------------------+------+-------+------------+-----------+-------+
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5. Clocking
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-----------
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+------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+------------+------+-------+------------+-----------+-------+
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| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
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| BUFIO | 0 | 0 | 0 | 20 | 0.00 |
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| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 |
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| PLLE2_ADV | 0 | 0 | 0 | 5 | 0.00 |
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| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 |
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| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
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| BUFR | 0 | 0 | 0 | 20 | 0.00 |
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+------------+------+-------+------------+-----------+-------+
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6. Specific Feature
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-------------------
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+-------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-------------+------+-------+------------+-----------+-------+
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| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
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| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
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| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
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| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
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| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
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| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
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| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
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| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
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| XADC | 0 | 0 | 0 | 1 | 0.00 |
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+-------------+------+-------+------------+-----------+-------+
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7. Primitives
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-------------
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+----------+-------+---------------------+
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| Ref Name | Used | Functional Category |
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+----------+-------+---------------------+
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| FDRE | 17752 | Flop & Latch |
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| LUT6 | 7154 | LUT |
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| MUXF7 | 2377 | MuxFx |
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| MUXF8 | 1088 | MuxFx |
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| LUT5 | 825 | LUT |
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| FDSE | 368 | Flop & Latch |
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| LUT4 | 281 | LUT |
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| LUT3 | 230 | LUT |
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| LUT2 | 154 | LUT |
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| CARRY4 | 39 | CarryLogic |
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| LUT1 | 15 | LUT |
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| OBUF | 13 | IO |
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| DSP48E1 | 3 | Block Arithmetic |
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| IBUF | 1 | IO |
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+----------+-------+---------------------+
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8. Black Boxes
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--------------
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+-------------------+------+
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| Ref Name | Used |
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+-------------------+------+
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| phase_locked_loop | 1 |
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+-------------------+------+
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9. Instantiated Netlists
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------------------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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