From aa64c19c8bbcb6526eca97f653b16eeeeb1685b4 Mon Sep 17 00:00:00 2001
From: unlockable <g@unlockableworld.com>
Date: Wed, 10 Jul 2024 23:56:40 +0800
Subject: [PATCH] Test neq

---
 05test_neq.asm             | 35 +++++++++++++++++++++++++++++++++++
 05test_neq_mars.txt        |  7 +++++++
 create_verilog_from_asm.py |  5 +++++
 3 files changed, 47 insertions(+)
 create mode 100644 05test_neq.asm
 create mode 100644 05test_neq_mars.txt
 create mode 100644 create_verilog_from_asm.py

diff --git a/05test_neq.asm b/05test_neq.asm
new file mode 100644
index 0000000..fda07bd
--- /dev/null
+++ b/05test_neq.asm
@@ -0,0 +1,35 @@
+    addi    $s1,            $zero,  1
+    nop     
+    nop     
+    nop     
+    nop     
+    bne     $s1,            $s2,    bne_target
+    nop     
+    nop     
+    nop     
+    nop     
+    addi    $s3,            $zero,  1
+    nop     
+    nop     
+    nop     
+    nop     
+
+bne_target:
+    addi    $s2,            $zero,  1
+    nop     
+    nop     
+    nop     
+    nop     
+    bne     $s1,            $s2,    bne_target2
+    nop     
+    nop     
+    nop     
+    nop     
+    addi    $s3,            $zero,  2
+    nop
+    nop
+    nop
+    nop
+
+bne_target2:
+    j       bne_target2
\ No newline at end of file
diff --git a/05test_neq_mars.txt b/05test_neq_mars.txt
new file mode 100644
index 0000000..a5bd9e0
--- /dev/null
+++ b/05test_neq_mars.txt
@@ -0,0 +1,7 @@
+20110001
+16320009
+20130001
+20120001
+16320009
+20130002
+0810001e
diff --git a/create_verilog_from_asm.py b/create_verilog_from_asm.py
new file mode 100644
index 0000000..e65b294
--- /dev/null
+++ b/create_verilog_from_asm.py
@@ -0,0 +1,5 @@
+file_name = input("File name: ")
+with open(file_name) as fl:
+    file_content = fl.readlines()
+for idx, inst in enumerate(file_content):
+    print("20'd%d: instruction <= 32'h%s;" % (idx, inst.strip()))
\ No newline at end of file