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This commit is contained in:
un-lock-able
2024-07-15 22:42:43 +08:00
parent f00725e8f3
commit 68b375f9b4
66 changed files with 2581 additions and 2305 deletions
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PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp
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10
PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v
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@@ -2,10 +2,10 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
// Date : Thu Jul 11 13:35:55 2024
// Date : Thu Jul 11 13:35:54 2024
// Host : Viviana running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top phase_locked_loop -prefix
// phase_locked_loop_ phase_locked_loop_sim_netlist.v
// Design : phase_locked_loop
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -29,14 +29,14 @@ module phase_locked_loop
wire locked;
wire reset;
phase_locked_loop_clk_wiz inst
phase_locked_loop_phase_locked_loop_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.reset(reset));
endmodule
module phase_locked_loop_clk_wiz
module phase_locked_loop_phase_locked_loop_clk_wiz
(clk_out1,
reset,
locked,

6
PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
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@@ -2,10 +2,10 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
// Date : Thu Jul 11 13:35:55 2024
// Date : Thu Jul 11 13:35:54 2024
// Host : Viviana running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top phase_locked_loop -prefix
// phase_locked_loop_ phase_locked_loop_stub.v
// Design : phase_locked_loop
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tfgg484-1