Use a.in

2024-07-15 22:42:43 +08:00
parent f00725e8f3
commit 68b375f9b4
66 changed files with 2581 additions and 2305 deletions
--- a/PipelineProcessor.ip_user_files/ip/phase_locked_loop/phase_locked_loop_stub.v
+++ b/PipelineProcessor.ip_user_files/ip/phase_locked_loop/phase_locked_loop_stub.v
@@ -1,24 +0,0 @@
-// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
-// Date        : Thu Jul 11 13:35:55 2024
-// Host        : Viviana running 64-bit major release  (build 9200)
-// Command     : write_verilog -force -mode synth_stub
-//               d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
-// Design      : phase_locked_loop
-// Purpose     : Stub declaration of top-level module interface
-// Device      : xc7a35tfgg484-1
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-module phase_locked_loop(clk_out1, reset, locked, clk_in1)
-/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
-/* synthesis syn_force_seq_prim="clk_out1" */;
-  output clk_out1 /* synthesis syn_isclock = 1 */;
-  input reset;
-  output locked;
-  input clk_in1;
-endmodule
--- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/activehdl/README.txt
+++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/activehdl/README.txt
@@ -5,7 +5,7 @@
 #             run the exported script and how to fetch design source file details
 #             from the file_info.txt file.
 #
-# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
+# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024
 #
 ################################################################################

--- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/modelsim/README.txt
+++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/modelsim/README.txt
@@ -5,7 +5,7 @@
 #             run the exported script and how to fetch design source file details
 #             from the file_info.txt file.
 #
-# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
+# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024
 #
 ################################################################################

--- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/questa/README.txt
+++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/questa/README.txt
@@ -5,7 +5,7 @@
 #             run the exported script and how to fetch design source file details
 #             from the file_info.txt file.
 #
-# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
+# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024
 #
 ################################################################################

--- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/riviera/README.txt
+++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/riviera/README.txt
@@ -5,7 +5,7 @@
 #             run the exported script and how to fetch design source file details
 #             from the file_info.txt file.
 #
-# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
+# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024
 #
 ################################################################################

--- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/vcs/README.txt
+++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/vcs/README.txt
@@ -5,7 +5,7 @@
 #             run the exported script and how to fetch design source file details
 #             from the file_info.txt file.
 #
-# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
+# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024
 #
 ################################################################################

--- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xcelium/README.txt
+++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xcelium/README.txt
@@ -5,7 +5,7 @@
 #             run the exported script and how to fetch design source file details
 #             from the file_info.txt file.
 #
-# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
+# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024
 #
 ################################################################################

--- a/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xsim/README.txt
+++ b/PipelineProcessor.ip_user_files/sim_scripts/phase_locked_loop/xsim/README.txt
@@ -5,7 +5,7 @@
 #             run the exported script and how to fetch design source file details
 #             from the file_info.txt file.
 #
-# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
+# Generated by export_simulation on Mon Jul 15 21:17:31 +0800 2024
 #
 ################################################################################