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un-lock-able
2024-07-15 22:42:43 +08:00
parent f00725e8f3
commit 68b375f9b4
66 changed files with 2581 additions and 2305 deletions
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PipelineProcessor.runs/impl_1/CPU.vdi
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@@ -3,8 +3,8 @@
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Sat Jul 13 23:39:15 2024
# Process ID: 27020
# Start of session at: Mon Jul 15 21:30:00 2024
# Process ID: 34208
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1
# Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi
@@ -12,13 +12,13 @@
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
#-----------------------------------------------------------
source CPU.tcl -notrace
create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 461.707 ; gain = 184.406
create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 462.992 ; gain = 184.602
Command: link_design -top CPU -part xc7a35tfgg484-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7a35tfgg484-1
INFO: [Project 1-454] Reading design checkpoint 'd:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp' for cell 'pll'
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 916.031 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.131 . Memory (MB): peak = 916.242 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 3508 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
@@ -28,18 +28,18 @@ Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/Pipelin
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54]
INFO: [Timing 38-2] Deriving generated clocks [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54]
get_clocks: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1599.215 ; gain = 558.836
get_clocks: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1599.602 ; gain = 559.164
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst'
Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1599.215 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1599.602 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:13 . Memory (MB): peak = 1599.215 ; gain = 1122.352
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1599.602 ; gain = 1123.602
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
@@ -50,112 +50,112 @@ INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.715 . Memory (MB): peak = 1599.215 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.641 . Memory (MB): peak = 1599.602 ; gain = 0.000
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1f0fa50d6
Ending Cache Timing Information Task | Checksum: 2009eb4ca
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.490 . Memory (MB): peak = 1613.043 ; gain = 13.828
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1613.895 ; gain = 14.293
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 1f0fa50d6
Phase 1.1 Core Generation And Design Setup | Checksum: 2009eb4ca
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.328 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1f0fa50d6
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2009eb4ca
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1972.328 ; gain = 0.000
Phase 1 Initialization | Checksum: 1f0fa50d6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 1 Initialization | Checksum: 2009eb4ca
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1972.328 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1f0fa50d6
Phase 2.1 Timer Update | Checksum: 2009eb4ca
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.387 . Memory (MB): peak = 1972.328 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.360 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1f0fa50d6
Phase 2.2 Timing Data Collection | Checksum: 2009eb4ca
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.405 . Memory (MB): peak = 1972.328 ; gain = 0.000
Phase 2 Timer Update And Timing Data Collection | Checksum: 1f0fa50d6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.374 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 2 Timer Update And Timing Data Collection | Checksum: 2009eb4ca
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.407 . Memory (MB): peak = 1972.328 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.375 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 13 inverters resulting in an inversion of 263 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 1e587632b
Phase 3 Retarget | Checksum: 1362abf1f
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.567 . Memory (MB): peak = 1972.328 ; gain = 0.000
Retarget | Checksum: 1e587632b
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.519 . Memory (MB): peak = 1979.137 ; gain = 0.000
Retarget | Checksum: 1362abf1f
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 14 cells
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 1b5603850
Phase 4 Constant propagation | Checksum: 164c5dc3c
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.652 . Memory (MB): peak = 1972.328 ; gain = 0.000
Constant propagation | Checksum: 1b5603850
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.595 . Memory (MB): peak = 1979.137 ; gain = 0.000
Constant propagation | Checksum: 164c5dc3c
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 15ea6b1a3
Phase 5 Sweep | Checksum: 1aad7b8f8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.816 . Memory (MB): peak = 1972.328 ; gain = 0.000
Sweep | Checksum: 15ea6b1a3
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.753 . Memory (MB): peak = 1979.137 ; gain = 0.000
Sweep | Checksum: 1aad7b8f8
INFO: [Opt 31-389] Phase Sweep created 12 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 15ea6b1a3
Phase 6 BUFG optimization | Checksum: 1aad7b8f8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.949 . Memory (MB): peak = 1972.328 ; gain = 0.000
BUFG optimization | Checksum: 15ea6b1a3
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.867 . Memory (MB): peak = 1979.137 ; gain = 0.000
BUFG optimization | Checksum: 1aad7b8f8
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 15ea6b1a3
Phase 7 Shift Register Optimization | Checksum: 1aad7b8f8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.959 . Memory (MB): peak = 1972.328 ; gain = 0.000
Shift Register Optimization | Checksum: 15ea6b1a3
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.876 . Memory (MB): peak = 1979.137 ; gain = 0.000
Shift Register Optimization | Checksum: 1aad7b8f8
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 118407d59
Phase 8 Post Processing Netlist | Checksum: 1e3f1f4ce
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.991 . Memory (MB): peak = 1972.328 ; gain = 0.000
Post Processing Netlist | Checksum: 118407d59
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.908 . Memory (MB): peak = 1979.137 ; gain = 0.000
Post Processing Netlist | Checksum: 1e3f1f4ce
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1587ffb16
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2361cfa52
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1972.328 ; gain = 0.000
Phase 9.2 Verifying Netlist Connectivity | Checksum: 1587ffb16
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 9.2 Verifying Netlist Connectivity | Checksum: 2361cfa52
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000
Phase 9 Finalization | Checksum: 1587ffb16
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 9 Finalization | Checksum: 2361cfa52
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000
Opt_design Change Summary
=========================
@@ -172,28 +172,28 @@ Opt_design Change Summary
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 1587ffb16
Ending Logic Optimization Task | Checksum: 2361cfa52
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.328 ; gain = 0.000
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1979.137 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 1587ffb16
Ending Power Optimization Task | Checksum: 2361cfa52
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1972.328 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1979.137 ; gain = 0.000
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1587ffb16
Ending Final Cleanup Task | Checksum: 2361cfa52
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.328 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1979.137 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.328 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 1587ffb16
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1979.137 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 2361cfa52
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1972.328 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1979.137 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
@@ -204,16 +204,16 @@ INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt.
report_drc completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1972.328 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1972.328 ; gain = 0.000
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1979.137 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1979.137 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1972.328 ; gain = 0.000
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1972.328 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1972.328 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.328 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1972.328 ; gain = 0.000
Wrote RouteStorage: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1979.137 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1979.137 ; gain = 0.000
Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1979.137 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1979.137 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1979.137 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_opt.dcp' has been generated.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -233,54 +233,54 @@ Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1972.328 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14ae9822c
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1972.328 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1972.328 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1979.137 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b434b971
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1979.137 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: c5c27cdb
Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: c5c27cdb
Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 1 Placer Initialization | Checksum: c5c27cdb
Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 146e69098
Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 151ff6269
Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 151ff6269
Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: a33c0039
Time (s): cpu = 00:00:01 ; elapsed = 00:00:12 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 55 LUT instances to create LUTNM shape
@@ -296,7 +296,7 @@ INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2039.625 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2034.871 ; gain = 0.000
Summary of Physical Synthesis Optimizations
============================================
@@ -320,53 +320,53 @@ Summary of Physical Synthesis Optimizations
Phase 2.4.2 Physical Synthesis In Placer | Checksum: f4053bc8
Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 2.4 Global Placement Core | Checksum: 1099bb7b7
Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 2 Global Placement | Checksum: 1099bb7b7
Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 10f07ac64
Time (s): cpu = 00:00:03 ; elapsed = 00:00:14 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1626a5454
Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 14fc2b59e
Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 169ab9d86
Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 10a431286
Phase 3.5 Small Shape Detail Placement | Checksum: 1aa221702
Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:08 ; elapsed = 00:00:24 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 145095dfd
Phase 3.6 Re-assign LUT pins | Checksum: 1a5685b79
Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:08 ; elapsed = 00:00:24 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1b6341a4b
Phase 3.7 Pipeline Register Optimization | Checksum: 2169317c7
Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297
Phase 3 Detail Placement | Checksum: 1b6341a4b
Time (s): cpu = 00:00:08 ; elapsed = 00:00:24 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 3 Detail Placement | Checksum: 2169317c7
Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297
Time (s): cpu = 00:00:08 ; elapsed = 00:00:24 . Memory (MB): peak = 2034.871 ; gain = 55.734
Phase 4 Post Placement Optimization and Clean-Up
@@ -374,7 +374,7 @@ Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 253ce2c5c
Post Placement Optimization Initialization | Checksum: 2b42d29d8
Phase 4.1.1.1 BUFG Insertion
@@ -383,33 +383,33 @@ Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.979 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 16956e8df
Phase 1 Physical Synthesis Initialization | Checksum: 2a752e597
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.808 . Memory (MB): peak = 2085.480 ; gain = 13.727
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.687 . Memory (MB): peak = 2077.816 ; gain = 9.480
INFO: [Place 46-33] Processed net data_memory/reset, BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 16956e8df
Ending Physical Synthesis Task | Checksum: 2a752e597
Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2087.383 ; gain = 15.629
Phase 4.1.1.1 BUFG Insertion | Checksum: 253ce2c5c
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2079.719 ; gain = 11.383
Phase 4.1.1.1 BUFG Insertion | Checksum: 2b42d29d8
Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
Time (s): cpu = 00:00:10 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.719 ; gain = 100.582
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=2.979. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1e8b73056
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 249162dd2
Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
Time (s): cpu = 00:00:10 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.719 ; gain = 100.582
Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
Phase 4.1 Post Commit Optimization | Checksum: 1e8b73056
Time (s): cpu = 00:00:10 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.719 ; gain = 100.582
Phase 4.1 Post Commit Optimization | Checksum: 249162dd2
Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
Time (s): cpu = 00:00:10 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.719 ; gain = 100.582
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1e8b73056
Phase 4.2 Post Placement Cleanup | Checksum: 249162dd2
Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582
Phase 4.3 Placer Reporting
@@ -428,42 +428,42 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1e8b73056
Phase 4.3.1 Print Estimated Congestion | Checksum: 249162dd2
Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
Phase 4.3 Placer Reporting | Checksum: 1e8b73056
Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582
Phase 4.3 Placer Reporting | Checksum: 249162dd2
Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2087.383 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2079.719 ; gain = 0.000
Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 11ee518f9
Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17f441675
Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
Ending Placer Task | Checksum: 91ee5898
Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582
Ending Placer Task | Checksum: f24d5614
Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 2079.719 ; gain = 100.582
66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:33 . Memory (MB): peak = 2087.383 ; gain = 115.055
place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 2079.719 ; gain = 100.582
INFO: [runtcl-4] Executing : report_io -file CPU_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 2087.383 ; gain = 0.000
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 2079.719 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 2087.383 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 2079.719 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2105.285 ; gain = 2.945
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2105.285 ; gain = 2.945
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.285 ; gain = 0.000
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2095.105 ; gain = 1.957
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2095.105 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2095.105 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2105.285 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 2105.285 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2105.285 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2105.285 ; gain = 2.945
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2095.105 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2095.105 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2095.105 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2095.105 ; gain = 1.957
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_placed.dcp' has been generated.
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -471,23 +471,23 @@ INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc
Starting Initial Update Timing Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 2150.406 ; gain = 45.121
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2141.781 ; gain = 46.676
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
75 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 2175.750 ; gain = 7.027
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2177.184 ; gain = 1.434
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2177.184 ; gain = 0.000
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 2167.066 ; gain = 6.965
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2167.965 ; gain = 1.836
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2167.965 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2177.184 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 2177.184 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2177.184 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2177.184 ; gain = 8.461
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2167.965 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2167.965 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2167.965 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2167.965 ; gain = 7.863
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -502,29 +502,29 @@ Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 7d4dfd1d ConstDB: 0 ShapeSum: 14a05b7b RouteDB: 0
Post Restoration Checksum: NetGraph: 678b964f | NumContArr: 2f28cab3 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 21c06563c
Checksum: PlaceDB: ddacfa99 ConstDB: 0 ShapeSum: 14a05b7b RouteDB: 0
Post Restoration Checksum: NetGraph: 7bb36a25 | NumContArr: 2f28cab3 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2302e2a12
Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 2288.059 ; gain = 82.391
Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 2284.527 ; gain = 85.477
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 21c06563c
Phase 2.1 Fix Topology Constraints | Checksum: 2302e2a12
Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 2288.059 ; gain = 82.391
Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 2284.527 ; gain = 85.477
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 21c06563c
Phase 2.2 Pre Route Cleanup | Checksum: 2302e2a12
Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 2288.059 ; gain = 82.391
Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 2284.527 ; gain = 85.477
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 30afab1eb
Phase 2.3 Update Timing | Checksum: 2fed2e595
Time (s): cpu = 00:00:02 ; elapsed = 00:00:18 . Memory (MB): peak = 2305.797 ; gain = 100.129
Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 2302.227 ; gain = 103.176
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.232 | TNS=0.000 | WHS=-0.150 | THS=-18.367|
@@ -540,87 +540,86 @@ Router Utilization Summary
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 2 Router Initialization | Checksum: 3338dbc90
Phase 2 Router Initialization | Checksum: 32765f03a
Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.363 ; gain = 141.695
Time (s): cpu = 00:00:11 ; elapsed = 00:00:20 . Memory (MB): peak = 2345.152 ; gain = 146.102
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 3338dbc90
Phase 3.1 Global Routing | Checksum: 32765f03a
Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.363 ; gain = 141.695
Time (s): cpu = 00:00:11 ; elapsed = 00:00:20 . Memory (MB): peak = 2345.152 ; gain = 146.102
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 18b5441e3
Phase 3.2 Initial Net Routing | Checksum: 2af1be2f2
Time (s): cpu = 00:00:04 ; elapsed = 00:00:21 . Memory (MB): peak = 2348.094 ; gain = 142.426
Phase 3 Initial Routing | Checksum: 18b5441e3
Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 2349.547 ; gain = 150.496
Phase 3 Initial Routing | Checksum: 2af1be2f2
Time (s): cpu = 00:00:04 ; elapsed = 00:00:21 . Memory (MB): peak = 2348.094 ; gain = 142.426
Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 2349.547 ; gain = 150.496
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 3428
Number of Nodes with overlaps = 278
Number of Nodes with overlaps = 35
Number of Nodes with overlaps = 12
Number of Nodes with overlaps = 4
Number of Nodes with overlaps = 3351
Number of Nodes with overlaps = 253
Number of Nodes with overlaps = 33
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.537 | TNS=0.000 | WHS=N/A | THS=N/A |
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.748 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 2a3342fb1
Phase 4.1 Global Iteration 0 | Checksum: 1c65aeb4f
Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.875 ; gain = 147.207
Phase 4 Rip-up And Reroute | Checksum: 2a3342fb1
Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.629 ; gain = 156.578
Phase 4 Rip-up And Reroute | Checksum: 1c65aeb4f
Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.875 ; gain = 147.207
Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.629 ; gain = 156.578
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 294396ac7
Phase 5.1.1 Update Timing | Checksum: 19ccb358b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.879 ; gain = 147.211
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.537 | TNS=0.000 | WHS=N/A | THS=N/A |
Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.629 ; gain = 156.578
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.748 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 5.1 Delay CleanUp | Checksum: 294396ac7
Phase 5.1 Delay CleanUp | Checksum: 19ccb358b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.879 ; gain = 147.211
Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.633 ; gain = 156.582
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 294396ac7
Phase 5.2 Clock Skew Optimization | Checksum: 19ccb358b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:34 . Memory (MB): peak = 2352.879 ; gain = 147.211
Phase 5 Delay and Skew Optimization | Checksum: 294396ac7
Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.633 ; gain = 156.582
Phase 5 Delay and Skew Optimization | Checksum: 19ccb358b
Time (s): cpu = 00:00:06 ; elapsed = 00:00:34 . Memory (MB): peak = 2352.879 ; gain = 147.211
Time (s): cpu = 00:00:14 ; elapsed = 00:00:32 . Memory (MB): peak = 2355.633 ; gain = 156.582
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 26ed22ad4
Phase 6.1.1 Update Timing | Checksum: 1aefd8a0c
Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.537 | TNS=0.000 | WHS=0.055 | THS=0.000 |
Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2355.633 ; gain = 156.582
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.748 | TNS=0.000 | WHS=0.055 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 26dd53850
Phase 6.1 Hold Fix Iter | Checksum: 1aff898c0
Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211
Phase 6 Post Hold Fix | Checksum: 26dd53850
Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2355.633 ; gain = 156.582
Phase 6 Post Hold Fix | Checksum: 1aff898c0
Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211
Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2355.633 ; gain = 156.582
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 15.1075 %
Global Horizontal Routing Utilization = 15.2186 %
Global Vertical Routing Utilization = 15.1128 %
Global Horizontal Routing Utilization = 15.1869 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
@@ -630,44 +629,44 @@ Router Utilization Summary
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 26dd53850
Phase 7 Route finalize | Checksum: 1aff898c0
Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211
Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2355.633 ; gain = 156.582
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 26dd53850
Phase 8 Verifying routed nets | Checksum: 1aff898c0
Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.930 ; gain = 149.262
Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2357.648 ; gain = 158.598
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1e498ff47
Phase 9 Depositing Routes | Checksum: 17c6dc57b
Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.930 ; gain = 149.262
Time (s): cpu = 00:00:15 ; elapsed = 00:00:34 . Memory (MB): peak = 2357.648 ; gain = 158.598
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=3.537 | TNS=0.000 | WHS=0.055 | THS=0.000 |
INFO: [Route 35-57] Estimated Timing Summary | WNS=3.748 | TNS=0.000 | WHS=0.055 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1e498ff47
Phase 10 Post Router Timing | Checksum: 17c6dc57b
Time (s): cpu = 00:00:07 ; elapsed = 00:00:36 . Memory (MB): peak = 2354.930 ; gain = 149.262
Time (s): cpu = 00:00:15 ; elapsed = 00:00:35 . Memory (MB): peak = 2357.648 ; gain = 158.598
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 118a89fd7
Phase 11 Post-Route Event Processing | Checksum: ff332dbf
Time (s): cpu = 00:00:07 ; elapsed = 00:00:37 . Memory (MB): peak = 2354.930 ; gain = 149.262
Ending Routing Task | Checksum: 118a89fd7
Time (s): cpu = 00:00:15 ; elapsed = 00:00:35 . Memory (MB): peak = 2357.648 ; gain = 158.598
Ending Routing Task | Checksum: ff332dbf
Time (s): cpu = 00:00:07 ; elapsed = 00:00:37 . Memory (MB): peak = 2354.930 ; gain = 149.262
Time (s): cpu = 00:00:15 ; elapsed = 00:00:36 . Memory (MB): peak = 2357.648 ; gain = 158.598
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
90 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:38 . Memory (MB): peak = 2354.930 ; gain = 177.746
route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:37 . Memory (MB): peak = 2357.648 ; gain = 189.684
INFO: [runtcl-4] Executing : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
Command: report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
@@ -680,7 +679,7 @@ INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2436.516 ; gain = 81.586
report_methodology: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2430.602 ; gain = 72.953
INFO: [runtcl-4] Executing : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
Command: report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
@@ -700,16 +699,16 @@ INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU_bus_sk
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2498.938 ; gain = 4.973
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2499.391 ; gain = 0.453
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2499.391 ; gain = 0.000
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2499.625 ; gain = 4.914
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2499.625 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2499.625 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.230 . Memory (MB): peak = 2499.391 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 2499.391 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2499.391 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2499.391 ; gain = 5.426
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.218 . Memory (MB): peak = 2499.625 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2499.625 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2499.625 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2499.625 ; gain = 4.914
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_routed.dcp' has been generated.
Command: write_bitstream -force CPU.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -753,5 +752,5 @@ INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT dev
INFO: [Common 17-83] Releasing license: Implementation
14 Infos, 13 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2964.719 ; gain = 465.328
INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 23:41:35 2024...
write_bitstream: Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 2965.840 ; gain = 466.215
INFO: [Common 17-206] Exiting Vivado at Mon Jul 15 21:32:10 2024...

2
PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Sat Jul 13 23:41:19 2024
| Date : Mon Jul 15 21:31:56 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file CPU_bus_skew_routed.rpt -pb CPU_bus_skew_routed.pb -rpx CPU_bus_skew_routed.rpx
| Design : CPU

2
PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Sat Jul 13 23:41:19 2024
| Date : Mon Jul 15 21:31:56 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_clock_utilization -file CPU_clock_utilization_routed.rpt
| Design : CPU

1020
PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt
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2
PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Sat Jul 13 23:39:42 2024
| Date : Mon Jul 15 21:30:24 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx
| Design : CPU

2
PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Sat Jul 13 23:41:07 2024
| Date : Mon Jul 15 21:31:43 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
| Design : CPU

2
PipelineProcessor.runs/impl_1/CPU_io_placed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Sat Jul 13 23:40:16 2024
| Date : Mon Jul 15 21:30:56 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_io -file CPU_io_placed.rpt
| Design : CPU

2
PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Sat Jul 13 23:41:13 2024
| Date : Mon Jul 15 21:31:49 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx
| Design : CPU

BIN
PipelineProcessor.runs/impl_1/CPU_opt.dcp
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4
PipelineProcessor.runs/impl_1/CPU_power_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Sat Jul 13 23:41:18 2024
| Date : Mon Jul 15 21:31:54 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
| Design : CPU
@@ -74,7 +74,7 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint | 1.000 | 0.038 | 0.029 | 0.010 | NA | Unspecified | NA |
| Vccint | 1.000 | 0.039 | 0.029 | 0.010 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.063 | 0.050 | 0.013 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |

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PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb
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PipelineProcessor.runs/impl_1/CPU_routed.dcp
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PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb
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1309
PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt
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10
PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Sat Jul 13 23:40:17 2024
| Date : Mon Jul 15 21:30:56 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb
| Design : CPU
@@ -58,8 +58,8 @@ Table of Contents
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 368 | Yes | Set | - |
| 17764 | Yes | Reset | - |
| 152 | Yes | Set | - |
| 17980 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -180,15 +180,15 @@ Table of Contents
+-----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+-----------+-------+---------------------+
| FDRE | 17764 | Flop & Latch |
| FDRE | 17980 | Flop & Latch |
| LUT6 | 7154 | LUT |
| MUXF7 | 2377 | MuxFx |
| MUXF8 | 1088 | MuxFx |
| LUT5 | 825 | LUT |
| FDSE | 368 | Flop & Latch |
| LUT4 | 281 | LUT |
| LUT3 | 230 | LUT |
| LUT2 | 154 | LUT |
| FDSE | 152 | Flop & Latch |
| CARRY4 | 39 | CarryLogic |
| OBUF | 13 | IO |
| DSP48E1 | 3 | Block Arithmetic |

2
PipelineProcessor.runs/impl_1/clockInfo.txt
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@@ -1,6 +1,6 @@
-------------------------------------
| Tool Version : Vivado v.2023.2
| Date : Sat Jul 13 23:39:48 2024
| Date : Mon Jul 15 21:30:29 2024
| Host : Viviana
| Design : design_1
| Device : xc7a35t-fgg484-1--

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4
PipelineProcessor.runs/impl_1/vivado.jou
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@@ -3,8 +3,8 @@
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Sat Jul 13 23:39:15 2024
# Process ID: 27020
# Start of session at: Mon Jul 15 21:30:00 2024
# Process ID: 34208
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1
# Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi

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4
PipelineProcessor.runs/phase_locked_loop_synth_1/.Xil/phase_locked_loop_propImpl.xdc
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@@ -1,4 +0,0 @@
set_property SRC_FILE_INFO {cfile:d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc rfile:../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc id:1 order:EARLY scoped_inst:inst} [current_design]
current_instance inst
set_property src_info {type:SCOPED_XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design]
set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100

32
PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc
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@@ -1,32 +0,0 @@
# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.
# IP: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
# IP: The module: 'phase_locked_loop' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# IP: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
# IP: The module: 'phase_locked_loop' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet

10
PipelineProcessor.runs/phase_locked_loop_synth_1/htr.txt
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@@ -1,10 +0,0 @@
REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
REM Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
REM
vivado -log phase_locked_loop.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source phase_locked_loop.tcl

BIN
PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp
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246
PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.tcl
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@@ -1,246 +0,0 @@
#
# Synthesis run script generated by Vivado
#
set TIME_start [clock seconds]
namespace eval ::optrace {
variable script "D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.tcl"
variable category "vivado_synth"
}
# Try to connect to running dispatch if we haven't done so already.
# This code assumes that the Tcl interpreter is not using threads,
# since the ::dispatch::connected variable isn't mutex protected.
if {![info exists ::dispatch::connected]} {
namespace eval ::dispatch {
variable connected false
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
set result "true"
if {[catch {
if {[lsearch -exact [package names] DispatchTcl] < 0} {
set result [load librdi_cd_clienttcl[info sharedlibextension]]
}
if {$result eq "false"} {
puts "WARNING: Could not load dispatch client library"
}
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
if { $connect_id eq "" } {
puts "WARNING: Could not initialize dispatch client"
} else {
puts "INFO: Dispatch client connection id - $connect_id"
set connected true
}
} catch_res]} {
puts "WARNING: failed to connect to dispatch server - $catch_res"
}
}
}
}
if {$::dispatch::connected} {
# Remove the dummy proc if it exists.
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
rename ::OPTRACE ""
}
proc ::OPTRACE { task action {tags {} } } {
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
}
# dispatch is generic. We specifically want to attach logging.
::vitis_log::connect_client
} else {
# Add dummy proc if it doesn't exist.
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
# Do nothing
}
}
}
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
OPTRACE "phase_locked_loop_synth_1" START { ROLLUP_AUTO }
set_param project.vivado.isBlockSynthRun true
set_msg_config -msgmgr_mode ooc_run
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7a35tfgg484-1
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.cache/wt [current_project]
set_property parent.project_path D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.xpr [current_project]
set_property XPM_LIBRARIES XPM_CDC [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
OPTRACE "Adding files" START { }
read_ip -quiet D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc]
set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc]
set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc]
OPTRACE "Adding files" END { }
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc]
set_param ips.enableIPCacheLiteLoad 1
OPTRACE "Configure IP Cache" START { }
set cacheID [config_ip_cache -export -no_bom -dir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1 -new_name phase_locked_loop -ip [get_ips phase_locked_loop]]
OPTRACE "Configure IP Cache" END { }
if { $cacheID == "" } {
close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { }
synth_design -top phase_locked_loop -part xc7a35tfgg484-1 -incremental_mode off -mode out_of_context
OPTRACE "synth_design" END { }
OPTRACE "Write IP Cache" START { }
#---------------------------------------------------------
# Generate Checkpoint/Stub/Simulation Files For IP Cache
#---------------------------------------------------------
# disable binary constraint mode for IPCache checkpoints
set_param constraints.enableBinaryConstraints false
catch {
write_checkpoint -force -noxdef -rename_prefix phase_locked_loop_ phase_locked_loop.dcp
set ipCachedFiles {}
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_stub.v
lappend ipCachedFiles phase_locked_loop_stub.v
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_stub.vhdl
lappend ipCachedFiles phase_locked_loop_stub.vhdl
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_sim_netlist.v
lappend ipCachedFiles phase_locked_loop_sim_netlist.v
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_sim_netlist.vhdl
lappend ipCachedFiles phase_locked_loop_sim_netlist.vhdl
set TIME_taken [expr [clock seconds] - $TIME_start]
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
config_ip_cache -add -dcp phase_locked_loop.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips phase_locked_loop]
}
OPTRACE "Write IP Cache" END { }
}
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
}
rename_ref -prefix_all phase_locked_loop_
OPTRACE "write_checkpoint" START { CHECKPOINT }
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef phase_locked_loop.dcp
OPTRACE "write_checkpoint" END { }
OPTRACE "synth reports" START { REPORT }
create_report "phase_locked_loop_synth_1_synth_report_utilization_0" "report_utilization -file phase_locked_loop_utilization_synth.rpt -pb phase_locked_loop_utilization_synth.pb"
OPTRACE "synth reports" END { }
if { [catch {
file copy -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp
} _RESULT ] } {
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
write_verilog -force -mode synth_stub d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode synth_stub d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_verilog -force -mode funcsim d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode funcsim d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
} else {
if { [catch {
file copy -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp
} _RESULT ] } {
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
file rename -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_stub.v d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_stub.vhdl d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_sim_netlist.v d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
file rename -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_sim_netlist.vhdl d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
close [open .end.used_ip_cache.rst w]
}; # end if cacheID
if {[file isdir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.ip_user_files/ip/phase_locked_loop]} {
catch {
file copy -force d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.ip_user_files/ip/phase_locked_loop
}
}
if {[file isdir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.ip_user_files/ip/phase_locked_loop]} {
catch {
file copy -force d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.vhdl D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.ip_user_files/ip/phase_locked_loop
}
}
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]
OPTRACE "phase_locked_loop_synth_1" END { }

240
PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds
View File

@@ -1,240 +0,0 @@
#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Thu Jul 11 13:35:23 2024
# Process ID: 33384
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1
# Command line: vivado.exe -log phase_locked_loop.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source phase_locked_loop.tcl
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds
# Journal file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1\vivado.jou
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
#-----------------------------------------------------------
source phase_locked_loop.tcl -notrace
create_project: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 464.625 ; gain = 187.449
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: phase_locked_loop
Command: synth_design -top phase_locked_loop -part xc7a35tfgg484-1 -incremental_mode off -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
INFO: [Device 21-403] Loading part xc7a35tfgg484-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 27764
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 1306.332 ; gain = 439.227
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v:65]
INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop_clk_wiz' [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v:65]
INFO: [Synth 8-6157] synthesizing module 'IBUF' [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631]
INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631]
INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111351]
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
Parameter CLKFBOUT_MULT bound to: 17 - type: integer
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double
Parameter CLKOUT0_DIVIDE bound to: 17 - type: integer
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
Parameter COMPENSATION bound to: ZHOLD - type: string
Parameter DIVCLK_DIVIDE bound to: 2 - type: integer
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111351]
INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop_clk_wiz' (0#1) [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v:65]
INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v:65]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1415.195 ; gain = 548.090
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1415.195 ; gain = 548.090
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1415.195 ; gain = 548.090
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1415.195 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc] for cell 'inst'
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc] for cell 'inst'
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc] for cell 'inst'
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc] for cell 'inst'
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'inst'
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/phase_locked_loop_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/phase_locked_loop_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
INFO: [Timing 38-2] Deriving generated clocks
Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc]
Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1429.117 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1429.145 ; gain = 0.027
INFO: [Designutils 20-5008] Incremental synthesis strategy off
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tfgg484-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 2|
|2 |PLLE2_ADV | 1|
|3 |IBUF | 1|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1429.145 ; gain = 548.090
Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1429.145 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1434.039 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete | Checksum: 5cde1ffc
INFO: [Common 17-83] Releasing license: Synthesis
30 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:23 . Memory (MB): peak = 1434.039 ; gain = 956.965
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1434.039 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP phase_locked_loop, cache-ID = 11b3438a8319906c
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1434.039 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file phase_locked_loop_utilization_synth.rpt -pb phase_locked_loop_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Thu Jul 11 13:35:55 2024...

BIN
PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_utilization_synth.pb
View File

Binary file not shown.

175
PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_utilization_synth.rpt
View File

@@ -1,175 +0,0 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Thu Jul 11 13:35:55 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_utilization -file phase_locked_loop_utilization_synth.rpt -pb phase_locked_loop_utilization_synth.pb
| Design : phase_locked_loop
| Device : xc7a35tfgg484-1
| Speed File : -1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 0 | 0 | 0 | 20800 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 20800 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 0 | 0 | 0 | 41600 | 0.00 |
| Register as Flip Flop | 0 | 0 | 0 | 41600 | 0.00 |
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 0 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 50 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 100 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 90 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 1 | 0 | 0 | 250 | 0.40 |
| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 240 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 250 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 250 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
| BUFIO | 0 | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 1 | 0 | 0 | 5 | 20.00 |
| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 0 | 20 | 0.00 |
+------------+------+-------+------------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
7. Primitives
-------------
+-----------+------+---------------------+
| Ref Name | Used | Functional Category |
+-----------+------+---------------------+
| BUFG | 2 | Clock |
| PLLE2_ADV | 1 | Clock |
| IBUF | 1 | IO |
+-----------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

14
PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.jou
View File

@@ -1,14 +0,0 @@
#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Thu Jul 11 13:35:23 2024
# Process ID: 33384
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1
# Command line: vivado.exe -log phase_locked_loop.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source phase_locked_loop.tcl
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds
# Journal file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1\vivado.jou
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
#-----------------------------------------------------------
source phase_locked_loop.tcl -notrace

BIN
PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.pb
View File

Binary file not shown.

BIN
PipelineProcessor.runs/synth_1/CPU.dcp
View File

Binary file not shown.

3
PipelineProcessor.runs/synth_1/CPU.tcl
View File

@@ -70,7 +70,6 @@ proc create_report { reportName command } {
}
}
OPTRACE "synth_1" START { ROLLUP_AUTO }
set_param chipscope.maxJobs 5
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7a35tfgg484-1
@@ -120,6 +119,8 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
read_xdc D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc
set_property used_in_implementation false [get_files D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc]
set_param ips.enableIPCacheLiteLoad 1
read_checkpoint -auto_incremental -incremental D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp

78
PipelineProcessor.runs/synth_1/CPU.vds
View File

@@ -3,8 +3,8 @@
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Sat Jul 13 23:37:30 2024
# Process ID: 27796
# Start of session at: Mon Jul 15 21:28:25 2024
# Process ID: 34260
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1
# Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds
@@ -12,7 +12,7 @@
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
#-----------------------------------------------------------
source CPU.tcl -notrace
create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 462.984 ; gain = 184.277
create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 463.656 ; gain = 184.578
Command: read_checkpoint -auto_incremental -incremental D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
@@ -25,13 +25,13 @@ INFO: [Designutils 20-5440] No compile time benefit to using incremental synthes
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 15424
INFO: [Synth 8-7075] Helper process launched with PID 34600
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 1308.293 ; gain = 439.242
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 1309.031 ; gain = 440.004
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'CPU' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/CPU.v:2]
INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-27796-Viviana/realtime/phase_locked_loop_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-27796-Viviana/realtime/phase_locked_loop_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-34260-Viviana/realtime/phase_locked_loop_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-34260-Viviana/realtime/phase_locked_loop_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'InstFetch' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstFetch.v:2]
INFO: [Synth 8-6157] synthesizing module 'InstructionMemory' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'InstructionMemory' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3]
@@ -66,18 +66,18 @@ WARNING: [Synth 8-7129] Port address[0] in module DataMemory is either unconnect
WARNING: [Synth 8-7129] Port address[1] in module InstructionMemory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module InstructionMemory is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.973 ; gain = 609.922
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.824 ; gain = 609.797
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1478.973 ; gain = 609.922
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.824 ; gain = 609.797
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1478.973 ; gain = 609.922
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.824 ; gain = 609.797
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.191 . Memory (MB): peak = 1478.973 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.169 . Memory (MB): peak = 1478.824 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
@@ -88,24 +88,26 @@ Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcesso
Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/CPU_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/CPU_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1586.277 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1583.539 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1586.277 ; gain = 0.000
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.061 . Memory (MB): peak = 1583.539 ; gain = 0.000
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 1586.277 ; gain = 717.227
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1583.539 ; gain = 714.512
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tfgg484-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 1586.277 ; gain = 717.227
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1583.539 ; gain = 714.512
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
@@ -114,10 +116,10 @@ Applied set_property IO_BUFFER_TYPE = NONE for hardware_clk. (constraint file d
Applied set_property CLOCK_BUFFER_TYPE = NONE for hardware_clk. (constraint file d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc, line 4).
Applied set_property KEEP_HIERARCHY = SOFT for pll. (constraint file auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 1586.277 ; gain = 717.227
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1583.539 ; gain = 714.512
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:22 . Memory (MB): peak = 1586.277 ; gain = 717.227
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:18 . Memory (MB): peak = 1583.539 ; gain = 714.512
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
@@ -173,7 +175,7 @@ DSP Report: Generating DSP alu/result0, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:00:44 . Memory (MB): peak = 1586.277 ; gain = 717.227
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:40 . Memory (MB): peak = 1583.539 ; gain = 714.512
---------------------------------------------------------------------------------
Sort Area is CPU__GC0 alu/result0_0 : 0 0 : 3101 5879 : Used 1 time 0
Sort Area is CPU__GC0 alu/result0_0 : 0 1 : 2778 5879 : Used 1 time 0
@@ -209,19 +211,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:51 . Memory (MB): peak = 1586.277 ; gain = 717.227
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:46 . Memory (MB): peak = 1583.539 ; gain = 714.512
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:01:07 . Memory (MB): peak = 1714.559 ; gain = 845.508
Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:01:00 . Memory (MB): peak = 1713.750 ; gain = 844.723
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:02 ; elapsed = 00:01:14 . Memory (MB): peak = 1720.918 ; gain = 851.867
Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:01:06 . Memory (MB): peak = 1720.066 ; gain = 851.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@@ -239,37 +241,37 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:03 ; elapsed = 00:01:19 . Memory (MB): peak = 1720.918 ; gain = 851.867
Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:01:11 . Memory (MB): peak = 1720.066 ; gain = 851.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:03 ; elapsed = 00:01:19 . Memory (MB): peak = 1720.918 ; gain = 851.867
Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:01:11 . Memory (MB): peak = 1720.066 ; gain = 851.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:01:12 . Memory (MB): peak = 1720.066 ; gain = 851.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867
Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:01:12 . Memory (MB): peak = 1720.066 ; gain = 851.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867
Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:01:13 . Memory (MB): peak = 1720.066 ; gain = 851.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867
Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:01:13 . Memory (MB): peak = 1720.066 ; gain = 851.039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -307,33 +309,33 @@ Report Cell Usage:
|9 |LUT6 | 7154|
|10 |MUXF7 | 2377|
|11 |MUXF8 | 1088|
|12 |FDRE | 17752|
|13 |FDSE | 368|
|12 |FDRE | 17968|
|13 |FDSE | 152|
|14 |IBUF | 1|
|15 |OBUF | 13|
+------+------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867
Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:01:13 . Memory (MB): peak = 1720.066 ; gain = 851.039
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:03 ; elapsed = 00:01:18 . Memory (MB): peak = 1720.918 ; gain = 744.562
Synthesis Optimization Complete : Time (s): cpu = 00:00:03 ; elapsed = 00:01:22 . Memory (MB): peak = 1720.918 ; gain = 851.867
Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:01:10 . Memory (MB): peak = 1720.066 ; gain = 746.324
Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:01:13 . Memory (MB): peak = 1720.066 ; gain = 851.039
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.294 . Memory (MB): peak = 1720.918 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.237 . Memory (MB): peak = 1720.066 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 3507 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1720.918 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1720.688 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete | Checksum: 560bc728
Synth Design complete | Checksum: 5b34e2bc
INFO: [Common 17-83] Releasing license: Synthesis
51 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:03 ; elapsed = 00:01:29 . Memory (MB): peak = 1720.918 ; gain = 1244.781
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1720.918 ; gain = 0.000
synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:01:19 . Memory (MB): peak = 1720.688 ; gain = 1244.133
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1720.688 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 23:39:08 2024...
INFO: [Common 17-206] Exiting Vivado at Mon Jul 15 21:29:53 2024...

10
PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Sat Jul 13 23:39:08 2024
| Date : Mon Jul 15 21:29:53 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb
| Design : CPU
@@ -58,8 +58,8 @@ Warning! LUT value is adjusted to account for LUT combining.
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 368 | Yes | Set | - |
| 17752 | Yes | Reset | - |
| 152 | Yes | Set | - |
| 17968 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -152,15 +152,15 @@ Warning! LUT value is adjusted to account for LUT combining.
+----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+----------+-------+---------------------+
| FDRE | 17752 | Flop & Latch |
| FDRE | 17968 | Flop & Latch |
| LUT6 | 7154 | LUT |
| MUXF7 | 2377 | MuxFx |
| MUXF8 | 1088 | MuxFx |
| LUT5 | 825 | LUT |
| FDSE | 368 | Flop & Latch |
| LUT4 | 281 | LUT |
| LUT3 | 230 | LUT |
| LUT2 | 154 | LUT |
| FDSE | 152 | Flop & Latch |
| CARRY4 | 39 | CarryLogic |
| LUT1 | 15 | LUT |
| OBUF | 13 | IO |

7
PipelineProcessor.runs/synth_1/dont_touch.xdc Normal file
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@@ -0,0 +1,7 @@
# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.
# XDC: new/top.xdc
# IP: ip/phase_locked_loop/phase_locked_loop.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==phase_locked_loop || ORIG_REF_NAME==phase_locked_loop} -quiet] -quiet

4
PipelineProcessor.runs/synth_1/vivado.jou
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@@ -3,8 +3,8 @@
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Sat Jul 13 23:37:30 2024
# Process ID: 27796
# Start of session at: Mon Jul 15 21:28:25 2024
# Process ID: 34260
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1
# Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds

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PipelineProcessor.runs/synth_1/vivado.pb
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