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Pass bgtz test

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un-lock-able
2024-07-11 00:27:58 +08:00
parent 15e6ea796b
commit 7b24b6bc2f
3 changed files with 5 additions and 5 deletions
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BIN
PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
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8
PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
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@@ -7,22 +7,22 @@ module InstructionMemory (
always @(*) begin
case (address[31:2])
20'd0: instruction <= 32'h2010fffe; // addi $s0, $zero, -2
20'd0: instruction <= 32'h20110002; // addi $s1, $zero, 2
20'd1: instruction <= 32'h00000000;
20'd2: instruction <= 32'h00000000;
20'd3: instruction <= 32'h00000000;
20'd4: instruction <= 32'h00000000; // start:
20'd5: instruction <= 32'h22100001; // addi $s0, $s0, 1
20'd5: instruction <= 32'h2231ffff; // addi $s1, $s1, -1
20'd6: instruction <= 32'h00000000;
20'd7: instruction <= 32'h00000000;
20'd8: instruction <= 32'h00000000;
20'd9: instruction <= 32'h00000000;
20'd10: instruction <= 32'h1a00fffa; // blez $s0, start
20'd10: instruction <= 32'h1e20fffa; // bgtz $s1, start
20'd11: instruction <= 32'h00000000;
20'd12: instruction <= 32'h00000000;
20'd13: instruction <= 32'h00000000;
20'd14: instruction <= 32'h00000000; // end:
20'd15: instruction <= 32'h0810000f; // j end
20'd15: instruction <= 32'h0800000f; // j end
default: instruction <= 32'h00000000;
endcase
end

2
PipelineProcessor.xpr
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@@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="194"/>
<Option Name="WTXSimLaunchSim" Val="198"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>