Fix sw problem

PipelineProcessor.srcs/sources_1/new/CPU.v

@@ -223,7 +223,7 @@ module CPU (
         .EX_rs_address(EX_rs_address),
         .EX_rt_address(EX_rt_address),
         .MEM_register_write(MEM_register_write),
-        .MEM_register_write_address(MEM_register_write_address),
+        .MEM_register_write_address(MEM_register_write_destination),
         .WB_register_write(WB_register_write),
         .WB_register_write_address(WB_register_write_address),
         .IDA_source(EXforward_IDA_source),

PipelineProcessor.srcs/sources_1/new/DataMemory.v

@@ -9,31 +9,33 @@ module DataMemory (
     output reg [31:0] read_data,
     output [31:0] bcd_hardwire
 );
-    parameter integer MEM_SIZE = 1024;
+    parameter integer MEM_SIZE_IN_WORD = 64;
     parameter integer START_ADDRESS = 32'h00000000;
 
-    reg [31:0] memory_data[MEM_SIZE + START_ADDRESS - 1:START_ADDRESS];
+    localparam integer StartAddressInWord = START_ADDRESS / 4;
 
-    assign bcd_hardwire = memory_data[START_ADDRESS+4];
+    reg [31:0] memory_data[MEM_SIZE_IN_WORD + StartAddressInWord - 1 : StartAddressInWord];
+
+    assign bcd_hardwire = memory_data[StartAddressInWord + 4];
 
     integer i;
 
     initial begin
-        for (i = START_ADDRESS; i < MEM_SIZE + START_ADDRESS; i = i + 1) begin
+        for (i = StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1) begin
             memory_data[i] <= 32'h00000000;
         end
     end
 
     always @(posedge clk) begin
         if (reset) begin
-            for (i = START_ADDRESS; i < MEM_SIZE + START_ADDRESS; i = i + 1) begin
+            for (i = StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1) begin
                 memory_data[i] <= 32'h00000000;
             end
         end else begin
             if (write_enable) begin
-                memory_data[address] <= write_data;
+                memory_data[address[31:2]] <= write_data;
             end
-            read_data <= memory_data[address];
+            read_data <= memory_data[address[31:2]];
         end
     end
 endmodule

PipelineProcessor.srcs/sources_1/new/InstructionMemory.v

@@ -7,9 +7,10 @@ module InstructionMemory (
 
     always @(*) begin
         case (address[31:2])
-            20'd0:  instruction <= 32'h3c104000;
-            20'd6:  instruction <= 32'h2011000a;
-            20'd11: instruction <= 32'hae11000f;
+            20'd0:  instruction <= 32'h3c104000; // lui $s0, 0x400
+            20'd6:  instruction <= 32'h2011000a; // addi $s1, $0, 0xa
+            20'd11: instruction <= 32'hae110010; // sw $s1, 16($s0)
+            20'd16: instruction <= 32'h8e120010; // lw $s2, 16($s0)
             default: instruction <= 32'h00000000;
         endcase
     end

PipelineProcessor.xpr

@@ -60,7 +60,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
-    <Option Name="WTXSimLaunchSim" Val="104"/>
+    <Option Name="WTXSimLaunchSim" Val="123"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>