Initial commit
This commit is contained in:
@@ -0,0 +1,311 @@
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||||
2023.2:
|
||||
* Version 6.0 (Rev. 13)
|
||||
* Bug Fix: CR Fixes
|
||||
* Other: CR Fixes
|
||||
|
||||
2023.1.2:
|
||||
* Version 6.0 (Rev. 12)
|
||||
* No changes
|
||||
|
||||
2023.1.1:
|
||||
* Version 6.0 (Rev. 12)
|
||||
* No changes
|
||||
|
||||
2023.1:
|
||||
* Version 6.0 (Rev. 12)
|
||||
* Bug Fix: CR Fixes
|
||||
* Other: CR Fixes
|
||||
|
||||
2022.2.2:
|
||||
* Version 6.0 (Rev. 11)
|
||||
* No changes
|
||||
|
||||
2022.2.1:
|
||||
* Version 6.0 (Rev. 11)
|
||||
* No changes
|
||||
|
||||
2022.2:
|
||||
* Version 6.0 (Rev. 11)
|
||||
* Bug Fix: CR Fixes
|
||||
* Other: CR Fixes
|
||||
|
||||
2022.1.2:
|
||||
* Version 6.0 (Rev. 10)
|
||||
* No changes
|
||||
|
||||
2022.1.1:
|
||||
* Version 6.0 (Rev. 10)
|
||||
* No changes
|
||||
|
||||
2022.1:
|
||||
* Version 6.0 (Rev. 10)
|
||||
* Bug Fix: CR Fixes
|
||||
* Other: CR Fixes
|
||||
|
||||
2021.2.2:
|
||||
* Version 6.0 (Rev. 9)
|
||||
* No changes
|
||||
|
||||
2021.2.1:
|
||||
* Version 6.0 (Rev. 9)
|
||||
* No changes
|
||||
|
||||
2021.2:
|
||||
* Version 6.0 (Rev. 9)
|
||||
* Bug Fix: CR Fixes
|
||||
* Other: CR Fixes
|
||||
|
||||
2021.1.1:
|
||||
* Version 6.0 (Rev. 8)
|
||||
* No changes
|
||||
|
||||
2021.1:
|
||||
* Version 6.0 (Rev. 8)
|
||||
* Bug Fix: Internal GUI fixes
|
||||
* Other: CR Fixes
|
||||
|
||||
2020.3:
|
||||
* Version 6.0 (Rev. 7)
|
||||
* Bug Fix: Internal GUI fixes
|
||||
* Other: CR Fixes
|
||||
|
||||
2020.2.2:
|
||||
* Version 6.0 (Rev. 6)
|
||||
* No changes
|
||||
|
||||
2020.2.1:
|
||||
* Version 6.0 (Rev. 6)
|
||||
* No changes
|
||||
|
||||
2020.2:
|
||||
* Version 6.0 (Rev. 6)
|
||||
* Bug Fix: Internal GUI fixes
|
||||
* Other: CR Fixes
|
||||
|
||||
2020.1.1:
|
||||
* Version 6.0 (Rev. 5)
|
||||
* No changes
|
||||
|
||||
2020.1:
|
||||
* Version 6.0 (Rev. 5)
|
||||
* Bug Fix: Internal GUI fixes
|
||||
* Other: CR Fixes
|
||||
|
||||
2019.2.2:
|
||||
* Version 6.0 (Rev. 4)
|
||||
* No changes
|
||||
|
||||
2019.2.1:
|
||||
* Version 6.0 (Rev. 4)
|
||||
* No changes
|
||||
|
||||
2019.2:
|
||||
* Version 6.0 (Rev. 4)
|
||||
* Bug Fix: Internal GUI fixes
|
||||
* Other: CR Fixes
|
||||
|
||||
2019.1.3:
|
||||
* Version 6.0 (Rev. 3)
|
||||
* No changes
|
||||
|
||||
2019.1.2:
|
||||
* Version 6.0 (Rev. 3)
|
||||
* No changes
|
||||
|
||||
2019.1.1:
|
||||
* Version 6.0 (Rev. 3)
|
||||
* No changes
|
||||
|
||||
2019.1:
|
||||
* Version 6.0 (Rev. 3)
|
||||
* Bug Fix: Internal GUI fixes
|
||||
* Other: New family support added
|
||||
|
||||
2018.3.1:
|
||||
* Version 6.0 (Rev. 2)
|
||||
* No changes
|
||||
|
||||
2018.3:
|
||||
* Version 6.0 (Rev. 2)
|
||||
* Bug Fix: Made input source independent for primary and secondary clock
|
||||
* Other: New family support added
|
||||
|
||||
2018.2:
|
||||
* Version 6.0 (Rev. 1)
|
||||
* Bug Fix: Removed vco freq check when Primitive is None
|
||||
* Other: New family support added
|
||||
|
||||
2018.1:
|
||||
* Version 6.0
|
||||
* Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature
|
||||
* Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI
|
||||
* Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals.
|
||||
* Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support
|
||||
* Other: DRCs added for invalid input values in Override mode
|
||||
|
||||
2017.4:
|
||||
* Version 5.4 (Rev. 3)
|
||||
* Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL
|
||||
* Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4
|
||||
|
||||
2017.3:
|
||||
* Version 5.4 (Rev. 2)
|
||||
* General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices
|
||||
|
||||
2017.2:
|
||||
* Version 5.4 (Rev. 1)
|
||||
* General: Internal GUI changes. No effect on the customer design.
|
||||
|
||||
2017.1:
|
||||
* Version 5.4
|
||||
* Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices.
|
||||
* Other: Added support for new zynq ultrascale plus devices.
|
||||
|
||||
2016.4:
|
||||
* Version 5.3 (Rev. 3)
|
||||
* Bug Fix: Internal GUI issues are fixed.
|
||||
|
||||
2016.3:
|
||||
* Version 5.3 (Rev. 2)
|
||||
* Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs.
|
||||
* Feature Enhancement: Added Matched Routing Option for better timing solutions.
|
||||
* Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list.
|
||||
* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
|
||||
* Other: Added support for Spartan7 devices.
|
||||
|
||||
2016.2:
|
||||
* Version 5.3 (Rev. 1)
|
||||
* Internal register bit update, no effect on customer designs.
|
||||
|
||||
2016.1:
|
||||
* Version 5.3
|
||||
* Added Clock Monitor Feature as part of clocking wizard
|
||||
* DRP registers can be directly written through AXI without resource utilization
|
||||
* Changes to HDL library management to support Vivado IP simulation library
|
||||
|
||||
2015.4.2:
|
||||
* Version 5.2 (Rev. 1)
|
||||
* No changes
|
||||
|
||||
2015.4.1:
|
||||
* Version 5.2 (Rev. 1)
|
||||
* No changes
|
||||
|
||||
2015.4:
|
||||
* Version 5.2 (Rev. 1)
|
||||
* Internal device family change, no functional changes
|
||||
|
||||
2015.3:
|
||||
* Version 5.2
|
||||
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
|
||||
* Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported
|
||||
* Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature
|
||||
* When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format
|
||||
* Example design and simulation files are delivered in verilog only
|
||||
|
||||
2015.2.1:
|
||||
* Version 5.1 (Rev. 6)
|
||||
* No changes
|
||||
|
||||
2015.2:
|
||||
* Version 5.1 (Rev. 6)
|
||||
* No changes
|
||||
|
||||
2015.1:
|
||||
* Version 5.1 (Rev. 6)
|
||||
* Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices
|
||||
* Supported devices and production status are now determined automatically, to simplify support for future devices
|
||||
|
||||
2014.4.1:
|
||||
* Version 5.1 (Rev. 5)
|
||||
* No changes
|
||||
|
||||
2014.4:
|
||||
* Version 5.1 (Rev. 5)
|
||||
* Internal device family change, no functional changes
|
||||
* updates related to the source selection based on board interface for zed board
|
||||
|
||||
2014.3:
|
||||
* Version 5.1 (Rev. 4)
|
||||
* Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface
|
||||
|
||||
2014.2:
|
||||
* Version 5.1 (Rev. 3)
|
||||
* Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065
|
||||
|
||||
2014.1:
|
||||
* Version 5.1 (Rev. 2)
|
||||
* Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock
|
||||
* Internal device family name change, no functional changes
|
||||
|
||||
2013.4:
|
||||
* Version 5.1 (Rev. 1)
|
||||
* Added support for Ultrascale devices
|
||||
* Updated Board Flow GUI to select the clock interfaces
|
||||
* Fixed issue with Stub file parameter error for BUFR output driver
|
||||
|
||||
2013.3:
|
||||
* Version 5.1
|
||||
* Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL
|
||||
* Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
|
||||
* Fixed precision issues between displayed and actual frequencies
|
||||
* Added tool tips to GUI
|
||||
* Added Jitter and Phase error values to IP properties
|
||||
* Added support for Cadence IES and Synopsys VCS simulators
|
||||
* Reduced warnings in synthesis and simulation
|
||||
* Enhanced support for IP Integrator
|
||||
|
||||
2013.2:
|
||||
* Version 5.0 (Rev. 1)
|
||||
* Fixed issue with clock constraints for multiple instances of clocking wizard
|
||||
* Updated Life-Cycle status of devices
|
||||
|
||||
2013.1:
|
||||
* Version 5.0
|
||||
* Lower case ports for Verilog
|
||||
* Added Safe Clock Startup and Clock Sequencing
|
||||
|
||||
(c) Copyright 2008 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of AMD and is protected under U.S. and international copyright
|
||||
and other intellectual property laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
AMD, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) AMD shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or AMD had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
AMD products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of AMD products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
Binary file not shown.
@@ -0,0 +1,89 @@
|
||||
|
||||
// file: phase_locked_loop.v
|
||||
// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1__10.00000______0.000______50.0______446.763____313.282
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_________100.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "phase_locked_loop,clk_wiz_v6_0_13_0_0,{component_name=phase_locked_loop,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module phase_locked_loop
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
input reset,
|
||||
output locked,
|
||||
// Clock in ports
|
||||
input clk_in1
|
||||
);
|
||||
|
||||
phase_locked_loop_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
// Status and control signals
|
||||
.reset(reset),
|
||||
.locked(locked),
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,57 @@
|
||||
|
||||
# file: phase_locked_loop.xdc
|
||||
# (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
# Input clock periods. These duplicate the values entered for the
|
||||
# input clocks. You can use these to time your system. If required
|
||||
# commented constraints can be used in the top level xdc
|
||||
#----------------------------------------------------------------
|
||||
# Connect to input port when clock capable pin is selected for input
|
||||
create_clock -period 10.000 [get_ports clk_in1]
|
||||
set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100
|
||||
|
||||
|
||||
set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]
|
||||
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
@@ -0,0 +1,181 @@
|
||||
|
||||
// file: phase_locked_loop.v
|
||||
// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1__10.00000______0.000______50.0______446.763____313.282
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_________100.000____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module phase_locked_loop_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
input reset,
|
||||
output locked,
|
||||
input clk_in1
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_phase_locked_loop;
|
||||
wire clk_in2_phase_locked_loop;
|
||||
IBUF clkin1_ibufg
|
||||
(.O (clk_in1_phase_locked_loop),
|
||||
.I (clk_in1));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_phase_locked_loop;
|
||||
wire clk_out2_phase_locked_loop;
|
||||
wire clk_out3_phase_locked_loop;
|
||||
wire clk_out4_phase_locked_loop;
|
||||
wire clk_out5_phase_locked_loop;
|
||||
wire clk_out6_phase_locked_loop;
|
||||
wire clk_out7_phase_locked_loop;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_phase_locked_loop;
|
||||
wire clkfbout_buf_phase_locked_loop;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout1_unused;
|
||||
wire clkout2_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
wire reset_high;
|
||||
|
||||
PLLE2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (5),
|
||||
.CLKFBOUT_MULT (41),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKOUT0_DIVIDE (82),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKIN1_PERIOD (10.000))
|
||||
plle2_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_phase_locked_loop),
|
||||
.CLKOUT0 (clk_out1_phase_locked_loop),
|
||||
.CLKOUT1 (clkout1_unused),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_phase_locked_loop),
|
||||
.CLKIN1 (clk_in1_phase_locked_loop),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (reset_high));
|
||||
assign reset_high = reset;
|
||||
|
||||
assign locked = locked_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_phase_locked_loop),
|
||||
.I (clkfbout_phase_locked_loop));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_phase_locked_loop));
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,55 @@
|
||||
|
||||
# file: phase_locked_loop_ooc.xdc
|
||||
# (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of AMD and is protected under U.S. and international copyright
|
||||
# and other intellectual property laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# AMD, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) AMD shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or AMD had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# AMD products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of AMD products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
#################
|
||||
#DEFAULT CLOCK CONSTRAINTS
|
||||
|
||||
############################################################
|
||||
# Clock Period Constraints #
|
||||
############################################################
|
||||
#create_clock -period 10.000 [get_ports clk_in1]
|
||||
|
||||
@@ -0,0 +1,220 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
// Date : Tue Jul 9 23:44:24 2024
|
||||
// Host : Viviana running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v
|
||||
// Design : phase_locked_loop
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7a35tfgg484-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* NotValidForBitStream *)
|
||||
module phase_locked_loop
|
||||
(clk_out1,
|
||||
reset,
|
||||
locked,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
input reset;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
(* IBUF_LOW_PWR *) wire clk_in1;
|
||||
wire clk_out1;
|
||||
wire locked;
|
||||
wire reset;
|
||||
|
||||
phase_locked_loop_clk_wiz inst
|
||||
(.clk_in1(clk_in1),
|
||||
.clk_out1(clk_out1),
|
||||
.locked(locked),
|
||||
.reset(reset));
|
||||
endmodule
|
||||
|
||||
module phase_locked_loop_clk_wiz
|
||||
(clk_out1,
|
||||
reset,
|
||||
locked,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
input reset;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
wire clk_in1;
|
||||
wire clk_in1_phase_locked_loop;
|
||||
wire clk_out1;
|
||||
wire clk_out1_phase_locked_loop;
|
||||
wire clkfbout_buf_phase_locked_loop;
|
||||
wire clkfbout_phase_locked_loop;
|
||||
wire locked;
|
||||
wire reset;
|
||||
wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
|
||||
wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkf_buf
|
||||
(.I(clkfbout_phase_locked_loop),
|
||||
.O(clkfbout_buf_phase_locked_loop));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF #(
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
clkin1_ibufg
|
||||
(.I(clk_in1),
|
||||
.O(clk_in1_phase_locked_loop));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout1_buf
|
||||
(.I(clk_out1_phase_locked_loop),
|
||||
.O(clk_out1));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
PLLE2_ADV #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKFBOUT_MULT(41),
|
||||
.CLKFBOUT_PHASE(0.000000),
|
||||
.CLKIN1_PERIOD(10.000000),
|
||||
.CLKIN2_PERIOD(0.000000),
|
||||
.CLKOUT0_DIVIDE(82),
|
||||
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT0_PHASE(0.000000),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT1_PHASE(0.000000),
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT2_PHASE(0.000000),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT3_PHASE(0.000000),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT4_PHASE(0.000000),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT5_PHASE(0.000000),
|
||||
.COMPENSATION("ZHOLD"),
|
||||
.DIVCLK_DIVIDE(5),
|
||||
.IS_CLKINSEL_INVERTED(1'b0),
|
||||
.IS_PWRDWN_INVERTED(1'b0),
|
||||
.IS_RST_INVERTED(1'b0),
|
||||
.REF_JITTER1(0.010000),
|
||||
.REF_JITTER2(0.010000),
|
||||
.STARTUP_WAIT("FALSE"))
|
||||
plle2_adv_inst
|
||||
(.CLKFBIN(clkfbout_buf_phase_locked_loop),
|
||||
.CLKFBOUT(clkfbout_phase_locked_loop),
|
||||
.CLKIN1(clk_in1_phase_locked_loop),
|
||||
.CLKIN2(1'b0),
|
||||
.CLKINSEL(1'b1),
|
||||
.CLKOUT0(clk_out1_phase_locked_loop),
|
||||
.CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
|
||||
.CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
|
||||
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
|
||||
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
|
||||
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
|
||||
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DCLK(1'b0),
|
||||
.DEN(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
|
||||
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
|
||||
.DWE(1'b0),
|
||||
.LOCKED(locked),
|
||||
.PWRDWN(1'b0),
|
||||
.RST(reset));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
@@ -0,0 +1,24 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
// Date : Tue Jul 9 23:44:24 2024
|
||||
// Host : Viviana running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
|
||||
// Design : phase_locked_loop
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a35tfgg484-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module phase_locked_loop(clk_out1, reset, locked, clk_in1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
|
||||
/* synthesis syn_force_seq_prim="clk_out1" */;
|
||||
output clk_out1 /* synthesis syn_isclock = 1 */;
|
||||
input reset;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
endmodule
|
||||
Reference in New Issue
Block a user