Fix lui RegWriteDstSrc
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@@ -9,6 +9,7 @@ module CPU (
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// first, we split the clock
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wire clk;
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phase_locked_loop pll (
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.reset(hardware_reset),
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.clk_in1 (hardware_clk),
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.clk_out1(clk),
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.locked(clock_locked)
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@@ -208,7 +209,7 @@ module CPU (
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.register_write_addr(WB_register_write_address)
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);
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DataMemory data_memory (
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DataMemory #(.START_ADDRESS(32'h40000000)) data_memory (
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.clk(clk),
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.reset(reset),
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.address(MEM_data_memory_address),
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@@ -67,7 +67,7 @@ module ControlUnit (
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assign register_write_destination_source = (opcode == 6'h23 || opcode == 6'h8 ||
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opcode == 6'h9 || opcode == 6'hc ||
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opcode == 6'ha || opcode == 6'hb ||
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(opcode == 6'h0 &&
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opcode == 6'hf || (opcode == 6'h0 &&
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(funct == 6'h0 || funct == 6'h2 ||
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funct == 6'h3))) ? 0 : 1;
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@@ -5,12 +5,13 @@ module InstructionMemory (
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output reg [31:0] instruction
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);
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always @(*) begin
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always @(*) begin
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case (address[31:2])
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20'd0: instruction <= 32'h20210001;
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20'd10: instruction <= 32'h08000000;
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20'd0: instruction <= 32'h3c104000;
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20'd6: instruction <= 32'h2011000a;
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20'd11: instruction <= 32'hae11000f;
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default: instruction <= 32'h00000000;
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endcase
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end
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end
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endmodule
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@@ -49,7 +49,7 @@ module MemoryAccess (
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// .write_data(memory_write_data_include_forward),
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// .read_data(memory_read_data)
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// );
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assign data_memory = MEM_memory_write;
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assign data_memory_write = MEM_memory_write;
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assign data_memory_address = MEM_ALU_result;
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assign data_memory_write_data = (MEM_write_data_source == 1'b0) ?
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MEM_memory_write_data : WB_forwarded_data;
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@@ -60,7 +60,7 @@
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
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<Option Name="WTXSimLaunchSim" Val="68"/>
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<Option Name="WTXSimLaunchSim" Val="104"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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