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Basic addi works

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un-lock-able
2024-07-10 15:58:01 +08:00
parent 07e6545d2a
commit 4b5dc5dc1b
14 changed files with 221 additions and 159 deletions
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BIN
PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb
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166
PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/obj/xsim_2.c
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PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
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8
PipelineProcessor.srcs/sim_1/new/test_cpu.v
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@@ -13,8 +13,14 @@ module test_cpu ();
CPU cpu(
.hardware_clk(sim_clk),
.reset(reset),
.hardware_reset(reset),
.clock_locked(clk_locked),
.bcd_control(bcd_control)
);
initial begin
reset = 1;
#30;
reset = 0;
end
endmodule

21
PipelineProcessor.srcs/sources_1/new/CPU.v
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@@ -1,7 +1,7 @@
`timescale 1ns / 1ps
module CPU (
input hardware_clk,
input reset,
input hardware_reset,
output clock_locked,
output [11:0] bcd_control
);
@@ -14,9 +14,12 @@ module CPU (
.locked(clock_locked)
);
wire reset;
assign reset = hardware_reset || ~clock_locked;
// Out of IF
wire IF_fetched_instruction;
wire IF_PC_plus_4;
wire [31:0] IF_fetched_instruction;
wire [31:0] IF_PC_plus_4;
// Out of ID
wire [1:0] ID_PC_jump;
@@ -89,6 +92,7 @@ module CPU (
InstFetch instruction_fetch (
.clk(clk),
.reset(reset),
.branch_target(EX_branch_target),
.jump_target(ID_jump_target),
.jump_register_target(ID_jump_register_target),
@@ -101,12 +105,13 @@ module CPU (
InstDecode instruction_decode (
.clk(clk),
.reset(reset),
.prev_fetched_instruction(IF_fetched_instruction),
.prev_PC_plus_4(IF_PC_plus_4),
.IFIDSrc(hazard_IFID_source),
.WB_write_enable(WB_write_enable),
.WB_write_address(WB_write_address),
.WB_write_data(WB_write_data),
.WB_write_enable(WB_register_write),
.WB_write_address(WB_register_write_address),
.WB_write_data(WB_register_write_data),
.PC_jump(ID_PC_jump),
.jump_target(ID_jump_target),
.jump_register_target(ID_jump_register_target),
@@ -131,6 +136,7 @@ module CPU (
Execution execution (
.clk(clk),
.reset(reset),
.prev_is_branch(ID_is_branch),
.prev_WB_source(ID_WB_source),
.prev_memory_write(ID_memory_write),
@@ -166,6 +172,7 @@ module CPU (
MemoryAccess memory_access (
.clk(clk),
.reset(reset),
.prev_register_write(EX_register_write),
.prev_WB_source(EX_WB_source),
.prev_memory_write(EX_memory_write),
@@ -190,6 +197,7 @@ module CPU (
WriteBack write_back (
.clk(clk),
.reset(reset),
.prev_register_write(MEM_register_write),
.prev_WB_source(MEM_WB_source),
.prev_memory_read_data(MEM_memory_read_data),
@@ -202,6 +210,7 @@ module CPU (
DataMemory data_memory (
.clk(clk),
.reset(reset),
.address(MEM_data_memory_address),
.write_enable(MEM_data_memory_write),
.write_data(MEM_data_memory_write_data),

23
PipelineProcessor.srcs/sources_1/new/DataMemory.v
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@@ -2,6 +2,7 @@
module DataMemory (
input clk,
input reset,
input [31:0] address,
input write_enable,
input [31:0] write_data,
@@ -13,12 +14,26 @@ module DataMemory (
reg [31:0] memory_data[MEM_SIZE + START_ADDRESS - 1:START_ADDRESS];
assign bcd_hardwire = memory_data[START_ADDRESS + 4];
assign bcd_hardwire = memory_data[START_ADDRESS+4];
integer i;
initial begin
for (i = START_ADDRESS; i < MEM_SIZE + START_ADDRESS; i = i + 1) begin
memory_data[i] <= 32'h00000000;
end
end
always @(posedge clk) begin
if (write_enable) begin
memory_data[address] <= write_data;
if (reset) begin
for (i = START_ADDRESS; i < MEM_SIZE + START_ADDRESS; i = i + 1) begin
memory_data[i] <= 32'h00000000;
end
end else begin
if (write_enable) begin
memory_data[address] <= write_data;
end
read_data <= memory_data[address];
end
read_data <= memory_data[address];
end
endmodule

3
PipelineProcessor.srcs/sources_1/new/Execution.v
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@@ -1,6 +1,7 @@
`timescale 1ns / 1ps
module Execution (
input clk,
input reset,
// From prev stage
input prev_is_branch,
input prev_WB_source,
@@ -96,7 +97,7 @@ module Execution (
assign rt_address = EX_rt_address;
always @(posedge clk) begin
if (IDEXSrc == 1'b1) begin
if (IDEXSrc == 1'b1 || reset == 1'b1) begin
EX_register_write <= 1'b0;
EX_WB_source <= 1'b0;
EX_memory_write <= 1'b0;

47
PipelineProcessor.srcs/sources_1/new/InstDecode.v
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@@ -1,6 +1,7 @@
`timescale 1ns / 1ps
module InstDecode (
input clk,
input reset,
// From prev stage
input [31:0] prev_fetched_instruction,
input [31:0] prev_PC_plus_4,
@@ -65,7 +66,7 @@ module InstDecode (
// Signals to connect from control unit to register file and immediate extend unit
wire write_ra;
wire ra_addr_source;
wire extendop;
wire [1:0] extendop;
ControlUnit control_unit (
.opcode(opcode),
@@ -93,6 +94,7 @@ module InstDecode (
RegisterFile register_file (
.clk(clk),
.reset(reset),
.read_addr1(rs),
.read_addr2(rt),
.write_enable(WB_write_enable),
@@ -108,31 +110,36 @@ module InstDecode (
assign register_file_read_A = RF_read_A_out;
assign jump_register_target = RF_read_A_out;
ImmediateExtender immediate_extender(
ImmediateExtender immediate_extender (
.immediate(immediate),
.extendop(extendop),
.extended_immediate(extended_immediate)
);
always @(posedge clk) begin
case (IFIDSrc)
2'b00: begin
IFID_instruction <= prev_fetched_instruction;
IFID_PC_plus_4 <= prev_PC_plus_4;
end
2'b01: begin
IFID_instruction <= 32'h00000000;
IFID_PC_plus_4 <= 32'h00000000;
end
2'b10: begin
IFID_instruction <= IFID_instruction;
IFID_PC_plus_4 <= IFID_PC_plus_4;
end
default: begin
IFID_instruction <= 32'h00000000;
IFID_PC_plus_4 <= 32'h00000000;
end
endcase
if (reset) begin
IFID_instruction <= 32'h00000000;
IFID_PC_plus_4 <= 32'h00000000;
end else begin
case (IFIDSrc)
2'b00: begin
IFID_instruction <= prev_fetched_instruction;
IFID_PC_plus_4 <= prev_PC_plus_4;
end
2'b01: begin
IFID_instruction <= 32'h00000000;
IFID_PC_plus_4 <= 32'h00000000;
end
2'b10: begin
IFID_instruction <= IFID_instruction;
IFID_PC_plus_4 <= IFID_PC_plus_4;
end
default: begin
IFID_instruction <= 32'h00000000;
IFID_PC_plus_4 <= 32'h00000000;
end
endcase
end
end
endmodule

28
PipelineProcessor.srcs/sources_1/new/InstFetch.v
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@@ -1,6 +1,7 @@
`timescale 1ns / 1ps
module InstFetch (
input clk,
input reset,
input [31:0] branch_target,
input [31:0] jump_target,
input [31:0] jump_register_target,
@@ -17,22 +18,27 @@ module InstFetch (
.instruction(fetched_instruction)
);
wire adder_out;
wire [31:0] adder_out;
assign adder_out = PC + 4;
assign PC_plus_4 = adder_out;
always @(posedge clk) begin
if (need_stall) begin
PC <= PC;
if (reset) begin
PC <= 32'h00000000;
end else begin
if (PC_branch) begin
PC <= branch_target;
if (need_stall) begin
PC <= PC;
end else begin
case (PC_jump)
2'b00: PC <= adder_out;
2'b01: PC <= jump_target;
2'b10: PC <= jump_register_target;
default: PC <= adder_out;
endcase
if (PC_branch) begin
PC <= branch_target;
end else begin
case (PC_jump)
2'b00: PC <= adder_out;
2'b01: PC <= jump_target;
2'b10: PC <= jump_register_target;
default: PC <= adder_out;
endcase
end
end
end
end

2
PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
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@@ -8,7 +8,7 @@ module InstructionMemory (
always @(*) begin
case (address[31:2])
20'd0: instruction <= 32'h20210001;
20'd1: instruction <= 32'h08000000;
20'd10: instruction <= 32'h08000000;
default: instruction <= 32'h00000000;
endcase
end

25
PipelineProcessor.srcs/sources_1/new/MemoryAccess.v
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@@ -1,6 +1,7 @@
`timescale 1ns / 1ps
module MemoryAccess (
input clk,
input reset,
// From prev stage
input prev_register_write,
input prev_WB_source,
@@ -61,12 +62,22 @@ module MemoryAccess (
assign register_write_destination = MEM_register_write_destination;
always @(posedge clk) begin
MEM_register_write <= prev_register_write;
MEM_WB_source <= prev_WB_source;
MEM_memory_write <= prev_memory_write;
MEM_ALU_result <= prev_ALU_result;
MEM_memory_write_data <= prev_memory_write_data;
MEM_register_write_destination <= prev_register_write_destination;
MEM_rt_address <= prev_rt_address;
if (reset) begin
MEM_register_write <= 1'b0;
MEM_WB_source <= 1'b0;
MEM_memory_write <= 1'b0;
MEM_ALU_result <= 32'h00000000;
MEM_memory_write_data <= 32'h00000000;
MEM_register_write_destination <= 5'b00000;
MEM_rt_address <= 5'b00000;
end else begin
MEM_register_write <= prev_register_write;
MEM_WB_source <= prev_WB_source;
MEM_memory_write <= prev_memory_write;
MEM_ALU_result <= prev_ALU_result;
MEM_memory_write_data <= prev_memory_write_data;
MEM_register_write_destination <= prev_register_write_destination;
MEM_rt_address <= prev_rt_address;
end
end
endmodule

36
PipelineProcessor.srcs/sources_1/new/RegisterFile.v
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@@ -2,6 +2,7 @@
module RegisterFile (
input clk,
input reset,
input [4:0] read_addr1,
input [4:0] read_addr2,
input write_enable,
@@ -14,7 +15,8 @@ module RegisterFile (
output [31:0] read_output2
);
reg [31:0] registers[31:1];
reg [31:0] registers[1:31];
integer i;
assign read_output1 = (read_addr1 == 5'b00000) ? 32'h00000000 :
(read_addr1 == write_ra_addr) ? write_ra_data :
@@ -24,22 +26,34 @@ module RegisterFile (
(read_addr2 == write_ra_addr) ? write_ra_data :
(read_addr2 == write_addr) ? write_data : registers[read_addr2];
initial begin
for (i = 1; i < 32; i = i + 1) begin
registers[i] <= 32'h00000000;
end
end
always @(posedge clk) begin
if (write_addr == write_ra_addr) begin
if (write_ra) begin
registers[write_ra_addr] <= write_ra_data;
if (reset) begin
for (i = 1; i < 32; i = i + 1) begin
registers[i] <= 32'h00000000;
end
end else begin
if (write_addr == write_ra_addr) begin
if (write_ra) begin
registers[write_ra_addr] <= write_ra_data;
end else begin
if (write_enable) begin
registers[write_addr] <= write_data;
end
end
end else begin
if (write_ra) begin
registers[write_ra_addr] <= write_ra_data;
end
if (write_enable) begin
registers[write_addr] <= write_data;
end
end
end else begin
if (write_ra) begin
registers[write_ra_addr] <= write_ra_data;
end
if (write_enable) begin
registers[write_addr] <= write_data;
end
end
end

19
PipelineProcessor.srcs/sources_1/new/WriteBack.v
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@@ -1,6 +1,7 @@
`timescale 1ns / 1ps
module WriteBack (
input clk,
input reset,
// From prev stage
input prev_register_write,
input prev_WB_source,
@@ -24,10 +25,18 @@ module WriteBack (
assign register_write_addr = WB_register_write_destination;
always @(posedge clk) begin
WB_register_write <= prev_register_write;
WB_WB_source <= prev_WB_source;
WB_memory_read_data <= prev_memory_read_data;
WB_ALU_result <= prev_ALU_result;
WB_register_write_destination <= prev_register_write_destination;
if (reset) begin
WB_register_write <= 1'b0;
WB_WB_source <= 1'b0;
WB_memory_read_data <= 32'h00000000;
WB_ALU_result <= 32'h00000000;
WB_register_write_destination <= 5'b00000;
end else begin
WB_register_write <= prev_register_write;
WB_WB_source <= prev_WB_source;
WB_memory_read_data <= prev_memory_read_data;
WB_ALU_result <= prev_ALU_result;
WB_register_write_destination <= prev_register_write_destination;
end
end
endmodule

2
PipelineProcessor.xpr
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@@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="17"/>
<Option Name="WTXSimLaunchSim" Val="68"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>