Display given number
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>ipcache</spirit:library>
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<spirit:name>11b3438a8319906c</spirit:name>
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<spirit:version>0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>phase_locked_loop</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
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<spirit:configurableElementValues>
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||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">203.457</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">155.540</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">50.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">phase_locked_loop</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">17</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">17</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a35t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fgg484</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEELABORATESCRC">e6a05ff8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">11b3438a8319906c</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">phase_locked_loop</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 4016217 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">401ad827</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">30</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
@@ -0,0 +1,220 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
// Date : Thu Jul 11 13:35:54 2024
|
||||
// Host : Viviana running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_sim_netlist.v
|
||||
// Design : phase_locked_loop
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7a35tfgg484-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* NotValidForBitStream *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||
(clk_out1,
|
||||
reset,
|
||||
locked,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
input reset;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
(* IBUF_LOW_PWR *) wire clk_in1;
|
||||
wire clk_out1;
|
||||
wire locked;
|
||||
wire reset;
|
||||
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_phase_locked_loop_clk_wiz inst
|
||||
(.clk_in1(clk_in1),
|
||||
.clk_out1(clk_out1),
|
||||
.locked(locked),
|
||||
.reset(reset));
|
||||
endmodule
|
||||
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_phase_locked_loop_clk_wiz
|
||||
(clk_out1,
|
||||
reset,
|
||||
locked,
|
||||
clk_in1);
|
||||
output clk_out1;
|
||||
input reset;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
|
||||
wire clk_in1;
|
||||
wire clk_in1_phase_locked_loop;
|
||||
wire clk_out1;
|
||||
wire clk_out1_phase_locked_loop;
|
||||
wire clkfbout_buf_phase_locked_loop;
|
||||
wire clkfbout_phase_locked_loop;
|
||||
wire locked;
|
||||
wire reset;
|
||||
wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
|
||||
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
|
||||
wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
|
||||
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkf_buf
|
||||
(.I(clkfbout_phase_locked_loop),
|
||||
.O(clkfbout_buf_phase_locked_loop));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
IBUF #(
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
clkin1_ibufg
|
||||
(.I(clk_in1),
|
||||
.O(clk_in1_phase_locked_loop));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
BUFG clkout1_buf
|
||||
(.I(clk_out1_phase_locked_loop),
|
||||
.O(clk_out1));
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
PLLE2_ADV #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKFBOUT_MULT(17),
|
||||
.CLKFBOUT_PHASE(0.000000),
|
||||
.CLKIN1_PERIOD(10.000000),
|
||||
.CLKIN2_PERIOD(0.000000),
|
||||
.CLKOUT0_DIVIDE(17),
|
||||
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT0_PHASE(0.000000),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT1_PHASE(0.000000),
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT2_PHASE(0.000000),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT3_PHASE(0.000000),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT4_PHASE(0.000000),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT5_PHASE(0.000000),
|
||||
.COMPENSATION("ZHOLD"),
|
||||
.DIVCLK_DIVIDE(2),
|
||||
.IS_CLKINSEL_INVERTED(1'b0),
|
||||
.IS_PWRDWN_INVERTED(1'b0),
|
||||
.IS_RST_INVERTED(1'b0),
|
||||
.REF_JITTER1(0.010000),
|
||||
.REF_JITTER2(0.010000),
|
||||
.STARTUP_WAIT("FALSE"))
|
||||
plle2_adv_inst
|
||||
(.CLKFBIN(clkfbout_buf_phase_locked_loop),
|
||||
.CLKFBOUT(clkfbout_phase_locked_loop),
|
||||
.CLKIN1(clk_in1_phase_locked_loop),
|
||||
.CLKIN2(1'b0),
|
||||
.CLKINSEL(1'b1),
|
||||
.CLKOUT0(clk_out1_phase_locked_loop),
|
||||
.CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
|
||||
.CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
|
||||
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
|
||||
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
|
||||
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
|
||||
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DCLK(1'b0),
|
||||
.DEN(1'b0),
|
||||
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
|
||||
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
|
||||
.DWE(1'b0),
|
||||
.LOCKED(locked),
|
||||
.PWRDWN(1'b0),
|
||||
.RST(reset));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
@@ -0,0 +1,24 @@
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
// Date : Thu Jul 11 13:35:54 2024
|
||||
// Host : Viviana running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_stub.v
|
||||
// Design : phase_locked_loop
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a35tfgg484-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, reset, locked, clk_in1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
|
||||
/* synthesis syn_force_seq_prim="clk_out1" */;
|
||||
output clk_out1 /* synthesis syn_isclock = 1 */;
|
||||
input reset;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
endmodule
|
||||
Binary file not shown.
@@ -53,7 +53,7 @@
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1__10.00000______0.000______50.0______446.763____313.282
|
||||
// clk_out1__50.00000______0.000______50.0______203.457____155.540
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
|
||||
@@ -53,7 +53,7 @@
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1__10.00000______0.000______50.0______446.763____313.282
|
||||
// clk_out1__50.00000______0.000______50.0______203.457____155.540
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
@@ -119,10 +119,10 @@ wire clk_in2_phase_locked_loop;
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (5),
|
||||
.CLKFBOUT_MULT (41),
|
||||
.DIVCLK_DIVIDE (2),
|
||||
.CLKFBOUT_MULT (17),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKOUT0_DIVIDE (82),
|
||||
.CLKOUT0_DIVIDE (17),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKIN1_PERIOD (10.000))
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
// Date : Tue Jul 9 23:44:24 2024
|
||||
// Date : Thu Jul 11 13:35:55 2024
|
||||
// Host : Viviana running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v
|
||||
@@ -82,11 +82,11 @@ module phase_locked_loop_clk_wiz
|
||||
(* BOX_TYPE = "PRIMITIVE" *)
|
||||
PLLE2_ADV #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKFBOUT_MULT(41),
|
||||
.CLKFBOUT_MULT(17),
|
||||
.CLKFBOUT_PHASE(0.000000),
|
||||
.CLKIN1_PERIOD(10.000000),
|
||||
.CLKIN2_PERIOD(0.000000),
|
||||
.CLKOUT0_DIVIDE(82),
|
||||
.CLKOUT0_DIVIDE(17),
|
||||
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT0_PHASE(0.000000),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
@@ -105,7 +105,7 @@ module phase_locked_loop_clk_wiz
|
||||
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||
.CLKOUT5_PHASE(0.000000),
|
||||
.COMPENSATION("ZHOLD"),
|
||||
.DIVCLK_DIVIDE(5),
|
||||
.DIVCLK_DIVIDE(2),
|
||||
.IS_CLKINSEL_INVERTED(1'b0),
|
||||
.IS_PWRDWN_INVERTED(1'b0),
|
||||
.IS_RST_INVERTED(1'b0),
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
// Date : Tue Jul 9 23:44:24 2024
|
||||
// Date : Thu Jul 11 13:35:55 2024
|
||||
// Host : Viviana running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
// Date : Tue Jul 9 23:44:24 2024
|
||||
// Date : Thu Jul 11 13:35:55 2024
|
||||
// Host : Viviana running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
# run the exported script and how to fetch design source file details
|
||||
# from the file_info.txt file.
|
||||
#
|
||||
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||
# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
# run the exported script and how to fetch design source file details
|
||||
# from the file_info.txt file.
|
||||
#
|
||||
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||
# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
# run the exported script and how to fetch design source file details
|
||||
# from the file_info.txt file.
|
||||
#
|
||||
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||
# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
# run the exported script and how to fetch design source file details
|
||||
# from the file_info.txt file.
|
||||
#
|
||||
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||
# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
# run the exported script and how to fetch design source file details
|
||||
# from the file_info.txt file.
|
||||
#
|
||||
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||
# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
# run the exported script and how to fetch design source file details
|
||||
# from the file_info.txt file.
|
||||
#
|
||||
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||
# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
# run the exported script and how to fetch design source file details
|
||||
# from the file_info.txt file.
|
||||
#
|
||||
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||
# Generated by export_simulation on Thu Jul 11 13:35:21 +0800 2024
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
334
PipelineProcessor.runs/impl_1/CPU.tcl
Normal file
334
PipelineProcessor.runs/impl_1/CPU.tcl
Normal file
@@ -0,0 +1,334 @@
|
||||
#
|
||||
# Report generation script generated by Vivado
|
||||
#
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
namespace eval ::optrace {
|
||||
variable script "D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.tcl"
|
||||
variable category "vivado_impl"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc start_step { step } {
|
||||
set stopFile ".stop.rst"
|
||||
if {[file isfile .stop.rst]} {
|
||||
puts ""
|
||||
puts "*** Halting run - EA reset detected ***"
|
||||
puts ""
|
||||
puts ""
|
||||
return -code error
|
||||
}
|
||||
set beginFile ".$step.begin.rst"
|
||||
set platform "$::tcl_platform(platform)"
|
||||
set user "$::tcl_platform(user)"
|
||||
set pid [pid]
|
||||
set host ""
|
||||
if { [string equal $platform unix] } {
|
||||
if { [info exist ::env(HOSTNAME)] } {
|
||||
set host $::env(HOSTNAME)
|
||||
} elseif { [info exist ::env(HOST)] } {
|
||||
set host $::env(HOST)
|
||||
}
|
||||
} else {
|
||||
if { [info exist ::env(COMPUTERNAME)] } {
|
||||
set host $::env(COMPUTERNAME)
|
||||
}
|
||||
}
|
||||
set ch [open $beginFile w]
|
||||
puts $ch "<?xml version=\"1.0\"?>"
|
||||
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
|
||||
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
|
||||
puts $ch " </Process>"
|
||||
puts $ch "</ProcessHandle>"
|
||||
close $ch
|
||||
}
|
||||
|
||||
proc end_step { step } {
|
||||
set endFile ".$step.end.rst"
|
||||
set ch [open $endFile w]
|
||||
close $ch
|
||||
}
|
||||
|
||||
proc step_failed { step } {
|
||||
set endFile ".$step.error.rst"
|
||||
set ch [open $endFile w]
|
||||
close $ch
|
||||
OPTRACE "impl_1" END { }
|
||||
}
|
||||
|
||||
|
||||
OPTRACE "impl_1" START { ROLLUP_1 }
|
||||
OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
|
||||
start_step init_design
|
||||
set ACTIVE_STEP init_design
|
||||
set rc [catch {
|
||||
create_msg_db init_design.pb
|
||||
set_param chipscope.maxJobs 5
|
||||
set_param xicom.use_bs_reader 1
|
||||
set_param runs.launchOptions { -jobs 20 }
|
||||
OPTRACE "create in-memory project" START { }
|
||||
create_project -in_memory -part xc7a35tfgg484-1
|
||||
set_property design_mode GateLvl [current_fileset]
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
OPTRACE "create in-memory project" END { }
|
||||
OPTRACE "set parameters" START { }
|
||||
set_property webtalk.parent_dir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.cache/wt [current_project]
|
||||
set_property parent.project_path D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.xpr [current_project]
|
||||
set_property ip_output_repo D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
set_property XPM_LIBRARIES XPM_CDC [current_project]
|
||||
OPTRACE "set parameters" END { }
|
||||
OPTRACE "add files" START { }
|
||||
add_files -quiet D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.dcp
|
||||
read_ip -quiet D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
|
||||
OPTRACE "read constraints: implementation" START { }
|
||||
read_xdc D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc
|
||||
OPTRACE "read constraints: implementation" END { }
|
||||
OPTRACE "read constraints: implementation_pre" START { }
|
||||
OPTRACE "read constraints: implementation_pre" END { }
|
||||
OPTRACE "add files" END { }
|
||||
OPTRACE "link_design" START { }
|
||||
link_design -top CPU -part xc7a35tfgg484-1
|
||||
OPTRACE "link_design" END { }
|
||||
OPTRACE "gray box cells" START { }
|
||||
OPTRACE "gray box cells" END { }
|
||||
OPTRACE "init_design_reports" START { REPORT }
|
||||
OPTRACE "init_design_reports" END { }
|
||||
OPTRACE "init_design_write_hwdef" START { }
|
||||
OPTRACE "init_design_write_hwdef" END { }
|
||||
close_msg_db -file init_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed init_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step init_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Init Design" END { }
|
||||
OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
|
||||
start_step opt_design
|
||||
set ACTIVE_STEP opt_design
|
||||
set rc [catch {
|
||||
create_msg_db opt_design.pb
|
||||
OPTRACE "read constraints: opt_design" START { }
|
||||
OPTRACE "read constraints: opt_design" END { }
|
||||
OPTRACE "opt_design" START { }
|
||||
opt_design
|
||||
OPTRACE "opt_design" END { }
|
||||
OPTRACE "read constraints: opt_design_post" START { }
|
||||
OPTRACE "read constraints: opt_design_post" END { }
|
||||
OPTRACE "opt_design reports" START { REPORT }
|
||||
create_report "impl_1_opt_report_drc_0" "report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx"
|
||||
OPTRACE "opt_design reports" END { }
|
||||
OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force CPU_opt.dcp
|
||||
OPTRACE "Opt Design: write_checkpoint" END { }
|
||||
close_msg_db -file opt_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed opt_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step opt_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Opt Design" END { }
|
||||
OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
|
||||
start_step place_design
|
||||
set ACTIVE_STEP place_design
|
||||
set rc [catch {
|
||||
create_msg_db place_design.pb
|
||||
OPTRACE "read constraints: place_design" START { }
|
||||
OPTRACE "read constraints: place_design" END { }
|
||||
if { [llength [get_debug_cores -quiet] ] > 0 } {
|
||||
OPTRACE "implement_debug_core" START { }
|
||||
implement_debug_core
|
||||
OPTRACE "implement_debug_core" END { }
|
||||
}
|
||||
OPTRACE "place_design" START { }
|
||||
place_design
|
||||
OPTRACE "place_design" END { }
|
||||
OPTRACE "read constraints: place_design_post" START { }
|
||||
OPTRACE "read constraints: place_design_post" END { }
|
||||
OPTRACE "place_design reports" START { REPORT }
|
||||
create_report "impl_1_place_report_io_0" "report_io -file CPU_io_placed.rpt"
|
||||
create_report "impl_1_place_report_utilization_0" "report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb"
|
||||
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CPU_control_sets_placed.rpt"
|
||||
OPTRACE "place_design reports" END { }
|
||||
OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force CPU_placed.dcp
|
||||
OPTRACE "Place Design: write_checkpoint" END { }
|
||||
close_msg_db -file place_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed place_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step place_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Place Design" END { }
|
||||
OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
|
||||
start_step phys_opt_design
|
||||
set ACTIVE_STEP phys_opt_design
|
||||
set rc [catch {
|
||||
create_msg_db phys_opt_design.pb
|
||||
OPTRACE "read constraints: phys_opt_design" START { }
|
||||
OPTRACE "read constraints: phys_opt_design" END { }
|
||||
OPTRACE "phys_opt_design" START { }
|
||||
phys_opt_design
|
||||
OPTRACE "phys_opt_design" END { }
|
||||
OPTRACE "read constraints: phys_opt_design_post" START { }
|
||||
OPTRACE "read constraints: phys_opt_design_post" END { }
|
||||
OPTRACE "phys_opt_design report" START { REPORT }
|
||||
OPTRACE "phys_opt_design report" END { }
|
||||
OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force CPU_physopt.dcp
|
||||
OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
|
||||
close_msg_db -file phys_opt_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed phys_opt_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step phys_opt_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Physical Opt Design" END { }
|
||||
OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
|
||||
start_step route_design
|
||||
set ACTIVE_STEP route_design
|
||||
set rc [catch {
|
||||
create_msg_db route_design.pb
|
||||
OPTRACE "read constraints: route_design" START { }
|
||||
OPTRACE "read constraints: route_design" END { }
|
||||
OPTRACE "route_design" START { }
|
||||
route_design
|
||||
OPTRACE "route_design" END { }
|
||||
OPTRACE "read constraints: route_design_post" START { }
|
||||
OPTRACE "read constraints: route_design_post" END { }
|
||||
OPTRACE "route_design reports" START { REPORT }
|
||||
create_report "impl_1_route_report_drc_0" "report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_methodology_0" "report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_power_0" "report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx"
|
||||
create_report "impl_1_route_report_route_status_0" "report_route_status -file CPU_route_status.rpt -pb CPU_route_status.pb"
|
||||
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file CPU_timing_summary_routed.rpt -pb CPU_timing_summary_routed.pb -rpx CPU_timing_summary_routed.rpx -warn_on_violation "
|
||||
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CPU_incremental_reuse_routed.rpt"
|
||||
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CPU_clock_utilization_routed.rpt"
|
||||
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file CPU_bus_skew_routed.rpt -pb CPU_bus_skew_routed.pb -rpx CPU_bus_skew_routed.rpx"
|
||||
OPTRACE "route_design reports" END { }
|
||||
OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force CPU_routed.dcp
|
||||
OPTRACE "Route Design: write_checkpoint" END { }
|
||||
OPTRACE "route_design misc" START { }
|
||||
close_msg_db -file route_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
|
||||
OPTRACE "route_design write_checkpoint" END { }
|
||||
write_checkpoint -force CPU_routed_error.dcp
|
||||
step_failed route_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step route_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "route_design misc" END { }
|
||||
OPTRACE "Phase: Route Design" END { }
|
||||
OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
|
||||
OPTRACE "write_bitstream setup" START { }
|
||||
start_step write_bitstream
|
||||
set ACTIVE_STEP write_bitstream
|
||||
set rc [catch {
|
||||
create_msg_db write_bitstream.pb
|
||||
OPTRACE "read constraints: write_bitstream" START { }
|
||||
OPTRACE "read constraints: write_bitstream" END { }
|
||||
set_property XPM_LIBRARIES XPM_CDC [current_project]
|
||||
catch { write_mem_info -force -no_partial_mmi CPU.mmi }
|
||||
OPTRACE "write_bitstream setup" END { }
|
||||
OPTRACE "write_bitstream" START { }
|
||||
write_bitstream -force CPU.bit
|
||||
OPTRACE "write_bitstream" END { }
|
||||
OPTRACE "write_bitstream misc" START { }
|
||||
OPTRACE "read constraints: write_bitstream_post" START { }
|
||||
OPTRACE "read constraints: write_bitstream_post" END { }
|
||||
catch {write_debug_probes -quiet -force CPU}
|
||||
catch {file copy -force CPU.ltx debug_nets.ltx}
|
||||
close_msg_db -file write_bitstream.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed write_bitstream
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step write_bitstream
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "write_bitstream misc" END { }
|
||||
OPTRACE "Phase: Write Bitstream" END { }
|
||||
OPTRACE "impl_1" END { }
|
||||
755
PipelineProcessor.runs/impl_1/CPU.vdi
Normal file
755
PipelineProcessor.runs/impl_1/CPU.vdi
Normal file
@@ -0,0 +1,755 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Fri Jul 12 00:09:58 2024
|
||||
# Process ID: 29956
|
||||
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1
|
||||
# Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace
|
||||
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi
|
||||
# Journal file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1\vivado.jou
|
||||
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
|
||||
#-----------------------------------------------------------
|
||||
source CPU.tcl -notrace
|
||||
Command: link_design -top CPU -part xc7a35tfgg484-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Device 21-403] Loading part xc7a35tfgg484-1
|
||||
INFO: [Project 1-454] Reading design checkpoint 'd:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp' for cell 'pll'
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.109 . Memory (MB): peak = 915.172 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 3483 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc] for cell 'pll/inst'
|
||||
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc] for cell 'pll/inst'
|
||||
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst'
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54]
|
||||
INFO: [Timing 38-2] Deriving generated clocks [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54]
|
||||
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst'
|
||||
Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
|
||||
Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1598.852 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:10 . Memory (MB): peak = 1598.852 ; gain = 1123.434
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.571 . Memory (MB): peak = 1598.852 ; gain = 0.000
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Ending Cache Timing Information Task | Checksum: 19815f8ec
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1613.586 ; gain = 14.734
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Initialization
|
||||
|
||||
Phase 1.1 Core Generation And Design Setup
|
||||
Phase 1.1 Core Generation And Design Setup | Checksum: 19815f8ec
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
|
||||
Phase 1.2 Setup Constraints And Sort Netlist
|
||||
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 19815f8ec
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Phase 1 Initialization | Checksum: 19815f8ec
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
|
||||
Phase 2 Timer Update And Timing Data Collection
|
||||
|
||||
Phase 2.1 Timer Update
|
||||
Phase 2.1 Timer Update | Checksum: 19815f8ec
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.348 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Timing Data Collection
|
||||
Phase 2.2 Timing Data Collection | Checksum: 19815f8ec
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.363 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Phase 2 Timer Update And Timing Data Collection | Checksum: 19815f8ec
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.364 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
|
||||
Phase 3 Retarget
|
||||
INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 96 pins
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 3 Retarget | Checksum: 1563adde0
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.477 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Retarget | Checksum: 1563adde0
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 4 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 4 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 4 Constant propagation | Checksum: 2080e885b
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.545 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Constant propagation | Checksum: 2080e885b
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 5 Sweep
|
||||
Phase 5 Sweep | Checksum: 1bd034584
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.654 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Sweep | Checksum: 1bd034584
|
||||
INFO: [Opt 31-389] Phase Sweep created 12 cells and removed 0 cells
|
||||
|
||||
Phase 6 BUFG optimization
|
||||
Phase 6 BUFG optimization | Checksum: 1bd034584
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
BUFG optimization | Checksum: 1bd034584
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 7 Shift Register Optimization
|
||||
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
|
||||
Phase 7 Shift Register Optimization | Checksum: 1bd034584
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.756 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Shift Register Optimization | Checksum: 1bd034584
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 8 Post Processing Netlist
|
||||
Phase 8 Post Processing Netlist | Checksum: 1408d463e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.781 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Post Processing Netlist | Checksum: 1408d463e
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
|
||||
Phase 9 Finalization
|
||||
|
||||
Phase 9.1 Finalizing Design Cores and Updating Shapes
|
||||
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1e5497da9
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.927 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
|
||||
Phase 9.2 Verifying Netlist Connectivity
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Phase 9.2 Verifying Netlist Connectivity | Checksum: 1e5497da9
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.944 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Phase 9 Finalization | Checksum: 1e5497da9
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.945 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 4 | 1 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 12 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Ending Logic Optimization Task | Checksum: 1e5497da9
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.947 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
|
||||
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 1e5497da9
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 1e5497da9
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 1e5497da9
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
INFO: [runtcl-4] Executing : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx
|
||||
Command: report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Writing XDEF routing special nets.
|
||||
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_opt.dcp' has been generated.
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Starting Placer Task
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12a703c9e
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 9fe0ea66
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.883 . Memory (MB): peak = 1973.746 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: fc45f473
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: fc45f473
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
Phase 1 Placer Initialization | Checksum: fc45f473
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 1187634b5
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 2.2 Update Timing before SLR Path Opt
|
||||
Phase 2.2 Update Timing before SLR Path Opt | Checksum: b5540111
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 2.3 Post-Processing in Floorplanning
|
||||
Phase 2.3 Post-Processing in Floorplanning | Checksum: b5540111
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 2.4 Global Placement Core
|
||||
|
||||
Phase 2.4.1 UpdateTiming Before Physical Synthesis
|
||||
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 110aaba25
|
||||
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 2.4.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 101 LUT instances to create LUTNM shape
|
||||
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
|
||||
INFO: [Physopt 32-1138] End 1 Pass. Optimized 40 nets or LUTs. Breaked 0 LUT, combined 40 existing LUTs and moved 0 existing LUT
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2031.629 ; gain = 0.000
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| LUT Combining | 0 | 40 | 40 | 0 | 1 | 00:00:00 |
|
||||
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 40 | 40 | 0 | 4 | 00:00:00 |
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 16851cd1d
|
||||
|
||||
Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
Phase 2.4 Global Placement Core | Checksum: 168fd7ea9
|
||||
|
||||
Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
Phase 2 Global Placement | Checksum: 168fd7ea9
|
||||
|
||||
Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 12da8b661
|
||||
|
||||
Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25e8832a5
|
||||
|
||||
Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 221700b80
|
||||
|
||||
Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 171118896
|
||||
|
||||
Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 25d9dec9c
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:24 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 16e056078
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:24 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: e663db1e
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:24 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
Phase 3 Detail Placement | Checksum: e663db1e
|
||||
|
||||
Time (s): cpu = 00:00:10 ; elapsed = 00:00:24 . Memory (MB): peak = 2031.629 ; gain = 57.883
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 51088c1c
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
|
||||
Starting Physical Synthesis Task
|
||||
|
||||
Phase 1 Physical Synthesis Initialization
|
||||
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
|
||||
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=3.262 | TNS=0.000 |
|
||||
Phase 1 Physical Synthesis Initialization | Checksum: d85dca42
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.632 . Memory (MB): peak = 2077.414 ; gain = 14.797
|
||||
INFO: [Place 46-33] Processed net data_memory/reset, BUFG insertion was skipped due to placement/routing conflicts.
|
||||
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
|
||||
Ending Physical Synthesis Task | Checksum: d85dca42
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2079.488 ; gain = 16.871
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 51088c1c
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 2079.488 ; gain = 105.742
|
||||
|
||||
Phase 4.1.1.2 Post Placement Timing Optimization
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=3.262. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: ebcb0a71
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 2079.488 ; gain = 105.742
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 2079.488 ; gain = 105.742
|
||||
Phase 4.1 Post Commit Optimization | Checksum: ebcb0a71
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 2079.488 ; gain = 105.742
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: ebcb0a71
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
|
||||
Phase 4.3.1 Print Estimated Congestion
|
||||
INFO: [Place 30-612] Post-Placement Estimated Congestion
|
||||
____________________________________________________
|
||||
| | Global Congestion | Short Congestion |
|
||||
| Direction | Region Size | Region Size |
|
||||
|___________|___________________|___________________|
|
||||
| North| 2x2| 4x4|
|
||||
|___________|___________________|___________________|
|
||||
| South| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
| East| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
| West| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
|
||||
Phase 4.3.1 Print Estimated Congestion | Checksum: ebcb0a71
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742
|
||||
Phase 4.3 Placer Reporting | Checksum: ebcb0a71
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2079.488 ; gain = 0.000
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: dc7f2636
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742
|
||||
Ending Placer Task | Checksum: 0e38a4fc
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742
|
||||
66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
place_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 2079.488 ; gain = 105.742
|
||||
INFO: [runtcl-4] Executing : report_io -file CPU_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 2079.488 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 2079.488 ; gain = 0.000
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 2093.965 ; gain = 0.941
|
||||
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2093.965 ; gain = 0.941
|
||||
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2093.965 ; gain = 0.000
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2093.965 ; gain = 0.000
|
||||
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 2093.965 ; gain = 0.000
|
||||
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2093.965 ; gain = 0.000
|
||||
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2093.965 ; gain = 0.941
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_placed.dcp' has been generated.
|
||||
Command: phys_opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
|
||||
Starting Initial Update Timing Task
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2141.992 ; gain = 48.027
|
||||
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
|
||||
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
75 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
phys_opt_design completed successfully
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2167.289 ; gain = 7.023
|
||||
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2168.047 ; gain = 0.758
|
||||
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2168.047 ; gain = 0.000
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2168.047 ; gain = 0.000
|
||||
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 2168.047 ; gain = 0.000
|
||||
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2168.047 ; gain = 0.000
|
||||
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2168.047 ; gain = 7.781
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_physopt.dcp' has been generated.
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Checksum: PlaceDB: 4912218 ConstDB: 0 ShapeSum: 9a782e4 RouteDB: 0
|
||||
Post Restoration Checksum: NetGraph: 84c40091 | NumContArr: e6c0ef1d | Constraints: c2a8fa9d | Timing: c2a8fa9d
|
||||
Phase 1 Build RT Design | Checksum: 2f0d6e4e8
|
||||
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 2281.172 ; gain = 79.680
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Fix Topology Constraints
|
||||
Phase 2.1 Fix Topology Constraints | Checksum: 2f0d6e4e8
|
||||
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 2281.172 ; gain = 79.680
|
||||
|
||||
Phase 2.2 Pre Route Cleanup
|
||||
Phase 2.2 Pre Route Cleanup | Checksum: 2f0d6e4e8
|
||||
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 2281.172 ; gain = 79.680
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.3 Update Timing
|
||||
Phase 2.3 Update Timing | Checksum: 26b5a1b04
|
||||
|
||||
Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 2298.930 ; gain = 97.438
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.420 | TNS=0.000 | WHS=-0.094 | THS=-28.831|
|
||||
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0 %
|
||||
Global Horizontal Routing Utilization = 0 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 21870
|
||||
(Failed Nets is the sum of unrouted and partially routed nets)
|
||||
Number of Unrouted Nets = 21870
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 1e43d66bb
|
||||
|
||||
Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 2335.145 ; gain = 133.652
|
||||
|
||||
Phase 3 Initial Routing
|
||||
|
||||
Phase 3.1 Global Routing
|
||||
Phase 3.1 Global Routing | Checksum: 1e43d66bb
|
||||
|
||||
Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 2335.145 ; gain = 133.652
|
||||
|
||||
Phase 3.2 Initial Net Routing
|
||||
Phase 3.2 Initial Net Routing | Checksum: 2f8d11093
|
||||
|
||||
Time (s): cpu = 00:00:09 ; elapsed = 00:00:18 . Memory (MB): peak = 2339.484 ; gain = 137.992
|
||||
Phase 3 Initial Routing | Checksum: 2f8d11093
|
||||
|
||||
Time (s): cpu = 00:00:09 ; elapsed = 00:00:18 . Memory (MB): peak = 2339.484 ; gain = 137.992
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 3181
|
||||
Number of Nodes with overlaps = 190
|
||||
Number of Nodes with overlaps = 29
|
||||
Number of Nodes with overlaps = 7
|
||||
Number of Nodes with overlaps = 4
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.975 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 20c3fb659
|
||||
|
||||
Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 2344.332 ; gain = 142.840
|
||||
Phase 4 Rip-up And Reroute | Checksum: 20c3fb659
|
||||
|
||||
Time (s): cpu = 00:00:12 ; elapsed = 00:00:26 . Memory (MB): peak = 2344.332 ; gain = 142.840
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
|
||||
Phase 5.1.1 Update Timing
|
||||
Phase 5.1.1 Update Timing | Checksum: 2767bd1b6
|
||||
|
||||
Time (s): cpu = 00:00:12 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.054 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 5.1 Delay CleanUp | Checksum: 2767bd1b6
|
||||
|
||||
Time (s): cpu = 00:00:12 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 2767bd1b6
|
||||
|
||||
Time (s): cpu = 00:00:12 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 2767bd1b6
|
||||
|
||||
Time (s): cpu = 00:00:12 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 25eb86b71
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.054 | TNS=0.000 | WHS=0.045 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 1cfa691ef
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840
|
||||
Phase 6 Post Hold Fix | Checksum: 1cfa691ef
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 14.3318 %
|
||||
Global Horizontal Routing Utilization = 14.5862 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
(Failed Nets is the sum of unrouted and partially routed nets)
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 1cfa691ef
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 2344.332 ; gain = 142.840
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 1cfa691ef
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:27 . Memory (MB): peak = 2346.379 ; gain = 144.887
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 1bd3fc6ab
|
||||
|
||||
Time (s): cpu = 00:00:13 ; elapsed = 00:00:28 . Memory (MB): peak = 2346.379 ; gain = 144.887
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=3.054 | TNS=0.000 | WHS=0.045 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 1bd3fc6ab
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:29 . Memory (MB): peak = 2346.379 ; gain = 144.887
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Phase 11 Post-Route Event Processing
|
||||
Phase 11 Post-Route Event Processing | Checksum: c96e4205
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:29 . Memory (MB): peak = 2346.379 ; gain = 144.887
|
||||
Ending Routing Task | Checksum: c96e4205
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:30 . Memory (MB): peak = 2346.379 ; gain = 144.887
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
90 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:30 . Memory (MB): peak = 2346.379 ; gain = 178.332
|
||||
INFO: [runtcl-4] Executing : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
|
||||
Command: report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
report_methodology: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2414.371 ; gain = 67.992
|
||||
INFO: [runtcl-4] Executing : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
|
||||
Command: report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
100 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file CPU_route_status.rpt -pb CPU_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file CPU_timing_summary_routed.rpt -pb CPU_timing_summary_routed.pb -rpx CPU_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file CPU_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file CPU_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU_bus_skew_routed.rpt -pb CPU_bus_skew_routed.pb -rpx CPU_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 2476.137 ; gain = 3.938
|
||||
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2476.574 ; gain = 1.379
|
||||
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2476.574 ; gain = 0.000
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.170 . Memory (MB): peak = 2476.574 ; gain = 0.000
|
||||
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 2476.574 ; gain = 0.000
|
||||
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2476.574 ; gain = 0.000
|
||||
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2476.574 ; gain = 4.375
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_routed.dcp' has been generated.
|
||||
Command: write_bitstream -force CPU.bit
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
|
||||
Running DRC as a precondition to command write_bitstream
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
|
||||
|
||||
set_property CFGBVS value1 [current_design]
|
||||
#where value1 is either VCCO or GND
|
||||
|
||||
set_property CONFIG_VOLTAGE value2 [current_design]
|
||||
#where value2 is the voltage provided to configuration bank 0
|
||||
|
||||
Refer to the device configuration user guide for more information.
|
||||
WARNING: [DRC DPIP-1] Input pipelining: DSP execution/alu/result0 input execution/alu/result0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
WARNING: [DRC DPIP-1] Input pipelining: DSP execution/alu/result0 input execution/alu/result0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
WARNING: [DRC DPIP-1] Input pipelining: DSP execution/alu/result0__0 input execution/alu/result0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
WARNING: [DRC DPIP-1] Input pipelining: DSP execution/alu/result0__0 input execution/alu/result0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
WARNING: [DRC DPIP-1] Input pipelining: DSP execution/alu/result0__1 input execution/alu/result0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
WARNING: [DRC DPIP-1] Input pipelining: DSP execution/alu/result0__1 input execution/alu/result0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP execution/alu/result0 output execution/alu/result0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP execution/alu/result0__0 output execution/alu/result0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP execution/alu/result0__1 output execution/alu/result0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP execution/alu/result0 multiplier stage execution/alu/result0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP execution/alu/result0__0 multiplier stage execution/alu/result0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP execution/alu/result0__1 multiplier stage execution/alu/result0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 13 Warnings
|
||||
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
|
||||
Loading data files...
|
||||
Loading site data...
|
||||
Loading route data...
|
||||
Processing options...
|
||||
Creating bitmap...
|
||||
Creating bitstream...
|
||||
Writing bitstream ./CPU.bit...
|
||||
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||||
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
14 Infos, 13 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
write_bitstream completed successfully
|
||||
write_bitstream: Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 2944.602 ; gain = 468.027
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Jul 12 00:11:53 2024...
|
||||
BIN
PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.pb
Normal file
Binary file not shown.
16
PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt
Normal file
16
PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt
Normal file
@@ -0,0 +1,16 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
| Date : Fri Jul 12 00:11:40 2024
|
||||
| Host : Viviana running 64-bit major release (build 9200)
|
||||
| Command : report_bus_skew -warn_on_violation -file CPU_bus_skew_routed.rpt -pb CPU_bus_skew_routed.pb -rpx CPU_bus_skew_routed.rpx
|
||||
| Design : CPU
|
||||
| Device : 7a35t-fgg484
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Bus Skew Report
|
||||
|
||||
No bus skew constraints
|
||||
|
||||
244
PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt
Normal file
244
PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt
Normal file
@@ -0,0 +1,244 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
| Date : Fri Jul 12 00:11:40 2024
|
||||
| Host : Viviana running 64-bit major release (build 9200)
|
||||
| Command : report_clock_utilization -file CPU_clock_utilization_routed.rpt
|
||||
| Design : CPU
|
||||
| Device : 7a35t-fgg484
|
||||
| Speed File : -1 PRODUCTION 1.23 2018-06-13
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Utilization Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Clock Primitive Utilization
|
||||
2. Global Clock Resources
|
||||
3. Global Clock Source Details
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
5. Clock Regions : Global Clock Summary
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
7. Device Cell Placement Summary for Global Clock g1
|
||||
8. Clock Region Cell Placement per Global Clock: Region X0Y0
|
||||
9. Clock Region Cell Placement per Global Clock: Region X1Y0
|
||||
10. Clock Region Cell Placement per Global Clock: Region X0Y1
|
||||
11. Clock Region Cell Placement per Global Clock: Region X1Y1
|
||||
12. Clock Region Cell Placement per Global Clock: Region X0Y2
|
||||
13. Clock Region Cell Placement per Global Clock: Region X1Y2
|
||||
|
||||
1. Clock Primitive Utilization
|
||||
------------------------------
|
||||
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| Type | Used | Available | LOC | Clock Region | Pblock |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| BUFGCTRL | 2 | 32 | 0 | 0 | 0 |
|
||||
| BUFH | 0 | 72 | 0 | 0 | 0 |
|
||||
| BUFIO | 0 | 20 | 0 | 0 | 0 |
|
||||
| BUFMR | 0 | 10 | 0 | 0 | 0 |
|
||||
| BUFR | 0 | 20 | 0 | 0 | 0 |
|
||||
| MMCM | 0 | 5 | 0 | 0 | 0 |
|
||||
| PLL | 1 | 5 | 0 | 0 | 0 |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
|
||||
|
||||
2. Global Clock Resources
|
||||
-------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+
|
||||
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+
|
||||
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 6 | 18132 | 0 | 20.000 | clk_out1_phase_locked_loop | pll/inst/clkout1_buf/O | pll/inst/clk_out1 |
|
||||
| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 1 | 0 | 20.000 | clkfbout_phase_locked_loop | pll/inst/clkf_buf/O | pll/inst/clkfbout_buf_phase_locked_loop |
|
||||
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
|
||||
|
||||
3. Global Clock Source Details
|
||||
------------------------------
|
||||
|
||||
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+----------------------------+----------------------------------+-------------------------------------+
|
||||
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
|
||||
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+----------------------------+----------------------------------+-------------------------------------+
|
||||
| src0 | g0 | PLLE2_ADV/CLKOUT0 | None | PLLE2_ADV_X1Y0 | X1Y0 | 1 | 0 | 20.000 | clk_out1_phase_locked_loop | pll/inst/plle2_adv_inst/CLKOUT0 | pll/inst/clk_out1_phase_locked_loop |
|
||||
| src1 | g1 | PLLE2_ADV/CLKFBOUT | None | PLLE2_ADV_X1Y0 | X1Y0 | 1 | 0 | 20.000 | clkfbout_phase_locked_loop | pll/inst/plle2_adv_inst/CLKFBOUT | pll/inst/clkfbout_phase_locked_loop |
|
||||
+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+----------------------------+----------------------------------+-------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
|
||||
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
------------------------------------------
|
||||
|
||||
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|
||||
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1725 | 1200 | 600 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
|
||||
| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3755 | 1500 | 1133 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
|
||||
| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2206 | 1200 | 708 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
|
||||
| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4046 | 1500 | 1149 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
|
||||
| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4593 | 1800 | 889 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
|
||||
| X1Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 1807 | 950 | 526 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
* Global Clock column represents track count; while other columns represents cell counts
|
||||
|
||||
|
||||
5. Clock Regions : Global Clock Summary
|
||||
---------------------------------------
|
||||
|
||||
All Modules
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 0 | 0 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+
|
||||
| g0 | BUFG/O | n/a | clk_out1_phase_locked_loop | 20.000 | {0.000 10.000} | 18132 | 0 | 0 | 0 | pll/inst/clk_out1 |
|
||||
+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+-------+-------+-----------------------+
|
||||
| | X0 | X1 | HORIZONTAL PROG DELAY |
|
||||
+----+-------+-------+-----------------------+
|
||||
| Y2 | 4593 | 1807 | 0 |
|
||||
| Y1 | 2206 | 4046 | 0 |
|
||||
| Y0 | 1725 | 3755 | 0 |
|
||||
+----+-------+-------+-----------------------+
|
||||
|
||||
|
||||
7. Device Cell Placement Summary for Global Clock g1
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-----------------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-----------------------------------------+
|
||||
| g1 | BUFG/O | n/a | clkfbout_phase_locked_loop | 20.000 | {0.000 10.000} | 0 | 0 | 1 | 0 | pll/inst/clkfbout_buf_phase_locked_loop |
|
||||
+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-----------------------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+----+----+-----------------------+
|
||||
| | X0 | X1 | HORIZONTAL PROG DELAY |
|
||||
+----+----+----+-----------------------+
|
||||
| Y2 | 0 | 0 | - |
|
||||
| Y1 | 0 | 0 | - |
|
||||
| Y0 | 0 | 1 | 0 |
|
||||
+----+----+----+-----------------------+
|
||||
|
||||
|
||||
8. Clock Region Cell Placement per Global Clock: Region X0Y0
|
||||
------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
| g0 | n/a | BUFG/O | None | 1725 | 0 | 1725 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
9. Clock Region Cell Placement per Global Clock: Region X1Y0
|
||||
------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 3755 | 0 | 3755 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
|
||||
| g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | pll/inst/clkfbout_buf_phase_locked_loop |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
10. Clock Region Cell Placement per Global Clock: Region X0Y1
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
| g0 | n/a | BUFG/O | None | 2206 | 0 | 2206 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
11. Clock Region Cell Placement per Global Clock: Region X1Y1
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
| g0 | n/a | BUFG/O | None | 4046 | 0 | 4046 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
12. Clock Region Cell Placement per Global Clock: Region X0Y2
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
| g0 | n/a | BUFG/O | None | 4593 | 0 | 4593 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
13. Clock Region Cell Placement per Global Clock: Region X1Y2
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
| g0 | n/a | BUFG/O | None | 1807 | 0 | 1807 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
|
||||
# Location of BUFG Primitives
|
||||
set_property LOC BUFGCTRL_X0Y1 [get_cells pll/inst/clkf_buf]
|
||||
set_property LOC BUFGCTRL_X0Y0 [get_cells pll/inst/clkout1_buf]
|
||||
|
||||
# Location of IO Primitives which is load of clock spine
|
||||
|
||||
# Location of clock ports
|
||||
set_property LOC IOB_X1Y24 [get_ports hardware_clk]
|
||||
|
||||
# Clock net "pll/inst/clk_out1" driven by instance "pll/inst/clkout1_buf" located at site "BUFGCTRL_X0Y0"
|
||||
#startgroup
|
||||
create_pblock {CLKAG_pll/inst/clk_out1}
|
||||
add_cells_to_pblock [get_pblocks {CLKAG_pll/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pll/inst/clk_out1"}]]]
|
||||
resize_pblock [get_pblocks {CLKAG_pll/inst/clk_out1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
|
||||
#endgroup
|
||||
625
PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt
Normal file
625
PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt
Normal file
@@ -0,0 +1,625 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
| Date : Fri Jul 12 00:10:49 2024
|
||||
| Host : Viviana running 64-bit major release (build 9200)
|
||||
| Command : report_control_sets -verbose -file CPU_control_sets_placed.rpt
|
||||
| Design : CPU
|
||||
| Device : xc7a35t
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Control Set Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
2. Histogram
|
||||
3. Flip-Flop Distribution
|
||||
4. Detailed Control Set Information
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+----------------------------------------------------------+-------+
|
||||
| Status | Count |
|
||||
+----------------------------------------------------------+-------+
|
||||
| Total control sets | 547 |
|
||||
| Minimum number of control sets | 547 |
|
||||
| Addition due to synthesis replication | 0 |
|
||||
| Addition due to physical synthesis replication | 0 |
|
||||
| Unused register locations in slices containing registers | 12 |
|
||||
+----------------------------------------------------------+-------+
|
||||
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
|
||||
** Run report_qor_suggestions for automated merging and remapping suggestions
|
||||
|
||||
|
||||
2. Histogram
|
||||
------------
|
||||
|
||||
+--------------------+-------+
|
||||
| Fanout | Count |
|
||||
+--------------------+-------+
|
||||
| Total control sets | 547 |
|
||||
| >= 0 to < 4 | 0 |
|
||||
| >= 4 to < 6 | 0 |
|
||||
| >= 6 to < 8 | 0 |
|
||||
| >= 8 to < 10 | 0 |
|
||||
| >= 10 to < 12 | 0 |
|
||||
| >= 12 to < 14 | 0 |
|
||||
| >= 14 to < 16 | 0 |
|
||||
| >= 16 | 547 |
|
||||
+--------------------+-------+
|
||||
* Control sets can be remapped at either synth_design or opt_design
|
||||
|
||||
|
||||
3. Flip-Flop Distribution
|
||||
-------------------------
|
||||
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| No | No | No | 0 | 0 |
|
||||
| No | No | Yes | 0 | 0 |
|
||||
| No | Yes | No | 712 | 221 |
|
||||
| Yes | No | No | 0 | 0 |
|
||||
| Yes | No | Yes | 0 | 0 |
|
||||
| Yes | Yes | No | 17420 | 7427 |
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
|
||||
|
||||
4. Detailed Control Set Information
|
||||
-----------------------------------
|
||||
|
||||
+--------------------+------------------------------------------------------------+-----------------------------------+------------------+----------------+--------------+
|
||||
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
|
||||
+--------------------+------------------------------------------------------------+-----------------------------------+------------------+----------------+--------------+
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_4[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_56[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | write_back/WB_register_write_reg_1[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[24][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[4][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[3][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[2][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[23][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[17][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[5][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[22][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[26][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[10][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[14][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[16][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[13][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[19][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[30][31]_i_1_n_0 | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[11][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[8][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[21][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[27][31]_i_1_n_0 | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[29][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[7][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[31][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[28][31]_i_1_n_0 | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[25][31]_i_1_n_0 | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/p_0_in | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[18][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[9][31]_i_1_n_0 | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[20][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | instruction_decode/register_file/registers[12][31]_i_1_n_0 | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | instruction_decode/E[0] | data_memory/reset | 9 | 32 | 3.56 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_0[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[10]_1[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/E[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_1[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_10[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_11[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_13[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_15[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_12[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_19[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_21[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_2[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_6[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_1[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_24[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_1[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_5[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_0[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__9_0[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_0[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_3[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_4[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__11_1[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_4[0] | data_memory/reset | 19 | 32 | 1.68 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_5[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__21_2[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__22_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_4[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__17_1[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_3[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_5[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_0[0] | data_memory/reset | 9 | 32 | 3.56 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_0[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_17[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_7[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_2[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__23_0[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_18[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_20[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_2[0] | data_memory/reset | 9 | 32 | 3.56 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__12_2[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_0[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_2[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_3[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__20_3[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__26_1[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_16[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_22[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_27[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_28[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_23[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__14_1[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_3[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_14[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_25[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_26[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_3[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_0[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__16_2[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_1[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_2[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__19_2[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__15_2[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__24_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__13_1[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[2]_rep__25_0[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_4[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_3[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__19_1[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_1[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_3[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__27_1[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__28_0[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_3[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_5[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__29_1[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__31_1[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_3[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_4[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_0[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_1[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_2[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_rep_1[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_4[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__13_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_1[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_0[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__18_3[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_5[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_4[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_4[0] | data_memory/reset | 19 | 32 | 1.68 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__16_1[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_1[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_3[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_3[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__25_1[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_1[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__11_1[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_3[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | write_back/WB_register_write_destination_reg[3]_1[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_8[0] | data_memory/reset | 9 | 32 | 3.56 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_3[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_5[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_4[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_1[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_9[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_3[0] | data_memory/reset | 9 | 32 | 3.56 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_0[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__19_2[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__22_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_0[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_1[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_2[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_2[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_3[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__17_3[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__26_3[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__10_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__12_1[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__14_2[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[30]_6[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__15_5[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__20_1[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__21_2[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__24_2[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_1[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_14[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_16[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_4[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_1[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_2[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_28[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_7[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_8[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_5[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_7[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_11[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_0[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_9[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_11[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_14[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_3[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_15[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_10[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_29[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_2[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_26[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_13[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_13[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_20[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_3[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_6[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_9[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_1[0] | data_memory/reset | 19 | 32 | 1.68 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_31[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_19[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_10[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_11[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_10[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_16[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_8[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_12[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_17[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__31_2[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_12[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_22[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_23[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_4[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_2[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_17[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_12[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_18[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_19[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_30[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_2[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_0[0] | data_memory/reset | 9 | 32 | 3.56 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_18[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_24[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_13[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_0[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_14[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_27[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_15[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_6[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_21[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[3]_rep__9_1[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_25[0] | data_memory/reset | 9 | 32 | 3.56 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[4]_rep__30_5[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[5]_rep__6_0[0] | data_memory/reset | 9 | 32 | 3.56 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_1[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_2[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_5[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_6[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_7[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_12[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_22[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_8[0] | data_memory/reset | 19 | 32 | 1.68 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_9[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_1[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_10[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_12[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_21[0] | data_memory/reset | 19 | 32 | 1.68 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_25[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_18[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_31[0] | data_memory/reset | 19 | 32 | 1.68 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_0[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_19[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_13[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_14[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_9[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_15[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_22[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_16[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_18[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_37[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_11[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_19[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_17[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_24[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_32[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_8[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_20[0] | data_memory/reset | 19 | 32 | 1.68 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_23[0] | data_memory/reset | 19 | 32 | 1.68 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_27[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_24[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_25[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_3[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_5[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_6[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_13[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_7[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_15[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_16[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_17[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_20[0] | data_memory/reset | 19 | 32 | 1.68 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_23[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_28[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_29[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_3[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_30[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_33[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_34[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_35[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_36[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_10[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_11[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_21[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep_4[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_14[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_26[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_38[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[6]_rep__0_4[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_4[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_5[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_7[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_24[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_29[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_37[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_8[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_9[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_0[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_1[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_10[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_5[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_9[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_30[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_13[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_6[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_22[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_27[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_35[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_4[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_40[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_7[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_12[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_26[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_32[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_23[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_36[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_39[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_28[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_3[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_41[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_14[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_1[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_31[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_18[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_19[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_23[0] | data_memory/reset | 19 | 32 | 1.68 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_25[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_26[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_27[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_16[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_3[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_20[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_33[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_11[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_10[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_15[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_30[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_17[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_21[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_22[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_24[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_25[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_38[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_6[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_29[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_31[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_32[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_2[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_21[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep_34[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_20[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[7]_rep__0_28[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_32[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_6[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_7[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_13[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_20[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_24[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_8[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_48[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_34[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_15[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_4[0] | data_memory/reset | 19 | 32 | 1.68 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_7[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_27[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_49[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_50[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_9[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_33[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_11[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_4[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_14[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_19[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_5[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_18[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_3[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_11[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_12[0] | data_memory/reset | 9 | 32 | 3.56 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_0[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_28[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_6[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_2[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_21[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_38[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_26[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_25[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_31[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_41[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_42[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_1[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_17[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_35[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_44[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_43[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_36[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_37[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_46[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_47[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_22[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_3[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_5[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_51[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_30[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep_8[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_10[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_16[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_13[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_23[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_29[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_39[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_40[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_45[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[8]_rep__0_52[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_5[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_6[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_7[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_2[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_3[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_0[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_4[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_9[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_8[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_ALU_result_reg[9]_1[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_10[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_11[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_13[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_6[0] | data_memory/reset | 16 | 32 | 2.00 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_8[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_1[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_10[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_11[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_5[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_14[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_0[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_13[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_1[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_12[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_0[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_12[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_3[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_4[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_7[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_2[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_9[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_14[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_20[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_25[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_15[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_4[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_17[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_35[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_31[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_27[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_21[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_26[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_37[0] | data_memory/reset | 9 | 32 | 3.56 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_28[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_9[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_38[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_39[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_21[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_28[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_35[0] | data_memory/reset | 18 | 32 | 1.78 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_15[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_8[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_18[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_22[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_19[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_24[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_22[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_32[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_30[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_16[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_36[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_6[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_25[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_1[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_18[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_19[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_23[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_27[0] | data_memory/reset | 9 | 32 | 3.56 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_12[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_2[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_11[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_24[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_17[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_2[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_33[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_29[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_29[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_3[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_30[0] | data_memory/reset | 9 | 32 | 3.56 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_31[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_13[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_32[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_33[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_5[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_23[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_16[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_34[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_26[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_36[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_10[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_20[0] | data_memory/reset | 17 | 32 | 1.88 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_34[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_0[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_7[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_46[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_55[0] | data_memory/reset | 10 | 32 | 3.20 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_5[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_41[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_47[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_43[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_49[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_53[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_42[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_52[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_44[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_57[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_61[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_9[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_54[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_48[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_60[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_4[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_45[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_51[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_59[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_58[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_6[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_7[0] | data_memory/reset | 15 | 32 | 2.13 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_8[0] | data_memory/reset | 11 | 32 | 2.91 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_50[0] | data_memory/reset | 12 | 32 | 2.67 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_62[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_63[0] | data_memory/reset | 14 | 32 | 2.29 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep__0_40[0] | data_memory/reset | 13 | 32 | 2.46 |
|
||||
| pll/inst/clk_out1 | memory_access/MEM_memory_write_reg_rep_3[0] | data_memory/reset | 13 | 44 | 3.38 |
|
||||
| pll/inst/clk_out1 | | instruction_decode/IFID_PC_plus_4 | 32 | 67 | 2.09 |
|
||||
| pll/inst/clk_out1 | | execution/alu/SR[0] | 50 | 160 | 3.20 |
|
||||
| pll/inst/clk_out1 | | data_memory/reset | 139 | 485 | 3.49 |
|
||||
+--------------------+------------------------------------------------------------+-----------------------------------+------------------+----------------+--------------+
|
||||
|
||||
|
||||
BIN
PipelineProcessor.runs/impl_1/CPU_drc_opted.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/CPU_drc_opted.pb
Normal file
Binary file not shown.
112
PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt
Normal file
112
PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt
Normal file
@@ -0,0 +1,112 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
| Date : Fri Jul 12 00:10:18 2024
|
||||
| Host : Viviana running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx
|
||||
| Design : CPU
|
||||
| Device : xc7a35tfgg484-1
|
||||
| Speed File : -1
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 13
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
|
||||
| DPIP-1 | Warning | Input pipelining | 6 |
|
||||
| DPOP-1 | Warning | PREG Output pipelining | 3 |
|
||||
| DPOP-2 | Warning | MREG Output pipelining | 3 |
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
CFGBVS-1#1 Warning
|
||||
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
|
||||
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
|
||||
|
||||
set_property CFGBVS value1 [current_design]
|
||||
#where value1 is either VCCO or GND
|
||||
|
||||
set_property CONFIG_VOLTAGE value2 [current_design]
|
||||
#where value2 is the voltage provided to configuration bank 0
|
||||
|
||||
Refer to the device configuration user guide for more information.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#1 Warning
|
||||
Input pipelining
|
||||
DSP execution/alu/result0 input execution/alu/result0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#2 Warning
|
||||
Input pipelining
|
||||
DSP execution/alu/result0 input execution/alu/result0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#3 Warning
|
||||
Input pipelining
|
||||
DSP execution/alu/result0__0 input execution/alu/result0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#4 Warning
|
||||
Input pipelining
|
||||
DSP execution/alu/result0__0 input execution/alu/result0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#5 Warning
|
||||
Input pipelining
|
||||
DSP execution/alu/result0__1 input execution/alu/result0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#6 Warning
|
||||
Input pipelining
|
||||
DSP execution/alu/result0__1 input execution/alu/result0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#1 Warning
|
||||
PREG Output pipelining
|
||||
DSP execution/alu/result0 output execution/alu/result0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#2 Warning
|
||||
PREG Output pipelining
|
||||
DSP execution/alu/result0__0 output execution/alu/result0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#3 Warning
|
||||
PREG Output pipelining
|
||||
DSP execution/alu/result0__1 output execution/alu/result0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#1 Warning
|
||||
MREG Output pipelining
|
||||
DSP execution/alu/result0 multiplier stage execution/alu/result0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#2 Warning
|
||||
MREG Output pipelining
|
||||
DSP execution/alu/result0__0 multiplier stage execution/alu/result0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#3 Warning
|
||||
MREG Output pipelining
|
||||
DSP execution/alu/result0__1 multiplier stage execution/alu/result0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
BIN
PipelineProcessor.runs/impl_1/CPU_drc_routed.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/CPU_drc_routed.pb
Normal file
Binary file not shown.
112
PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt
Normal file
112
PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt
Normal file
@@ -0,0 +1,112 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
| Date : Fri Jul 12 00:11:29 2024
|
||||
| Host : Viviana running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
|
||||
| Design : CPU
|
||||
| Device : xc7a35tfgg484-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 13
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
|
||||
| DPIP-1 | Warning | Input pipelining | 6 |
|
||||
| DPOP-1 | Warning | PREG Output pipelining | 3 |
|
||||
| DPOP-2 | Warning | MREG Output pipelining | 3 |
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
CFGBVS-1#1 Warning
|
||||
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
|
||||
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
|
||||
|
||||
set_property CFGBVS value1 [current_design]
|
||||
#where value1 is either VCCO or GND
|
||||
|
||||
set_property CONFIG_VOLTAGE value2 [current_design]
|
||||
#where value2 is the voltage provided to configuration bank 0
|
||||
|
||||
Refer to the device configuration user guide for more information.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#1 Warning
|
||||
Input pipelining
|
||||
DSP execution/alu/result0 input execution/alu/result0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#2 Warning
|
||||
Input pipelining
|
||||
DSP execution/alu/result0 input execution/alu/result0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#3 Warning
|
||||
Input pipelining
|
||||
DSP execution/alu/result0__0 input execution/alu/result0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#4 Warning
|
||||
Input pipelining
|
||||
DSP execution/alu/result0__0 input execution/alu/result0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#5 Warning
|
||||
Input pipelining
|
||||
DSP execution/alu/result0__1 input execution/alu/result0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPIP-1#6 Warning
|
||||
Input pipelining
|
||||
DSP execution/alu/result0__1 input execution/alu/result0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#1 Warning
|
||||
PREG Output pipelining
|
||||
DSP execution/alu/result0 output execution/alu/result0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#2 Warning
|
||||
PREG Output pipelining
|
||||
DSP execution/alu/result0__0 output execution/alu/result0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-1#3 Warning
|
||||
PREG Output pipelining
|
||||
DSP execution/alu/result0__1 output execution/alu/result0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#1 Warning
|
||||
MREG Output pipelining
|
||||
DSP execution/alu/result0 multiplier stage execution/alu/result0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#2 Warning
|
||||
MREG Output pipelining
|
||||
DSP execution/alu/result0__0 multiplier stage execution/alu/result0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
DPOP-2#3 Warning
|
||||
MREG Output pipelining
|
||||
DSP execution/alu/result0__1 multiplier stage execution/alu/result0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
526
PipelineProcessor.runs/impl_1/CPU_io_placed.rpt
Normal file
526
PipelineProcessor.runs/impl_1/CPU_io_placed.rpt
Normal file
@@ -0,0 +1,526 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
| Date : Fri Jul 12 00:10:49 2024
|
||||
| Host : Viviana running 64-bit major release (build 9200)
|
||||
| Command : report_io -file CPU_io_placed.rpt
|
||||
| Design : CPU
|
||||
| Device : xc7a35t
|
||||
| Speed File : -1
|
||||
| Package : fgg484
|
||||
| Package Version : FINAL 2013-11-27
|
||||
| Package Pin Delay Version : VERS. 2.0 2013-11-27
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
IO Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
2. IO Assignments by Package Pin
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+---------------+
|
||||
| Total User IO |
|
||||
+---------------+
|
||||
| 15 |
|
||||
+---------------+
|
||||
|
||||
|
||||
2. IO Assignments by Package Pin
|
||||
--------------------------------
|
||||
|
||||
+------------+-----------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
|
||||
+------------+-----------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| A1 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A4 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A6 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A8 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A10 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A14 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A15 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A16 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A17 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| A18 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A19 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A20 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A21 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA3 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AA4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AA5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AA6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AA7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| AA8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AA9 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AA10 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AA11 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA13 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AA14 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AA15 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AA16 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AA17 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| AA18 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| AA19 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| AA20 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| AA21 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AB2 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AB3 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AB4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| AB5 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AB6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AB7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AB8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB10 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AB11 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AB12 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AB13 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AB14 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| AB15 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AB16 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AB17 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| AB18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB20 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| AB21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| AB22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| B1 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B4 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B6 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B8 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B9 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B10 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B11 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| B15 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B16 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B17 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B18 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B20 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B21 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B22 | hardware_reset | High Range | IO_L20N_T3_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| C1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| C2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| C5 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C7 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C8 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| C9 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C11 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C14 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C15 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C18 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C19 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C20 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| C22 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D2 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D5 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| D7 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D9 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D10 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| D11 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D16 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D17 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| D19 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D20 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D21 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D22 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E2 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E3 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E6 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| E11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E12 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| E13 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E14 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| E16 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E17 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E18 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E19 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E21 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E22 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F1 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| F3 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F4 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F6 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| F7 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| F8 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| F9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| F10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
|
||||
| F13 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F14 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F15 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F16 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F18 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F19 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F20 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F21 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
|
||||
| G1 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G2 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G3 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G4 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G13 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G15 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G16 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G17 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G18 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| G20 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G21 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| G22 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H2 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H3 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H4 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H5 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| H13 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H14 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| H17 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H18 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H19 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H20 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H22 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J1 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J2 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| J4 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J5 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J6 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| J14 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J16 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J17 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J19 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J22 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K1 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K3 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K6 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| K9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| K10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| K13 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K14 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K16 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K17 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K19 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| K21 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K22 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L1 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L3 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| L4 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| L5 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| L6 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| L10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| L11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| L12 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| L13 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L14 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L15 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L16 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| L18 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L19 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L20 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L21 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M1 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M2 | bcd_control[11] | High Range | IO_L16N_T2_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M3 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M4 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| M5 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M6 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| M9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| M10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| M13 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M14 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| M15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M16 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M17 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M18 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M21 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| N1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| N2 | bcd_control[0] | High Range | IO_L22N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N3 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| N4 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| N5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| N10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| N12 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| N13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N14 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N15 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| N18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| N19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| N20 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| N21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| N22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| P1 | bcd_control[5] | High Range | IO_L20N_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P2 | bcd_control[10] | High Range | IO_L22P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| P5 | bcd_control[1] | High Range | IO_L21P_T3_DQS_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P14 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P15 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P16 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| P19 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P20 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P21 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| P22 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R1 | bcd_control[9] | High Range | IO_L20P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R2 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R3 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R4 | hardware_clk | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| R5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| R6 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R13 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| R14 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| R16 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R17 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R18 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R21 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| R22 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| T3 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T4 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T5 | bcd_control[4] | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T6 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
|
||||
| T13 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| T14 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| T15 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| T16 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T18 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T20 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T21 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| T22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| U1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U2 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U5 | bcd_control[3] | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U6 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U7 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| U9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| U10 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| U11 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| U12 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| U13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U15 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| U16 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| U19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| U20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| U21 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| U22 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V2 | clock_locked | High Range | IO_L2N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V3 | bcd_control[7] | High Range | IO_L6N_T0_VREF_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V4 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V5 | bcd_control[2] | High Range | IO_L16N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| V7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V8 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V10 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| V13 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| V14 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| V15 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| V16 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| V17 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V19 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V22 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| W1 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W2 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
|
||||
| W4 | bcd_control[6] | High Range | IO_L12N_T1_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W5 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W6 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W9 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W10 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| W11 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| W12 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| W13 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| W14 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| W15 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| W16 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| W17 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| W20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| W21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| W22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| Y1 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y3 | bcd_control[8] | High Range | IO_L9P_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y7 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y8 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y9 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y10 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| Y11 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y12 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y13 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y14 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y16 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y17 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| Y19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| Y20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| Y21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| Y22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
+------------+-----------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
* Default value
|
||||
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
BIN
PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.pb
Normal file
Binary file not shown.
50
PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt
Normal file
50
PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt
Normal file
@@ -0,0 +1,50 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
| Date : Fri Jul 12 00:11:34 2024
|
||||
| Host : Viviana running 64-bit major release (build 9200)
|
||||
| Command : report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx
|
||||
| Design : CPU
|
||||
| Device : xc7a35tfgg484-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Methodology
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Max violations: <unlimited>
|
||||
Violations found: 3
|
||||
+----------+----------+-----------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+----------+----------+-----------------+------------+
|
||||
| SYNTH-10 | Warning | Wide multiplier | 3 |
|
||||
+----------+----------+-----------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
SYNTH-10#1 Warning
|
||||
Wide multiplier
|
||||
Detected multiplier at execution/alu/result0 of size 16x18, it is decomposed from a wide multipler into 4 DSP blocks.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-10#2 Warning
|
||||
Wide multiplier
|
||||
Detected multiplier at execution/alu/result0__0 of size 18x18, it is decomposed from a wide multipler into 4 DSP blocks.
|
||||
Related violations: <none>
|
||||
|
||||
SYNTH-10#3 Warning
|
||||
Wide multiplier
|
||||
Detected multiplier at execution/alu/result0__1 of size 18x16, it is decomposed from a wide multipler into 4 DSP blocks.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
BIN
PipelineProcessor.runs/impl_1/CPU_opt.dcp
Normal file
BIN
PipelineProcessor.runs/impl_1/CPU_opt.dcp
Normal file
Binary file not shown.
BIN
PipelineProcessor.runs/impl_1/CPU_physopt.dcp
Normal file
BIN
PipelineProcessor.runs/impl_1/CPU_physopt.dcp
Normal file
Binary file not shown.
BIN
PipelineProcessor.runs/impl_1/CPU_placed.dcp
Normal file
BIN
PipelineProcessor.runs/impl_1/CPU_placed.dcp
Normal file
Binary file not shown.
158
PipelineProcessor.runs/impl_1/CPU_power_routed.rpt
Normal file
158
PipelineProcessor.runs/impl_1/CPU_power_routed.rpt
Normal file
@@ -0,0 +1,158 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
| Date : Fri Jul 12 00:11:38 2024
|
||||
| Host : Viviana running 64-bit major release (build 9200)
|
||||
| Command : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
|
||||
| Design : CPU
|
||||
| Device : xc7a35tfgg484-1
|
||||
| Design State : routed
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 0.188 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.120 |
|
||||
| Device Static (W) | 0.069 |
|
||||
| Effective TJA (C/W) | 2.8 |
|
||||
| Max Ambient (C) | 84.5 |
|
||||
| Junction Temperature (C) | 25.5 |
|
||||
| Confidence Level | Medium |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
| Clocks | 0.016 | 5 | --- | --- |
|
||||
| Slice Logic | 0.003 | 29973 | --- | --- |
|
||||
| LUT as Logic | 0.003 | 7991 | 20800 | 38.42 |
|
||||
| CARRY4 | <0.001 | 39 | 8150 | 0.48 |
|
||||
| Register | <0.001 | 18132 | 41600 | 43.59 |
|
||||
| F7/F8 Muxes | <0.001 | 3440 | 32600 | 10.55 |
|
||||
| Others | 0.000 | 12 | --- | --- |
|
||||
| Signals | 0.002 | 21870 | --- | --- |
|
||||
| PLL | 0.099 | 1 | 5 | 20.00 |
|
||||
| DSPs | <0.001 | 3 | 90 | 3.33 |
|
||||
| I/O | <0.001 | 15 | 250 | 6.00 |
|
||||
| Static Power | 0.069 | | | |
|
||||
| Total | 0.188 | | | |
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.039 | 0.030 | 0.010 | NA | Unspecified | NA |
|
||||
| Vccaux | 1.800 | 0.063 | 0.050 | 0.013 | NA | Unspecified | NA |
|
||||
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
|
||||
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | High | User specified more than 95% of clocks | |
|
||||
| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Medium | | |
|
||||
+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 2.8 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 4.6 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+----------------------------+-------------------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+----------------------------+-------------------------------------+-----------------+
|
||||
| clk_out1_phase_locked_loop | pll/inst/clk_out1_phase_locked_loop | 20.0 |
|
||||
| clkfbout_phase_locked_loop | pll/inst/clkfbout_phase_locked_loop | 20.0 |
|
||||
| hardware_clk | hardware_clk | 10.0 |
|
||||
+----------------------------+-------------------------------------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+----------------------+-----------+
|
||||
| Name | Power (W) |
|
||||
+----------------------+-----------+
|
||||
| CPU | 0.120 |
|
||||
| data_memory | 0.014 |
|
||||
| instruction_decode | 0.002 |
|
||||
| register_file | 0.001 |
|
||||
| instruction_fetch | 0.001 |
|
||||
| pll | 0.100 |
|
||||
| inst | 0.100 |
|
||||
| write_back | 0.002 |
|
||||
+----------------------+-----------+
|
||||
|
||||
|
||||
BIN
PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb
Normal file
Binary file not shown.
BIN
PipelineProcessor.runs/impl_1/CPU_route_status.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/CPU_route_status.pb
Normal file
Binary file not shown.
11
PipelineProcessor.runs/impl_1/CPU_route_status.rpt
Normal file
11
PipelineProcessor.runs/impl_1/CPU_route_status.rpt
Normal file
@@ -0,0 +1,11 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 30198 :
|
||||
# of nets not needing routing.......... : 8321 :
|
||||
# of internally routed nets........ : 8321 :
|
||||
# of routable nets..................... : 21877 :
|
||||
# of fully routed nets............. : 21877 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
BIN
PipelineProcessor.runs/impl_1/CPU_routed.dcp
Normal file
BIN
PipelineProcessor.runs/impl_1/CPU_routed.dcp
Normal file
Binary file not shown.
BIN
PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb
Normal file
Binary file not shown.
3363
PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt
Normal file
3363
PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt
Normal file
File diff suppressed because it is too large
Load Diff
BIN
PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb
Normal file
Binary file not shown.
218
PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt
Normal file
218
PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt
Normal file
@@ -0,0 +1,218 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
| Date : Fri Jul 12 00:10:49 2024
|
||||
| Host : Viviana running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb
|
||||
| Design : CPU
|
||||
| Device : xc7a35tfgg484-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Placed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Slice Logic Distribution
|
||||
3. Memory
|
||||
4. DSP
|
||||
5. IO and GT Specific
|
||||
6. Clocking
|
||||
7. Specific Feature
|
||||
8. Primitives
|
||||
9. Black Boxes
|
||||
10. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+-------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------------------+-------+-------+------------+-----------+-------+
|
||||
| Slice LUTs | 7991 | 0 | 0 | 20800 | 38.42 |
|
||||
| LUT as Logic | 7991 | 0 | 0 | 20800 | 38.42 |
|
||||
| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 |
|
||||
| Slice Registers | 18132 | 0 | 0 | 41600 | 43.59 |
|
||||
| Register as Flip Flop | 18132 | 0 | 0 | 41600 | 43.59 |
|
||||
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
|
||||
| F7 Muxes | 2352 | 0 | 0 | 16300 | 14.43 |
|
||||
| F8 Muxes | 1088 | 0 | 0 | 8150 | 13.35 |
|
||||
+-------------------------+-------+-------+------------+-----------+-------+
|
||||
* Warning! LUT value is adjusted to account for LUT combining.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 18132 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Slice Logic Distribution
|
||||
---------------------------
|
||||
|
||||
+--------------------------------------------+-------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+--------------------------------------------+-------+-------+------------+-----------+-------+
|
||||
| Slice | 7679 | 0 | 0 | 8150 | 94.22 |
|
||||
| SLICEL | 5398 | 0 | | | |
|
||||
| SLICEM | 2281 | 0 | | | |
|
||||
| LUT as Logic | 7991 | 0 | 0 | 20800 | 38.42 |
|
||||
| using O5 output only | 0 | | | | |
|
||||
| using O6 output only | 7632 | | | | |
|
||||
| using O5 and O6 | 359 | | | | |
|
||||
| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | | |
|
||||
| LUT as Shift Register | 0 | 0 | | | |
|
||||
| Slice Registers | 18132 | 0 | 0 | 41600 | 43.59 |
|
||||
| Register driven from within the Slice | 1317 | | | | |
|
||||
| Register driven from outside the Slice | 16815 | | | | |
|
||||
| LUT in front of the register is unused | 14690 | | | | |
|
||||
| LUT in front of the register is used | 2125 | | | | |
|
||||
| Unique Control Sets | 547 | | 0 | 8150 | 6.71 |
|
||||
+--------------------------------------------+-------+-------+------------+-----------+-------+
|
||||
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
|
||||
3. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 0 | 100 | 0.00 |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
4. DSP
|
||||
------
|
||||
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| DSPs | 3 | 0 | 0 | 90 | 3.33 |
|
||||
| DSP48E1 only | 3 | | | | |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
5. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Bonded IOB | 15 | 15 | 0 | 250 | 6.00 |
|
||||
| IOB Master Pads | 6 | | | | |
|
||||
| IOB Slave Pads | 9 | | | | |
|
||||
| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 0 | 240 | 0.00 |
|
||||
| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 0 | 250 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 0 | 250 | 0.00 |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
6. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
|
||||
| BUFIO | 0 | 0 | 0 | 20 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 |
|
||||
| PLLE2_ADV | 1 | 0 | 0 | 5 | 20.00 |
|
||||
| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
|
||||
| BUFR | 0 | 0 | 0 | 20 | 0.00 |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
7. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
8. Primitives
|
||||
-------------
|
||||
|
||||
+-----------+-------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+-----------+-------+---------------------+
|
||||
| FDRE | 18132 | Flop & Latch |
|
||||
| LUT6 | 6948 | LUT |
|
||||
| MUXF7 | 2352 | MuxFx |
|
||||
| MUXF8 | 1088 | MuxFx |
|
||||
| LUT5 | 701 | LUT |
|
||||
| LUT4 | 309 | LUT |
|
||||
| LUT3 | 230 | LUT |
|
||||
| LUT2 | 161 | LUT |
|
||||
| CARRY4 | 39 | CarryLogic |
|
||||
| OBUF | 13 | IO |
|
||||
| DSP48E1 | 3 | Block Arithmetic |
|
||||
| IBUF | 2 | IO |
|
||||
| BUFG | 2 | Clock |
|
||||
| PLLE2_ADV | 1 | Clock |
|
||||
| LUT1 | 1 | LUT |
|
||||
+-----------+-------+---------------------+
|
||||
|
||||
|
||||
9. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
10. Instantiated Netlists
|
||||
-------------------------
|
||||
|
||||
+-------------------+------+
|
||||
| Ref Name | Used |
|
||||
+-------------------+------+
|
||||
| phase_locked_loop | 1 |
|
||||
+-------------------+------+
|
||||
|
||||
|
||||
10
PipelineProcessor.runs/impl_1/clockInfo.txt
Normal file
10
PipelineProcessor.runs/impl_1/clockInfo.txt
Normal file
@@ -0,0 +1,10 @@
|
||||
-------------------------------------
|
||||
| Tool Version : Vivado v.2023.2
|
||||
| Date : Fri Jul 12 00:10:23 2024
|
||||
| Host : Viviana
|
||||
| Design : design_1
|
||||
| Device : xc7a35t-fgg484-1--
|
||||
-------------------------------------
|
||||
|
||||
For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
|
||||
|
||||
10
PipelineProcessor.runs/impl_1/htr.txt
Normal file
10
PipelineProcessor.runs/impl_1/htr.txt
Normal file
@@ -0,0 +1,10 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
REM Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log CPU.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace
|
||||
BIN
PipelineProcessor.runs/impl_1/init_design.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/init_design.pb
Normal file
Binary file not shown.
BIN
PipelineProcessor.runs/impl_1/opt_design.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/opt_design.pb
Normal file
Binary file not shown.
BIN
PipelineProcessor.runs/impl_1/phys_opt_design.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/phys_opt_design.pb
Normal file
Binary file not shown.
BIN
PipelineProcessor.runs/impl_1/place_design.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/place_design.pb
Normal file
Binary file not shown.
BIN
PipelineProcessor.runs/impl_1/route_design.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/route_design.pb
Normal file
Binary file not shown.
14
PipelineProcessor.runs/impl_1/vivado.jou
Normal file
14
PipelineProcessor.runs/impl_1/vivado.jou
Normal file
@@ -0,0 +1,14 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Fri Jul 12 00:09:58 2024
|
||||
# Process ID: 29956
|
||||
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1
|
||||
# Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace
|
||||
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi
|
||||
# Journal file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1\vivado.jou
|
||||
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
|
||||
#-----------------------------------------------------------
|
||||
source CPU.tcl -notrace
|
||||
BIN
PipelineProcessor.runs/impl_1/vivado.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/vivado.pb
Normal file
Binary file not shown.
BIN
PipelineProcessor.runs/impl_1/write_bitstream.pb
Normal file
BIN
PipelineProcessor.runs/impl_1/write_bitstream.pb
Normal file
Binary file not shown.
@@ -1,7 +1,7 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
|
||||
# IP: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
|
||||
# IP: The module: 'phase_locked_loop' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc
|
||||
@@ -16,7 +16,7 @@ set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||
|
||||
# IP: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
|
||||
# IP: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
|
||||
# IP: The module: 'phase_locked_loop' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc
|
||||
|
||||
Binary file not shown.
@@ -88,7 +88,7 @@ set_property ip_output_repo d:/Documents/VivadoProjects/PipelineProcessor/Pipeli
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_ip -quiet d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
|
||||
read_ip -quiet D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
|
||||
set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc]
|
||||
|
||||
@@ -3,8 +3,8 @@
|
||||
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Tue Jul 9 23:43:44 2024
|
||||
# Process ID: 8060
|
||||
# Start of session at: Thu Jul 11 13:35:23 2024
|
||||
# Process ID: 33384
|
||||
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1
|
||||
# Command line: vivado.exe -log phase_locked_loop.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source phase_locked_loop.tcl
|
||||
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds
|
||||
@@ -12,7 +12,7 @@
|
||||
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
|
||||
#-----------------------------------------------------------
|
||||
source phase_locked_loop.tcl -notrace
|
||||
create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:09 . Memory (MB): peak = 463.379 ; gain = 184.172
|
||||
create_project: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 464.625 ; gain = 187.449
|
||||
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: phase_locked_loop
|
||||
Command: synth_design -top phase_locked_loop -part xc7a35tfgg484-1 -incremental_mode off -mode out_of_context
|
||||
Starting synth_design
|
||||
@@ -21,9 +21,9 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t
|
||||
INFO: [Device 21-403] Loading part xc7a35tfgg484-1
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 32256
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 27764
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 1307.695 ; gain = 439.426
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 1306.332 ; gain = 439.227
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v:65]
|
||||
INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop_clk_wiz' [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v:65]
|
||||
@@ -31,14 +31,14 @@ INFO: [Synth 8-6157] synthesizing module 'IBUF' [E:/Applications/Xilinx/Vivado/2
|
||||
INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631]
|
||||
INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111351]
|
||||
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
|
||||
Parameter CLKFBOUT_MULT bound to: 41 - type: integer
|
||||
Parameter CLKFBOUT_MULT bound to: 17 - type: integer
|
||||
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
|
||||
Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double
|
||||
Parameter CLKOUT0_DIVIDE bound to: 82 - type: integer
|
||||
Parameter CLKOUT0_DIVIDE bound to: 17 - type: integer
|
||||
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
|
||||
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
|
||||
Parameter COMPENSATION bound to: ZHOLD - type: string
|
||||
Parameter DIVCLK_DIVIDE bound to: 5 - type: integer
|
||||
Parameter DIVCLK_DIVIDE bound to: 2 - type: integer
|
||||
Parameter STARTUP_WAIT bound to: FALSE - type: string
|
||||
INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111351]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
|
||||
@@ -46,18 +46,18 @@ INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [E:/Applications/Xili
|
||||
INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop_clk_wiz' (0#1) [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v:65]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v:65]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1415.195 ; gain = 548.090
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1415.195 ; gain = 548.090
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1415.195 ; gain = 548.090
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1416.121 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1415.195 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
@@ -77,31 +77,31 @@ Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcesso
|
||||
Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1416.121 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1429.117 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1416.121 ; gain = 0.000
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1429.145 ; gain = 0.027
|
||||
INFO: [Designutils 20-5008] Incremental synthesis strategy off
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a35tfgg484-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
@@ -124,25 +124,25 @@ Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
@@ -160,37 +160,37 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -211,18 +211,18 @@ Report Cell Usage:
|
||||
|3 |IBUF | 1|
|
||||
+------+----------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:19 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:05 ; elapsed = 00:00:18 . Memory (MB): peak = 1429.145 ; gain = 548.090
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:20 . Memory (MB): peak = 1429.145 ; gain = 562.039
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1416.121 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1429.145 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1428.094 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1434.039 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
@@ -230,11 +230,11 @@ Synth Design complete | Checksum: 5cde1ffc
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
30 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:24 . Memory (MB): peak = 1428.094 ; gain = 952.102
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1428.094 ; gain = 0.000
|
||||
synth_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:23 . Memory (MB): peak = 1434.039 ; gain = 956.965
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1434.039 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp' has been generated.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP phase_locked_loop, cache-ID = a4c5028597ba9ab4
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1428.094 ; gain = 0.000
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP phase_locked_loop, cache-ID = 11b3438a8319906c
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1434.039 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file phase_locked_loop_utilization_synth.rpt -pb phase_locked_loop_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Tue Jul 9 23:44:24 2024...
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Jul 11 13:35:55 2024...
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
| Date : Tue Jul 9 23:44:24 2024
|
||||
| Date : Thu Jul 11 13:35:55 2024
|
||||
| Host : Viviana running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file phase_locked_loop_utilization_synth.rpt -pb phase_locked_loop_utilization_synth.pb
|
||||
| Design : phase_locked_loop
|
||||
|
||||
@@ -3,8 +3,8 @@
|
||||
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Tue Jul 9 23:43:44 2024
|
||||
# Process ID: 8060
|
||||
# Start of session at: Thu Jul 11 13:35:23 2024
|
||||
# Process ID: 33384
|
||||
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1
|
||||
# Command line: vivado.exe -log phase_locked_loop.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source phase_locked_loop.tcl
|
||||
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds
|
||||
|
||||
Binary file not shown.
31
PipelineProcessor.runs/synth_1/.Xil/CPU_propImpl.xdc
Normal file
31
PipelineProcessor.runs/synth_1/.Xil/CPU_propImpl.xdc
Normal file
@@ -0,0 +1,31 @@
|
||||
set_property SRC_FILE_INFO {cfile:D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc rfile:../../../PipelineProcessor.srcs/constrs_1/new/top.xdc id:1} [current_design]
|
||||
set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {hardware_clk}]
|
||||
set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports {hardware_reset}]
|
||||
set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {clock_locked}]
|
||||
set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports {bcd_control[0]}]
|
||||
set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {bcd_control[1]}]
|
||||
set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {bcd_control[2]}]
|
||||
set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports {bcd_control[3]}]
|
||||
set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {bcd_control[4]}]
|
||||
set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports {bcd_control[5]}]
|
||||
set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS33} [get_ports {bcd_control[6]}]
|
||||
set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS33} [get_ports {bcd_control[7]}]
|
||||
set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports {bcd_control[8]}]
|
||||
set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {bcd_control[9]}]
|
||||
set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {bcd_control[10]}]
|
||||
set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bcd_control[11]}]
|
||||
BIN
PipelineProcessor.runs/synth_1/CPU.dcp
Normal file
BIN
PipelineProcessor.runs/synth_1/CPU.dcp
Normal file
Binary file not shown.
147
PipelineProcessor.runs/synth_1/CPU.tcl
Normal file
147
PipelineProcessor.runs/synth_1/CPU.tcl
Normal file
@@ -0,0 +1,147 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
namespace eval ::optrace {
|
||||
variable script "D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.tcl"
|
||||
variable category "vivado_synth"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
OPTRACE "synth_1" START { ROLLUP_AUTO }
|
||||
set_param chipscope.maxJobs 5
|
||||
set_param xicom.use_bs_reader 1
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7a35tfgg484-1
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.cache/wt [current_project]
|
||||
set_property parent.project_path D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.xpr [current_project]
|
||||
set_property XPM_LIBRARIES XPM_CDC [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_verilog -library xil_defaultlib {
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ALU.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ControlUnit.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/DataMemory.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/Execution.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ExecutionForward.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/HazardUnit.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ImmediateExtender.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstDecode.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstFetch.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/MemoryAccess.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/RegisterFile.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/WriteBack.v
|
||||
D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/CPU.v
|
||||
}
|
||||
read_ip -quiet D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
|
||||
set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc]
|
||||
set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc]
|
||||
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc
|
||||
set_property used_in_implementation false [get_files D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
|
||||
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
read_checkpoint -auto_incremental -incremental D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top CPU -part xc7a35tfgg484-1
|
||||
OPTRACE "synth_design" END { }
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef CPU.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb"
|
||||
OPTRACE "synth reports" END { }
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "synth_1" END { }
|
||||
329
PipelineProcessor.runs/synth_1/CPU.vds
Normal file
329
PipelineProcessor.runs/synth_1/CPU.vds
Normal file
@@ -0,0 +1,329 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Fri Jul 12 00:08:43 2024
|
||||
# Process ID: 16484
|
||||
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
|
||||
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds
|
||||
# Journal file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1\vivado.jou
|
||||
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
|
||||
#-----------------------------------------------------------
|
||||
source CPU.tcl -notrace
|
||||
Command: read_checkpoint -auto_incremental -incremental D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp
|
||||
INFO: [Vivado 12-5825] Read reference checkpoint from D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp for incremental synthesis
|
||||
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
|
||||
Command: synth_design -top CPU -part xc7a35tfgg484-1
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||
INFO: [Device 21-403] Loading part xc7a35tfgg484-1
|
||||
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
|
||||
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 16380
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 1308.098 ; gain = 440.137
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'CPU' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/CPU.v:2]
|
||||
INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-16484-Viviana/realtime/phase_locked_loop_stub.v:6]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-16484-Viviana/realtime/phase_locked_loop_stub.v:6]
|
||||
INFO: [Synth 8-6157] synthesizing module 'InstFetch' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstFetch.v:2]
|
||||
INFO: [Synth 8-6157] synthesizing module 'InstructionMemory' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'InstructionMemory' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'InstFetch' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstFetch.v:2]
|
||||
INFO: [Synth 8-6157] synthesizing module 'InstDecode' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstDecode.v:2]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'RegisterFile' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/RegisterFile.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'RegisterFile' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/RegisterFile.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ImmediateExtender' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ImmediateExtender.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ImmediateExtender' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ImmediateExtender.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'InstDecode' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstDecode.v:2]
|
||||
INFO: [Synth 8-6157] synthesizing module 'Execution' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/Execution.v:2]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ALU' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ALU' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'Execution' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/Execution.v:2]
|
||||
INFO: [Synth 8-6157] synthesizing module 'MemoryAccess' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/MemoryAccess.v:2]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'MemoryAccess' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/MemoryAccess.v:2]
|
||||
INFO: [Synth 8-6157] synthesizing module 'WriteBack' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/WriteBack.v:2]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'WriteBack' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/WriteBack.v:2]
|
||||
INFO: [Synth 8-6157] synthesizing module 'DataMemory' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/DataMemory.v:3]
|
||||
Parameter MEM_SIZE_IN_WORD bound to: 512 - type: integer
|
||||
Parameter START_ADDRESS bound to: 1073741824 - type: integer
|
||||
INFO: [Synth 8-6155] done synthesizing module 'DataMemory' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/DataMemory.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ExecutionForward' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ExecutionForward.v:2]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ExecutionForward' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/ExecutionForward.v:2]
|
||||
INFO: [Synth 8-6157] synthesizing module 'HazardUnit' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/HazardUnit.v:2]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'HazardUnit' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/HazardUnit.v:2]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'CPU' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/CPU.v:2]
|
||||
WARNING: [Synth 8-7129] Port address[1] in module DataMemory is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port address[0] in module DataMemory is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port address[1] in module InstructionMemory is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port address[0] in module InstructionMemory is either unconnected or has no load
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1475.660 ; gain = 607.699
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1475.660 ; gain = 607.699
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1475.660 ; gain = 607.699
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.145 . Memory (MB): peak = 1475.660 ; gain = 0.000
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc] for cell 'pll'
|
||||
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc] for cell 'pll'
|
||||
Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
|
||||
Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/CPU_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/CPU_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1581.605 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 1581.605 ; gain = 0.000
|
||||
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
|
||||
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 1581.605 ; gain = 713.645
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a35tfgg484-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 1581.605 ; gain = 713.645
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property IO_BUFFER_TYPE = NONE for hardware_clk. (constraint file d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc, line 3).
|
||||
Applied set_property CLOCK_BUFFER_TYPE = NONE for hardware_clk. (constraint file d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc, line 4).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for pll. (constraint file auto generated constraint).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:12 . Memory (MB): peak = 1581.605 ; gain = 713.645
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 1581.605 ; gain = 713.645
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 32 Bit Adders := 2
|
||||
3 Input 32 Bit Adders := 1
|
||||
+---XORs :
|
||||
2 Input 32 Bit XORs := 1
|
||||
2 Input 1 Bit XORs := 1
|
||||
+---Registers :
|
||||
32 Bit Registers := 554
|
||||
5 Bit Registers := 7
|
||||
1 Bit Registers := 12
|
||||
+---Multipliers :
|
||||
32x32 Multipliers := 1
|
||||
+---Muxes :
|
||||
2 Input 32 Bit Muxes := 81
|
||||
4 Input 32 Bit Muxes := 3
|
||||
2 Input 5 Bit Muxes := 3
|
||||
6 Input 5 Bit Muxes := 1
|
||||
4 Input 5 Bit Muxes := 1
|
||||
3 Input 2 Bit Muxes := 4
|
||||
2 Input 2 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 703
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 90 (col length:60)
|
||||
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
DSP Report: Generating DSP alu/result0, operation Mode is: A*B.
|
||||
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
|
||||
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
|
||||
DSP Report: Generating DSP alu/result0, operation Mode is: (PCIN>>17)+A*B.
|
||||
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
|
||||
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
|
||||
DSP Report: Generating DSP alu/result0, operation Mode is: A*B.
|
||||
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
|
||||
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
|
||||
DSP Report: Generating DSP alu/result0, operation Mode is: (PCIN>>17)+A*B.
|
||||
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
|
||||
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:32 . Memory (MB): peak = 1581.605 ; gain = 713.645
|
||||
---------------------------------------------------------------------------------
|
||||
Sort Area is CPU__GC0 alu/result0_0 : 0 0 : 3101 5879 : Used 1 time 0
|
||||
Sort Area is CPU__GC0 alu/result0_0 : 0 1 : 2778 5879 : Used 1 time 0
|
||||
Sort Area is CPU__GC0 alu/result0_3 : 0 0 : 2759 5418 : Used 1 time 0
|
||||
Sort Area is CPU__GC0 alu/result0_3 : 0 1 : 2659 5418 : Used 1 time 0
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
|
||||
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
||||
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
|
||||
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
||||
|Execution | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|Execution | (PCIN>>17)+A*B | 16 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|Execution | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|Execution | (PCIN>>17)+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
||||
|
||||
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:38 . Memory (MB): peak = 1581.605 ; gain = 713.645
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:45 . Memory (MB): peak = 1721.945 ; gain = 853.984
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:50 . Memory (MB): peak = 1728.258 ; gain = 860.297
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:53 . Memory (MB): peak = 1728.258 ; gain = 860.297
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:54 . Memory (MB): peak = 1728.258 ; gain = 860.297
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:55 . Memory (MB): peak = 1728.258 ; gain = 860.297
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:55 . Memory (MB): peak = 1728.258 ; gain = 860.297
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:55 . Memory (MB): peak = 1728.258 ; gain = 860.297
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:55 . Memory (MB): peak = 1728.258 ; gain = 860.297
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
DSP Final Report (the ' indicates corresponding REG is set)
|
||||
+------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
||||
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
|
||||
+------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
||||
|Execution | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|Execution | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
|Execution | PCIN>>17+A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
||||
+------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
||||
|
||||
|
||||
Report BlackBoxes:
|
||||
+------+------------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+------+------------------+----------+
|
||||
|1 |phase_locked_loop | 1|
|
||||
+------+------------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+------------------+------+
|
||||
| |Cell |Count |
|
||||
+------+------------------+------+
|
||||
|1 |phase_locked_loop | 1|
|
||||
|2 |CARRY4 | 39|
|
||||
|3 |DSP48E1 | 3|
|
||||
|4 |LUT1 | 5|
|
||||
|5 |LUT2 | 161|
|
||||
|6 |LUT3 | 230|
|
||||
|7 |LUT4 | 309|
|
||||
|8 |LUT5 | 701|
|
||||
|9 |LUT6 | 6948|
|
||||
|10 |MUXF7 | 2352|
|
||||
|11 |MUXF8 | 1088|
|
||||
|12 |FDRE | 18120|
|
||||
|13 |IBUF | 1|
|
||||
|14 |OBUF | 13|
|
||||
+------+------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:55 . Memory (MB): peak = 1728.258 ; gain = 860.297
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:53 . Memory (MB): peak = 1728.258 ; gain = 754.352
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:55 . Memory (MB): peak = 1728.258 ; gain = 860.297
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.208 . Memory (MB): peak = 1728.258 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 3482 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1728.258 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Synth Design complete | Checksum: 83c65142
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
51 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:01:01 . Memory (MB): peak = 1728.258 ; gain = 1251.520
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1728.258 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Jul 12 00:09:51 2024...
|
||||
BIN
PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb
Normal file
BIN
PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb
Normal file
Binary file not shown.
188
PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt
Normal file
188
PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt
Normal file
@@ -0,0 +1,188 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||
| Date : Fri Jul 12 00:09:51 2024
|
||||
| Host : Viviana running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb
|
||||
| Design : CPU
|
||||
| Device : xc7a35tfgg484-1
|
||||
| Speed File : -1
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+-------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------------------+-------+-------+------------+-----------+-------+
|
||||
| Slice LUTs* | 8036 | 0 | 0 | 20800 | 38.63 |
|
||||
| LUT as Logic | 8036 | 0 | 0 | 20800 | 38.63 |
|
||||
| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 |
|
||||
| Slice Registers | 18120 | 0 | 0 | 41600 | 43.56 |
|
||||
| Register as Flip Flop | 18120 | 0 | 0 | 41600 | 43.56 |
|
||||
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
|
||||
| F7 Muxes | 2352 | 0 | 0 | 16300 | 14.43 |
|
||||
| F8 Muxes | 1088 | 0 | 0 | 8150 | 13.35 |
|
||||
+-------------------------+-------+-------+------------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
Warning! LUT value is adjusted to account for LUT combining.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 18120 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 0 | 100 | 0.00 |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| DSPs | 3 | 0 | 0 | 90 | 3.33 |
|
||||
| DSP48E1 only | 3 | | | | |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Bonded IOB | 14 | 0 | 0 | 250 | 5.60 |
|
||||
| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 0 | 240 | 0.00 |
|
||||
| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 0 | 250 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 0 | 250 | 0.00 |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 0 | 20 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 0 | 5 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
|
||||
| BUFR | 0 | 0 | 0 | 20 | 0.00 |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+-------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+-------+---------------------+
|
||||
| FDRE | 18120 | Flop & Latch |
|
||||
| LUT6 | 6948 | LUT |
|
||||
| MUXF7 | 2352 | MuxFx |
|
||||
| MUXF8 | 1088 | MuxFx |
|
||||
| LUT5 | 701 | LUT |
|
||||
| LUT4 | 309 | LUT |
|
||||
| LUT3 | 230 | LUT |
|
||||
| LUT2 | 161 | LUT |
|
||||
| CARRY4 | 39 | CarryLogic |
|
||||
| OBUF | 13 | IO |
|
||||
| LUT1 | 5 | LUT |
|
||||
| DSP48E1 | 3 | Block Arithmetic |
|
||||
| IBUF | 1 | IO |
|
||||
+----------+-------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+-------------------+------+
|
||||
| Ref Name | Used |
|
||||
+-------------------+------+
|
||||
| phase_locked_loop | 1 |
|
||||
+-------------------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
10
PipelineProcessor.runs/synth_1/htr.txt
Normal file
10
PipelineProcessor.runs/synth_1/htr.txt
Normal file
@@ -0,0 +1,10 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
REM Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log CPU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
|
||||
1
PipelineProcessor.runs/synth_1/incr_synth_reason.pb
Normal file
1
PipelineProcessor.runs/synth_1/incr_synth_reason.pb
Normal file
@@ -0,0 +1 @@
|
||||
<EFBFBD> 6No compile time benefit to using incremental synthesis
|
||||
14
PipelineProcessor.runs/synth_1/vivado.jou
Normal file
14
PipelineProcessor.runs/synth_1/vivado.jou
Normal file
@@ -0,0 +1,14 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Fri Jul 12 00:08:43 2024
|
||||
# Process ID: 16484
|
||||
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
|
||||
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds
|
||||
# Journal file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1\vivado.jou
|
||||
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
|
||||
#-----------------------------------------------------------
|
||||
source CPU.tcl -notrace
|
||||
BIN
PipelineProcessor.runs/synth_1/vivado.pb
Normal file
BIN
PipelineProcessor.runs/synth_1/vivado.pb
Normal file
Binary file not shown.
@@ -13,7 +13,6 @@ verilog xil_defaultlib --include "../../../../PipelineProcessor.ip_user_files/i
|
||||
"../../../../PipelineProcessor.srcs/sources_1/new/InstFetch.v" \
|
||||
"../../../../PipelineProcessor.srcs/sources_1/new/InstructionMemory.v" \
|
||||
"../../../../PipelineProcessor.srcs/sources_1/new/MemoryAccess.v" \
|
||||
"../../../../PipelineProcessor.srcs/sources_1/new/MemoryForward.v" \
|
||||
"../../../../PipelineProcessor.srcs/sources_1/new/RegisterFile.v" \
|
||||
"../../../../PipelineProcessor.srcs/sources_1/new/WriteBack.v" \
|
||||
"../../../../PipelineProcessor.srcs/sources_1/new/CPU.v" \
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
22
PipelineProcessor.srcs/constrs_1/new/top.xdc
Normal file
22
PipelineProcessor.srcs/constrs_1/new/top.xdc
Normal file
@@ -0,0 +1,22 @@
|
||||
set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports {hardware_clk}]
|
||||
# create_clock -period 10.000 -name CLOCK -waveform {0.000 5.000} [get_ports {hardware_clk}]
|
||||
|
||||
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports {hardware_reset}]
|
||||
|
||||
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {clock_locked}]
|
||||
|
||||
# a
|
||||
set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports {bcd_control[0]}]
|
||||
# b
|
||||
set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {bcd_control[1]}]
|
||||
set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {bcd_control[2]}]
|
||||
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports {bcd_control[3]}]
|
||||
set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {bcd_control[4]}]
|
||||
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports {bcd_control[5]}]
|
||||
set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS33} [get_ports {bcd_control[6]}]
|
||||
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS33} [get_ports {bcd_control[7]}]
|
||||
# AN0, the first at the right
|
||||
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports {bcd_control[8]}]
|
||||
set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {bcd_control[9]}]
|
||||
set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {bcd_control[10]}]
|
||||
set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bcd_control[11]}]
|
||||
@@ -84,7 +84,7 @@
|
||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "50.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
@@ -154,9 +154,9 @@
|
||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "41", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "17", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
@@ -167,7 +167,7 @@
|
||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "82", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "17", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
@@ -245,8 +245,8 @@
|
||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "446.763", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "313.282", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "203.457", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "155.540", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
@@ -338,14 +338,14 @@
|
||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__10.00000______0.000______50.0______446.763____313.282", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__50.00000______0.000______50.0______203.457____155.540", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
@@ -366,7 +366,7 @@
|
||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "10.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
@@ -398,17 +398,17 @@
|
||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "41.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "17.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "82.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "17.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@@ -540,12 +540,12 @@
|
||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "0.012195121951219513", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "0.012195121951219513", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "0.012195121951219513", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.012195121951219513", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.012195121951219513", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.012195121951219513", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "0.058823529411764705", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "0.058823529411764705", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "0.058823529411764705", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.058823529411764705", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.058823529411764705", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.058823529411764705", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
@@ -566,7 +566,7 @@
|
||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "10.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
|
||||
@@ -7,11 +7,92 @@ module InstructionMemory (
|
||||
|
||||
always @(*) begin
|
||||
case (address[31:2])
|
||||
20'd0: instruction <= 32'h3c104000; // lui $s0, 0x4000
|
||||
20'd1: instruction <= 32'h20110001; // addi $s1, $zero, 1
|
||||
20'd2: instruction <= 32'hae110000; // sw $s1, 0($s0)
|
||||
20'd3: instruction <= 32'h8e120000; // lw $s2, 0($s0)
|
||||
20'd4: instruction <= 32'hae120004; // sw $s2, 4($s0)
|
||||
20'd0: instruction <= 32'h3c1d4000;
|
||||
20'd1: instruction <= 32'h23bd07ff;
|
||||
20'd2: instruction <= 32'h3c104000;
|
||||
20'd3: instruction <= 32'h22100020;
|
||||
20'd4: instruction <= 32'h2011003f;
|
||||
20'd5: instruction <= 32'hae110000;
|
||||
20'd6: instruction <= 32'h20110006;
|
||||
20'd7: instruction <= 32'hae110004;
|
||||
20'd8: instruction <= 32'h2011005b;
|
||||
20'd9: instruction <= 32'hae110008;
|
||||
20'd10: instruction <= 32'h2011004f;
|
||||
20'd11: instruction <= 32'hae11000c;
|
||||
20'd12: instruction <= 32'h20110066;
|
||||
20'd13: instruction <= 32'hae110010;
|
||||
20'd14: instruction <= 32'h2011006d;
|
||||
20'd15: instruction <= 32'hae110014;
|
||||
20'd16: instruction <= 32'h2011007d;
|
||||
20'd17: instruction <= 32'hae110018;
|
||||
20'd18: instruction <= 32'h20110007;
|
||||
20'd19: instruction <= 32'hae11001c;
|
||||
20'd20: instruction <= 32'h2011007f;
|
||||
20'd21: instruction <= 32'hae110020;
|
||||
20'd22: instruction <= 32'h2011006f;
|
||||
20'd23: instruction <= 32'hae110024;
|
||||
20'd24: instruction <= 32'h20110077;
|
||||
20'd25: instruction <= 32'hae110028;
|
||||
20'd26: instruction <= 32'h2011007c;
|
||||
20'd27: instruction <= 32'hae11002c;
|
||||
20'd28: instruction <= 32'h20110058;
|
||||
20'd29: instruction <= 32'hae110030;
|
||||
20'd30: instruction <= 32'h2011005e;
|
||||
20'd31: instruction <= 32'hae110034;
|
||||
20'd32: instruction <= 32'h20110079;
|
||||
20'd33: instruction <= 32'hae110038;
|
||||
20'd34: instruction <= 32'h20110071;
|
||||
20'd35: instruction <= 32'hae11003c;
|
||||
20'd36: instruction <= 32'h3c114000;
|
||||
20'd37: instruction <= 32'h22310010;
|
||||
20'd38: instruction <= 32'h20100a80;
|
||||
20'd39: instruction <= 32'h22100001;
|
||||
20'd40: instruction <= 32'h22040000;
|
||||
20'd41: instruction <= 32'h22250000;
|
||||
20'd42: instruction <= 32'h0c00002c;
|
||||
20'd43: instruction <= 32'h08000027;
|
||||
20'd44: instruction <= 32'h23bdffe0;
|
||||
20'd45: instruction <= 32'hafbf0004;
|
||||
20'd46: instruction <= 32'hafb00008;
|
||||
20'd47: instruction <= 32'hafb1000c;
|
||||
20'd48: instruction <= 32'hafb20010;
|
||||
20'd49: instruction <= 32'hafb30014;
|
||||
20'd50: instruction <= 32'hafb40018;
|
||||
20'd51: instruction <= 32'hafb5001c;
|
||||
20'd52: instruction <= 32'hafb60020;
|
||||
20'd53: instruction <= 32'h20900000;
|
||||
20'd54: instruction <= 32'h20b10000;
|
||||
20'd55: instruction <= 32'h3c124000;
|
||||
20'd56: instruction <= 32'h22520020;
|
||||
20'd57: instruction <= 32'h20132ed4;
|
||||
20'd58: instruction <= 32'h22140000;
|
||||
20'd59: instruction <= 32'h20160100;
|
||||
20'd60: instruction <= 32'h20150004;
|
||||
20'd61: instruction <= 32'h3288000f;
|
||||
20'd62: instruction <= 32'h00084080;
|
||||
20'd63: instruction <= 32'h02484020;
|
||||
20'd64: instruction <= 32'h8d080000;
|
||||
20'd65: instruction <= 32'h01164025;
|
||||
20'd66: instruction <= 32'hae280000;
|
||||
20'd67: instruction <= 32'h0014a102;
|
||||
20'd68: instruction <= 32'h0016b040;
|
||||
20'd69: instruction <= 32'h200800ff;
|
||||
20'd70: instruction <= 32'h2108ffff;
|
||||
20'd71: instruction <= 32'h1d00fffe;
|
||||
20'd72: instruction <= 32'h22b5ffff;
|
||||
20'd73: instruction <= 32'h1ea0fff3;
|
||||
20'd74: instruction <= 32'h2273ffff;
|
||||
20'd75: instruction <= 32'h1e60ffee;
|
||||
20'd76: instruction <= 32'h8fbf0004;
|
||||
20'd77: instruction <= 32'h8fb00008;
|
||||
20'd78: instruction <= 32'h8fb1000c;
|
||||
20'd79: instruction <= 32'h8fb20010;
|
||||
20'd80: instruction <= 32'h8fb30014;
|
||||
20'd81: instruction <= 32'h8fb40018;
|
||||
20'd82: instruction <= 32'h8fb5001c;
|
||||
20'd83: instruction <= 32'h8fb60020;
|
||||
20'd84: instruction <= 32'h23bd0020;
|
||||
20'd85: instruction <= 32'h03e00008;
|
||||
default: instruction <= 32'h00000000;
|
||||
endcase
|
||||
end
|
||||
|
||||
BIN
PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp
Normal file
BIN
PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp
Normal file
Binary file not shown.
@@ -60,20 +60,20 @@
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="235"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="276"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="1"/>
|
||||
<Option Name="WTModelSimExportSim" Val="1"/>
|
||||
<Option Name="WTQuestaExportSim" Val="1"/>
|
||||
<Option Name="WTXSimExportSim" Val="2"/>
|
||||
<Option Name="WTModelSimExportSim" Val="2"/>
|
||||
<Option Name="WTQuestaExportSim" Val="2"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="1"/>
|
||||
<Option Name="WTRivieraExportSim" Val="1"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="1"/>
|
||||
<Option Name="WTVcsExportSim" Val="2"/>
|
||||
<Option Name="WTRivieraExportSim" Val="2"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="2"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -168,13 +168,6 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/MemoryForward.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/RegisterFile.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
@@ -203,6 +196,12 @@
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/top.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
@@ -232,6 +231,14 @@
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<File Path="$PSRCDIR/utils_1/imports/synth_1/CPU.dcp">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedInSteps" Val="synth_1"/>
|
||||
<Attr Name="AutoDcp" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
@@ -269,11 +276,12 @@
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tfgg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tfgg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/CPU.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
@@ -288,7 +296,7 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tfgg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tfgg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 20 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
@@ -301,6 +309,7 @@
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
|
||||
Reference in New Issue
Block a user