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un-lock-able
2024-07-12 00:17:54 +08:00
parent c8a110e740
commit f391a7bfd2
78 changed files with 8031 additions and 103 deletions
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PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp
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PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v
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@@ -53,7 +53,7 @@
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__10.00000______0.000______50.0______446.763____313.282
// clk_out1__50.00000______0.000______50.0______203.457____155.540
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)

8
PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v
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@@ -53,7 +53,7 @@
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__10.00000______0.000______50.0______446.763____313.282
// clk_out1__50.00000______0.000______50.0______203.457____155.540
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
@@ -119,10 +119,10 @@ wire clk_in2_phase_locked_loop;
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT (41),
.DIVCLK_DIVIDE (2),
.CLKFBOUT_MULT (17),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (82),
.CLKOUT0_DIVIDE (17),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.000))

8
PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v
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@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
// Date : Tue Jul 9 23:44:24 2024
// Date : Thu Jul 11 13:35:55 2024
// Host : Viviana running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v
@@ -82,11 +82,11 @@ module phase_locked_loop_clk_wiz
(* BOX_TYPE = "PRIMITIVE" *)
PLLE2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(41),
.CLKFBOUT_MULT(17),
.CLKFBOUT_PHASE(0.000000),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE(82),
.CLKOUT0_DIVIDE(17),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT1_DIVIDE(1),
@@ -105,7 +105,7 @@ module phase_locked_loop_clk_wiz
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.DIVCLK_DIVIDE(2),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),

2
PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
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@@ -2,7 +2,7 @@
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
// Date : Tue Jul 9 23:44:24 2024
// Date : Thu Jul 11 13:35:55 2024
// Host : Viviana running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v